SAMA5 GMAC: Initial driver check-in is just the EMAC driver forced to compile with the GMAC register definitions
This commit is contained in:
Gregory Nutt
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9dd0680f0e
commit
48f1227fbf
@ -265,6 +265,178 @@ if SAMA5_GMAC
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menu "GMAC device driver options"
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config SAMA5_GMAC_NRXBUFFERS
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int "Number of RX buffers"
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default 16
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---help---
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GMAC buffer memory is segmented into 128 byte units (not
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configurable). This setting provides the number of such 128 byte
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units used for reception. This is also equal to the number of RX
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descriptors that will be allocated The selected value must be an
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even power of 2.
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config SAMA5_GMAC_NTXBUFFERS
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int "Number of TX buffers"
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default 1
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---help---
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GMAC buffer memory is segmented into full Ethernet packets (size
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NET_BUFSIZE bytes). This setting provides the number of such packets
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that can be in flight. This is also equal to the number of TX
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descriptors that will be allocated.
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config SAMA5_GMAC_PREALLOCATE
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bool "Preallocate buffers"
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default n
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---help---
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Buffer an descriptor many may either be allocated from the memory
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pool or pre-allocated to lie in .bss. This options selected pre-
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allocated buffer memory.
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config SAMA5_GMAC_NBC
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bool "Disable Broadcast"
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default n
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---help---
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Select to disable receipt of broadcast packets.
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config SAMA5_GMAC_PHYADDR
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int "PHY address"
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default 1
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---help---
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The 5-bit address of the PHY on the board. Default: 1
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config SAMA5_GMAC_PHYINIT
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bool "Board-specific PHY Initialization"
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default n
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---help---
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Some boards require specialized initialization of the PHY before it can be used.
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This may include such things as configuring GPIOs, resetting the PHY, etc. If
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SAMA5_GMAC_PHYINIT is defined in the configuration then the board specific logic must
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provide sam_phyinitialize(); The SAMA5 GMAC driver will call this function
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one time before it first uses the PHY.
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config SAMA5_GMAC_GMII
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bool "Use MII interface"
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default n
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---help---
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Support Ethernet MII interface (vs RMII).
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config SAMA5_GMAC_RGMII
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bool
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default y if !SAMA5_GMAC_GMII
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default n if SAMA5_GMAC_GMII
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config SAMA5_GMAC_AUTONEG
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bool "Use autonegotiation"
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default y
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---help---
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Use PHY autonegotiation to determine speed and mode
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config SAMA5_GMAC_ETHFD
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bool "Full duplex"
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default n
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depends on !SAMA5_GMAC_AUTONEG
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---help---
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If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select full duplex
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mode. Default: half-duplex
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config SAMA5_GMAC_ETH100MBPS
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bool "100 Mbps"
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default n
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depends on !SAMA5_GMAC_AUTONEG
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---help---
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If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
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speed. Default: 10 Mbps
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config SAMA5_GMAC_PHYSR
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int "PHY Status Register Address (decimal)"
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depends on SAMA5_GMAC_AUTONEG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. The PHY status register
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address may diff from PHY to PHY. This configuration sets the address of
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the PHY status register.
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config SAMA5_GMAC_PHYSR_ALTCONFIG
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bool "PHY Status Alternate Bit Layout"
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default n
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depends on SAMA5_GMAC_AUTONEG
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---help---
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Different PHYs present speed and mode information in different ways. Some
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will present separate information for speed and mode (this is the default).
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Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
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full/half duplex indication. This options selects an alternative representation
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where speed and mode information are combined. This might mean, for example,
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separate bits for 10HD, 100HD, 10FD and 100FD.
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config SAMA5_GMAC_PHYSR_SPEED
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hex "PHY Speed Mask"
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depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides bit mask
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for isolating the 10 or 100MBps speed indication.
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config SAMA5_GMAC_PHYSR_100MBPS
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hex "PHY 100Mbps Speed Value"
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depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides the value
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of the speed bit(s) indicating 100MBps speed.
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config SAMA5_GMAC_PHYSR_MODE
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hex "PHY Mode Mask"
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depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This provide bit mask
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for isolating the full or half duplex mode bits.
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config SAMA5_GMAC_PHYSR_FULLDUPLEX
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hex "PHY Full Duplex Mode Value"
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depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides the
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value of the mode bits indicating full duplex mode.
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config SAMA5_GMAC_PHYSR_ALTMODE
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hex "PHY Mode Mask"
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depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This provide bit mask
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for isolating the speed and full/half duplex mode bits.
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config SAMA5_GMAC_PHYSR_10HD
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hex "10MBase-T Half Duplex Value"
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depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
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under the bit mask that represents the 10Mbps, half duplex setting.
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config SAMA5_GMAC_PHYSR_100HD
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hex "100Base-T Half Duplex Value"
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depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
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under the bit mask that represents the 100Mbps, half duplex setting.
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config SAMA5_GMAC_PHYSR_10FD
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hex "10Base-T Full Duplex Value"
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depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
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under the bit mask that represents the 10Mbps, full duplex setting.
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config SAMA5_GMAC_PHYSR_100FD
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hex "100Base-T Full Duplex Value"
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depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
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---help---
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This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
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under the bit mask that represents the 100Mbps, full duplex setting.
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config SAMA5_GMAC_REGDEBUG
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bool "Register-Level Debug"
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default n
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depends on DEBUG
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---help---
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Enable very low-level register access debug. Depends on DEBUG.
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if SAMA5_EMAC
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config SAMA5_GMAC_ISETH0
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@ -272,6 +444,14 @@ config SAMA5_GMAC_ISETH0
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default y
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endif # SAMA5_EMAC
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if !SAMA5_EMAC
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config SAMA5_GMAC_ISETH0
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bool
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default y
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endif # !SAMA5_EMAC
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endmenu # GMAC device driver options
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endif # SAMA5_GMAC
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@ -451,4 +451,5 @@ struct emac_txdesc_s
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uint32_t addr; /* Buffer address */
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uint32_t status; /* TX status and controls */
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};
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H */
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@ -590,8 +590,8 @@
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#define GMAC_MAN_DATA_MASK (0x0000ffff << GMAC_MAN_DATA_SHIFT)
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# define GMAC_MAN_DATA(n) ((uint32_t)(n) << GMAC_MAN_DATA_SHIFT)
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#define GMAC_MAN_WTN_SHIFT (16) /* Bits 16-17: Must be written to b10 */
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#define GMAC_MAN_WTN_MASK (3 << GMAC_MAN_CODE_SHIFT)
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# define GMAC_MAN_WTN (2 << GMAC_MAN_CODE_SHIFT)
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#define GMAC_MAN_WTN_MASK (3 << GMAC_MAN_WTN_SHIFT)
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# define GMAC_MAN_WTN (2 << GMAC_MAN_WTN_SHIFT)
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#define GMAC_MAN_REGA_SHIFT (18) /* Bits 18-22: Register Address */
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#define GMAC_MAN_REGA_MASK (31 << GMAC_MAN_REGA_SHIFT)
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# define GMAC_MAN_REGA(n) ((uint32_t)(n) << GMAC_MAN_REGA_SHIFT)
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@ -915,4 +915,99 @@
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# define GMAC_ST2RPQ0_VLANP(n) ((n) << GMAC_ST2RPQ0_VLANP_SHIFT)
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#define GMAC_ST2RPQ0_VLANE (1 << 8) /* Bit 8: VLAN Enable */
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/* Descriptors **********************************************************************/
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/* Receive buffer descriptor: Address word */
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#define GMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=GMAC owns */
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#define GMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
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#define GMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */
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/* Receive buffer descriptor: Control word */
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#define GMACRXD_STA_FRLEN_SHIFT (0) /* Bits 0-12: Length of frame */
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#define GMACRXD_STA_FRLEN_MASK (0x00000fff << GMACRXD_STA_FRLEN_SHIFT)
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#define GMACRXD_STA_JFRLEN_SHIFT (0) /* Bits 0-13: Length of jumbo frame */
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#define GMACRXD_STA_JFRLEN_MASK (0x00001fff << GMACRXD_STA_JFRLEN_SHIFT)
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#define GMACRXD_STA_BADFCS (1 << 13) /* Bit 13: Frame had bad FCS */
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#define GMACRXD_STA_SOF (1 << 14) /* Bit 14: Start of frame */
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#define GMACRXD_STA_EOF (1 << 15) /* Bit 15: End of frame */
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#define GMACRXD_STA_CFI (1 << 16) /* Bit 16: Canonical format indicator (CFI) bit */
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#define GMACRXD_STA_VLPRIO_SHIFT (17) /* Bits 17-19: VLAN priority */
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#define GMACRXD_STA_VLPRIO_MASK (7 << GMACRXD_STA_VLANPRIO_SHIFT)
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#define GMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */
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#define GMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */
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#define GMACRXD_STA_TYPID_SHIFT (22) /* Bits 22-23: Type ID register match */
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#define GMACRXD_STA_TYPID_MASK (3 << GMACRXD_STA_TYPID_SHIFT)
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# define GMACRXD_STA_TYPID1 (0 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 1 match */
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# define GMACRXD_STA_TYPID2 (1 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 2 match */
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# define GMACRXD_STA_TYPID3 (2 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 3 match */
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# define GMACRXD_STA_TYPID4 (3 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 4 match */
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#define GMACRXD_STA_SNAP_SHIFT (22) /* Bits 22-23: Specific Address Register match */
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#define GMACRXD_STA_SNAP_MASK (3 << GMACRXD_STA_SNAP_SHIFT)
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# define GMACRXD_STA_SNAP_NOCHK (0 << GMACRXD_STA_SNAP_SHIFT) /* Checksum not checked */
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# define GMACRXD_STA_SNAP_IPCHK (1 << GMACRXD_STA_SNAP_SHIFT) /* IP header checksum checked */
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# define GMACRXD_STA_SNAP_TCPCHK (2 << GMACRXD_STA_SNAP_SHIFT) /* IP header and TCP checksum checked */
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# define GMACRXD_STA_SNAP_UDPCHK (3 << GMACRXD_STA_SNAP_SHIFT) /* IP header and UDP checksum checked */
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#define GMACRXD_STA_TYPID (1 << 24) /* Bit 24: Type ID match found */
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#define GMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */
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#define GMACRXD_STA_ADDR_SHIFT (25) /* Bits 25-26: Specific Address Register match */
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#define GMACRXD_STA_ADDR_MASK (3 << GMACRXD_STA_ADDR_SHIFT)
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# define GMACRXD_STA_ADDR1_MATCH (0 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */
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# define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */
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# define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */
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# define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */
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#define GMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific Address Register match found */
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/* Bit 28: Reserved */
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#define GMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */
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#define GMACRXD_STA_MCAST (1 << 30) /* Bit 30: Multicast hash match */
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#define GMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */
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/* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */
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/* Transmit buffer descriptor: Control word */
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#define GMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */
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#define GMACTXD_STA_BUFLEN_MASK (0x00003fff << GMACTXD_STA_BUFLEN_SHIFT)
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/* Bit 14: Reserved */
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#define GMACTXD_STA_LAST (1 << 15) /* Bit 15: Last buffer in the current frame */
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#define GMACTXD_STA_NOCRC (1 << 16) /* Bit 16: No CRC */
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/* Bits 17-19: Reserved */
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#define GMACTXD_STA_CKERR_SHIFT (20) /* Bits 20-22: Transmit checksum generation errors */
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#define GMACTXD_STA_CKERR_MASK (7 << GMACTXD_STA_CKERR_SHIFT)
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# define GMACTXD_STA_CKERR_OK (0 << GMACTXD_STA_CKERR_SHIFT) /* No Error */
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# define GMACTXD_STA_CKERR_VLAN (1 << GMACTXD_STA_CKERR_SHIFT) /* VLAN header error */
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# define GMACTXD_STA_CKERR_SNAP (2 << GMACTXD_STA_CKERR_SHIFT) /* SNAP header error */
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# define GMACTXD_STA_CKERR_IP (3 << GMACTXD_STA_CKERR_SHIFT) /* Bad IP type */
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# define GMACTXD_STA_CKERR_UNK (4 << GMACTXD_STA_CKERR_SHIFT) /* Not VLAN, SNAP or IP */
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# define GMACTXD_STA_CKERR_FRAG (5 << GMACTXD_STA_CKERR_SHIFT) /* Bad packet fragmentation */
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# define GMACTXD_STA_CKERR_PROTO (6 << GMACTXD_STA_CKERR_SHIFT) /* Not TCP or UDP */
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# define GMACTXD_STA_CKERR_END (7 << GMACTXD_STA_CKERR_SHIFT) /* Premature end of packet */
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/* Bits 23-25: Reserved */
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#define GMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision */
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#define GMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit Frame Corruption due to AHB error */
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#define GMACTXD_STA_TXUR (1 << 28) /* Bit 28: Transmit underrun */
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#define GMACTXD_STA_TXERR (1 << 29) /* Bit 29: Retry limit exceeded, transmit error detected */
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#define GMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */
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#define GMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the GMAC to read from buffer */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* Receive buffer descriptor */
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struct gmac_rxdesc_s
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{
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uint32_t addr; /* Buffer address */
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uint32_t status; /* RX status and controls */
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};
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/* Transmit buffer descriptor */
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struct gmac_txdesc_s
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{
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uint32_t addr; /* Buffer address */
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uint32_t status; /* TX status and controls */
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};
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GMAC_H */
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2942
arch/arm/src/sama5/sam_gmac.c
Normal file
2942
arch/arm/src/sama5/sam_gmac.c
Normal file
File diff suppressed because it is too large
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