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risc-v/esp32c3: Don't reserve any vectors for any special use.

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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-02-22 13:19:40 +01:00 committed by Xiang Xiao
parent 291a5755cc
commit 491a4c1ed2
1 changed files with 2 additions and 18 deletions
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20
arch/risc-v/src/esp32c3/esp32c3_vectors.S
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@ -55,25 +55,9 @@ _vector_table:
j _exception_handler
/* 29 identical entries, all pointing to the interrupt handler */
/* 31 identical entries, all pointing to the interrupt handler */
.rept (29)
.rept (31)
j _interrupt_handler
.endr
/* Call panic handler for ESP32C3_CPU_INT_T1_WDT interrupt (soc-level panic)*/
j _panic_handler
/* Call panic handler for ESP32C3_CPU_INT_CACHEERR interrupt (soc-level panic)*/
j _panic_handler
/****************************************************************************
* Name: _panic_handler
****************************************************************************/
.type _panic_handler, @function
_panic_handler:
j _panic_handler