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First round of changes made during debug

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2880 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-08-22 16:46:42 +00:00
parent c530bd319a
commit 4920cce713
4 changed files with 38 additions and 17 deletions
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8
ChangeLog
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@ -1199,11 +1199,11 @@
* examples/uip/main.c - if DHCPC is selected, this example now shows
the assigned IP address.
* arch/arm/src/lm3s and arch/arm/include/lm3s - Definitions for the
TI LM3S9B96 contributed by Tiago Maluta.
TI LM3S9B96 contributed by Tiago Maluta.
* arch/arm/src/lm3s/lm3s_gioirq.c - Fix a logic error in the address
table lookup.
* arch/arm/src/lm3s/lm3s_gioirq.c - Also needs to enable the global
GPIO interrupts.
GPIO interrupts.
* arch/arm/src/lm3s/lm3s_internal.h and lm3s_gpio.c - Fixed the encoding
of GPIO port number that limited support for GPIO ports to 8
* sched/pg_*.c and *.c and include/nuttx/page.h - Implemented the
@ -1211,3 +1211,7 @@
http://www.nuttx.org/NuttXDemandPaging.html for details.
* drivers/usbdev/usbdev_serial.c - Correct compilation errors that
occur if CONFIG_USBDEV_DUALSPEED is selected.
* configs/ea3131/pgnsh - Add an NSH configuration with on-demand paging
enabled. This is not expected to be a functionality configuration (at
least not yet); it was created in order to debug the on-demand paging
feature.

17
arch/arm/src/arm/pg_macros.h
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@ -138,14 +138,16 @@
#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
/* We position the paged region PTEs immediately after the locked
* region PTEs.
* region PTEs. NOTE that the size of the paged regions is much
* larger than the size of the physical paged region. That is the
* core of what the On-Demanding Paging feature provides.
*/
#define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2))
#define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
#define PG_L2_PAGED_PADDR (PG_L2_BASE_PADDR + PG_L2_LOCKED_SIZE)
#define PG_L2_PAGED_VADDR (PG_L2_BASE_VADDR + PG_L2_LOCKED_SIZE)
#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NPPAGED)
#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NVPAGED)
/* This describes the overall text region */
@ -346,16 +348,17 @@
orr \tmp, \ppage, \mmuflags
/* Write value into table at the current table address */
/* Write value into table at the current table address
* (and increment the L2 page table address by 4)
*/
str \tmp, [\l2], #4
/* Update the physical addresses that will correspond to the next
/* Update the physical address that will correspond to the next
* table entry.
*/
add \ppage, \ppage, #CONFIG_PAGING_PAGESIZE
add \l2, \l2, #4
/* Decrement the number of pages written */
@ -417,7 +420,9 @@
orr \tmp, \l2, \mmuflags
/* Write the value into the L1 table at the correct offset. */
/* Write the value into the L1 table at the correct offset.
* (and increment the L1 table address by 4)
*/
str \tmp, [\l1], #4

26
arch/arm/src/arm/up_head.S
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@ -188,17 +188,20 @@ __start:
* We could probably make the the pg_l1span and pg_l2map macros into
* call-able subroutines, but we would have to be carefully during
* this phase while we are operating in a physical address space.
*
* NOTE: That the value of r5 (L1 table base address) must be
* preserved through the following.
*/
adr r0, .Ltxtspan
ldmia r0, {r0, r1, r2, r3}
pg_l1span r0, r1, r2, r3, r4
pg_l1span r0, r1, r2, r3, r5
/* Then populate the L2 table for the locked text region only. */
adr r0, .Ltxtmap
ldmia r0, {r0, r1, r2, r3}
pg_l2map r0, r1, r2, r3, r4
pg_l2map r0, r1, r2, r3, r5
/* Make sure that the page table is itself mapped and and read/write-able.
* First, populate the L1 table:
@ -206,19 +209,22 @@ __start:
adr r0, .Lptabspan
ldmia r0, {r0, r1, r2, r3}
pg_l1span r0, r1, r2, r3, r4
pg_l1span r0, r1, r2, r3, r5
/* Then populate the L2 table. */
adr r0, .Lptabmap
ldmia r0, {r0, r1, r2, r3}
pg_l2map r0, r1, r2, r3, r4
pg_l2map r0, r1, r2, r3, r5
#else
/* Create a virtual single section mapping for the first MB of the .text
* address space. Now, we have the first 1MB mapping to both phyical and
* virtual addresses. The rest of the .text mapping will be completed in
* .Lvstart once we have moved the physical mapping out of the way.
*
* Here we expect to have:
* r4 = Address of the base of the L1 table
*/
ldr r2, .LCvpgtable /* r2=virt. page table */
@ -231,7 +237,11 @@ __start:
#endif
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* The following logic will set up the ARM920/ARM926 for normal operation */
/* The following logic will set up the ARM920/ARM926 for normal operation.
*
* Here we expect to have:
* r4 = Address of the base of the L1 table
*/
mov r0, #0
mcr p15, 0, r0, c7, c7 /* Invalidate I,D caches */
@ -317,8 +327,10 @@ __start:
/* Get TMP=2 Processor ID register */
mrc p15, 0, r1, c0, c0, 0 /* read id reg */
mov r1, r1
mov r1, r1
mov r1,r1 /* Null-avoiding nop */
mov r1,r1 /* Null-avoiding nop */
/* And "jump" to .Lvstart */
mov pc, lr

4
arch/arm/src/lpc313x/lpc313x_memorymap.h
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@ -251,7 +251,7 @@
# define NUTTX_START_VADDR LPC313X_EXTSDRAM0_VSECTION
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
# define NUTTX_START_VADDR LPC313X_EXTSRAM0_VADDR
#else /* CONFIG_BOOT_RUNFROMISRAM */
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
# define NUTTX_START_VADDR LPC313X_INTSRAM0_VADDR
#endif
@ -284,7 +284,7 @@
* where the vector table was place.
*/
# ifdef CONFIG_ARCH_ROMPGTABLE /* Vectors located at 0x0000:0000 */
# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
/* In this case, ISRAM0 will be shadowed at address 0x0000:0000. The page
* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a LPC3130)