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arm64/irq: Add mask for DAIF and SPSR DAIF bits

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Use them for critical section handling, removes a bit of copy&pasted
code behind CONFIG_ARM64_DECODEFIQ flag
This commit is contained in:
Ville Juven 2024-09-06 14:43:10 +03:00 committed by Xiang Xiao
parent fc5a029e44
commit 498275ca43
2 changed files with 14 additions and 30 deletions
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24
arch/arm64/include/irq.h
View File

@ -220,6 +220,14 @@
#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
#ifdef CONFIG_ARM64_DECODEFIQ
# define IRQ_DAIF_MASK (3)
#else
# define IRQ_DAIF_MASK (2)
#endif
#define IRQ_SPSR_MASK (IRQ_DAIF_MASK << 6)
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -349,13 +357,9 @@ static inline irqstate_t up_irq_save(void)
__asm__ __volatile__
(
"mrs %0, daif\n"
#ifdef CONFIG_ARM64_DECODEFIQ
"msr daifset, #3\n"
#else
"msr daifset, #2\n"
#endif
"msr daifset, %1\n"
: "=r" (flags)
:
: "i" (IRQ_DAIF_MASK)
: "memory"
);
@ -371,13 +375,9 @@ static inline irqstate_t up_irq_enable(void)
__asm__ __volatile__
(
"mrs %0, daif\n"
#ifdef CONFIG_ARM64_DECODEFIQ
"msr daifclr, #3\n"
#else
"msr daifclr, #2\n"
#endif
"msr daifclr, %1\n"
: "=r" (flags)
:
: "i" (IRQ_DAIF_MASK)
: "memory"
);
return flags;

20
arch/arm64/src/common/arm64_vectors.S
View File

@ -56,22 +56,6 @@
.endm
.macro enable_irq
#ifdef CONFIG_ARM64_DECODEFIQ
msr daifclr, #3
#else
msr daifclr, #2
#endif
.endm
.macro disable_irq
#ifdef CONFIG_ARM64_DECODEFIQ
msr daifset, #3
#else
msr daifset, #2
#endif
.endm
/****************************************************************************
* Public Functions
****************************************************************************/
@ -238,9 +222,9 @@ SECTION_FUNC(text, arm64_sync_exc)
/* Call dispatch_syscall() on the kernel stack with interrupts enabled */
enable_irq
msr daifclr, #IRQ_DAIF_MASK /* Re-enable interrupts */
bl dispatch_syscall
disable_irq
msr daifset, #IRQ_DAIF_MASK /* Disable interrupts */
/* Save the return value into the user context */