Merged in OSer916/nuttx/stm32f746g-disco_sai (pull request #1081)
boards/arm/stm32f7/stm32f746g-disco: add SAI driver Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
OSer
Gregory Nutt
parent
d2af57169b
commit
498fb6d15f
@ -732,6 +732,8 @@ config STM32F7_STM32F746XX
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select STM32F7_HAVE_CAN2
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select STM32F7_HAVE_SPI4
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select STM32F7_HAVE_EXTERNAL_ULPI
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select STM32F7_HAVE_SAI1
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select STM32F7_HAVE_SAI2
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config STM32F7_STM32F756XX
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bool
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@ -1236,6 +1238,15 @@ config STM32F7_HAVE_EXTERNAL_ULPI
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bool
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default n
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config STM32F7_HAVE_SAI1
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bool
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default n
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config STM32F7_HAVE_SAI2
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bool
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default n
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# These "hidden" settings are the OR of individual peripheral selections
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# indicating that the general capability is required.
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@ -1491,12 +1502,48 @@ config STM32F7_RNG
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config STM32F7_SAI1
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bool "SAI1"
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default n
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depends on STM32F7_HAVE_SAI1
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config STM32F7_SAI1_A
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bool "SAI1 Block A"
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default n
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select AUDIO
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select I2S
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select SCHED_HPWORK
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select STM32F7_SAI
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depends on STM32F7_SAI1
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config STM32F7_SAI1_B
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bool "SAI1 Block B"
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default n
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select AUDIO
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select I2S
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select SCHED_HPWORK
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select STM32F7_SAI
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depends on STM32F7_SAI1
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config STM32F7_SAI2
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bool "SAI2"
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default n
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select STM32F7_HAVE_SAI2
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config STM32F7_SAI2_A
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bool "SAI2 Block A"
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default n
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select AUDIO
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select I2S
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select SCHED_HPWORK
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select STM32F7_SAI
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depends on STM32F7_SAI2
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config STM32F7_SAI2_B
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bool "SAI2 Block B"
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default n
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select AUDIO
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select I2S
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select SCHED_HPWORK
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select STM32F7_SAI
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depends on STM32F7_SAI2
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config STM32F7_SDMMC1
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bool "SDMMC1"
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@ -5763,4 +5810,68 @@ endchoice
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endmenu
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menu "SAI Configuration"
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depends on STM32F7_SAI
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choice
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prompt "Operation mode"
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default STM32F7_SAI_DMA
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---help---
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Select the operation mode the SAI driver should use.
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config STM32F7_SAI_POLLING
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bool "Polling"
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---help---
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The SAI registers are polled for events.
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config STM32F7_SAI_INTERRUPTS
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bool "Interrupt"
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---help---
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Select to enable interrupt driven SAI support.
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config STM32F7_SAI_DMA
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bool "DMA"
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---help---
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Use DMA to improve SAI transfer performance.
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endchoice # Operation mode
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choice
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prompt "SAI1 synchronization enable"
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default STM32F7_SAI1_BOTH_ASYNC
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depends on STM32F7_SAI1_A && STM32F7_SAI1_B
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---help---
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Select the synchronization mode of the SAI sub-blocks
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config STM32F7_SAI1_BOTH_ASYNC
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bool "Both asynchronous"
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config STM32F7_SAI1_A_SYNC_WITH_B
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bool "Block A is synchronous with Block B"
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config STM32F7_SAI1_B_SYNC_WITH_A
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bool "Block B is synchronous with Block A"
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endchoice # SAI1 synchronization enable
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choice
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prompt "SAI2 synchronization enable"
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default STM32F7_SAI2_BOTH_ASYNC
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depends on STM32F7_SAI2_A && STM32F7_SAI2_B
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---help---
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Select the synchronization mode of the SAI sub-blocks
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config STM32F7_SAI2_BOTH_ASYNC
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bool "Both asynchronous"
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config STM32F7_SAI2_A_SYNC_WITH_B
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bool "Block A is synchronous with Block B"
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config STM32F7_SAI2_B_SYNC_WITH_A
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bool "Block B is synchronous with Block A"
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endchoice # SAI2 synchronization enable
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endmenu
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endif # ARCH_CHIP_STM32F7
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@ -237,6 +237,10 @@ ifeq ($(CONFIG_STM32F7_CAN),y)
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CHIP_CSRCS += stm32_can.c
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endif
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ifeq ($(CONFIG_STM32F7_SAI),y)
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CHIP_CSRCS += stm32_sai.c
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endif
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ifeq ($(CONFIG_PWM),y)
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CHIP_CSRCS += stm32_pwm.c
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endif
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259
arch/arm/src/stm32f7/hardware/stm32_sai.h
Normal file
259
arch/arm/src/stm32f7/hardware/stm32_sai.h
Normal file
@ -0,0 +1,259 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/hardware/stm32_sai.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SAI_H
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#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SAI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32F7_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
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#define STM32F7_SAI_A_OFFSET 0x0004
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#define STM32F7_SAI_B_OFFSET 0x0024
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#define STM32F7_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */
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#define STM32F7_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */
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#define STM32F7_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */
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#define STM32F7_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */
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#define STM32F7_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */
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#define STM32F7_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */
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#define STM32F7_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */
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#define STM32F7_SAI_DR_OFFSET 0x001c /* SAI Data Register A */
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/* Register Addresses ***************************************************************/
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#define STM32F7_SAI1_GCR (STM32_SAI1_BASE+STM32F7_SAI_GCR_OFFSET)
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#define STM32F7_SAI1_A_BASE (STM32_SAI1_BASE+STM32F7_SAI_A_OFFSET)
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#define STM32F7_SAI1_B_BASE (STM32_SAI1_BASE+STM32F7_SAI_B_OFFSET)
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#define STM32F7_SAI1_ACR1 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR1_OFFSET)
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#define STM32F7_SAI1_ACR2 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR2_OFFSET)
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#define STM32F7_SAI1_AFRCR (STM32F7_SAI1_A_BASE+STM32F7_SAI_FRCR_OFFSET)
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#define STM32F7_SAI1_ASLOTR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SLOTR_OFFSET)
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#define STM32F7_SAI1_AIM (STM32F7_SAI1_A_BASE+STM32F7_SAI_IM_OFFSET)
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#define STM32F7_SAI1_ASR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SR_OFFSET)
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#define STM32F7_SAI1_ACLRFR (STM32F7_SAI1_A_BASE+STM32F7_SAI_CLRFR_OFFSET)
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#define STM32F7_SAI1_ADR (STM32F7_SAI1_A_BASE+STM32F7_SAI_DR_OFFSET)
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#define STM32F7_SAI1_BCR1 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR1_OFFSET)
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#define STM32F7_SAI1_BCR2 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR2_OFFSET)
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#define STM32F7_SAI1_BFRCR (STM32F7_SAI1_B_BASE+STM32F7_SAI_FRCR_OFFSET)
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#define STM32F7_SAI1_BSLOTR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SLOTR_OFFSET)
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#define STM32F7_SAI1_BIM (STM32F7_SAI1_B_BASE+STM32F7_SAI_IM_OFFSET)
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#define STM32F7_SAI1_BSR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SR_OFFSET)
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#define STM32F7_SAI1_BCLRFR (STM32F7_SAI1_B_BASE+STM32F7_SAI_CLRFR_OFFSET)
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#define STM32F7_SAI1_BDR (STM32F7_SAI1_B_BASE+STM32F7_SAI_DR_OFFSET)
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#define STM32F7_SAI2_GCR (STM32_SAI2_BASE+STM32F7_SAI_GCR_OFFSET)
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#define STM32F7_SAI2_A_BASE (STM32_SAI2_BASE+STM32F7_SAI_A_OFFSET)
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#define STM32F7_SAI2_B_BASE (STM32_SAI2_BASE+STM32F7_SAI_B_OFFSET)
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#define STM32F7_SAI2_ACR1 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR1_OFFSET)
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#define STM32F7_SAI2_ACR2 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR2_OFFSET)
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#define STM32F7_SAI2_AFRCR (STM32F7_SAI2_A_BASE+STM32F7_SAI_FRCR_OFFSET)
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#define STM32F7_SAI2_ASLOTR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SLOTR_OFFSET)
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#define STM32F7_SAI2_AIM (STM32F7_SAI2_A_BASE+STM32F7_SAI_IM_OFFSET)
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#define STM32F7_SAI2_ASR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SR_OFFSET)
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#define STM32F7_SAI2_ACLRFR (STM32F7_SAI2_A_BASE+STM32F7_SAI_CLRFR_OFFSET)
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#define STM32F7_SAI2_ADR (STM32F7_SAI2_A_BASE+STM32F7_SAI_DR_OFFSET)
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#define STM32F7_SAI2_BCR1 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR1_OFFSET)
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#define STM32F7_SAI2_BCR2 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR2_OFFSET)
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#define STM32F7_SAI2_BFRCR (STM32F7_SAI2_B_BASE+STM32F7_SAI_FRCR_OFFSET)
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#define STM32F7_SAI2_BSLOTR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SLOTR_OFFSET)
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#define STM32F7_SAI2_BIM (STM32F7_SAI2_B_BASE+STM32F7_SAI_IM_OFFSET)
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#define STM32F7_SAI2_BSR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SR_OFFSET)
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#define STM32F7_SAI2_BCLRFR (STM32F7_SAI2_B_BASE+STM32F7_SAI_CLRFR_OFFSET)
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#define STM32F7_SAI2_BDR (STM32F7_SAI2_B_BASE+STM32F7_SAI_DR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* SAI Global Configuration Register */
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#define SAI_GCR_SYNCIN_SHIFT (0) /* Bits 0-1: Synchronization inputs */
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#define SAI_GCR_SYNCIN_MASK (3 << SAI_GCR_SYNCIN_SHIFT)
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# define SAI_GCR_SYNCIN(n) ((uint32_t)(n) << SAI_GCR_SYNCIN_SHIFT)
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/* Bits 2-3: Reserved */
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#define SAI_GCR_SYNCOUT_SHIFT (4) /* Bits 4-5: Synchronization outputs */
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#define SAI_GCR_SYNCOUT_MASK (3 << SAI_GCR_SYNCOUT_SHIFT)
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# define SAI_GCR_SYNCOUT ((uint32_t)(n) << SAI_GCR_SYNCOUT_SHIFT)
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/* Bits 6-31: Reserved */
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/* SAI Configuration Register 1 */
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#define SAI_CR1_MODE_SHIFT (0) /* Bits 0-1: SAI audio block mode */
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#define SAI_CR1_MODE_MASK (3 << SAI_CR1_MODE_SHIFT)
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# define SAI_CR1_MODE_MASTER_TX (0 << SAI_CR1_MODE_SHIFT) /* Master transmitter */
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# define SAI_CR1_MODE_MASTER_RX (1 << SAI_CR1_MODE_SHIFT) /* Master receiver */
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# define SAI_CR1_MODE_SLAVE_TX (2 << SAI_CR1_MODE_SHIFT) /* Slave transmitter */
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# define SAI_CR1_MODE_SLAVE_RX (3 << SAI_CR1_MODE_SHIFT) /* Slave receiver */
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#define SAI_CR1_PRTCFG_SHIFT (2) /* Bits 2-3: Protocol configuration */
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#define SAI_CR1_PRTCFG_MASK (3 << SAI_CR1_PRTCFG_SHIFT)
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# define SAI_CR1_PRTCFG_FREE (0 << SAI_CR1_PRTCFG_SHIFT) /* Free protocol */
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# define SAI_CR1_PRTCFG_SPDIF (1 << SAI_CR1_PRTCFG_SHIFT) /* SPDIF protocol */
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# define SAI_CR1_PRTCFG_AC97 (2 << SAI_CR1_PRTCFG_SHIFT) /* AC97 protocol */
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/* Bit 4: Reserved */
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#define SAI_CR1_DS_SHIFT (5) /* Bits 5-7: Data size */
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#define SAI_CR1_DS_MASK (7 << SAI_CR1_DS_SHIFT)
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# define SAI_CR1_DS_8BITS (2 << SAI_CR1_DS_SHIFT) /* 8 bits */
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# define SAI_CR1_DS_10BITS (3 << SAI_CR1_DS_SHIFT) /* 10 bits */
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# define SAI_CR1_DS_16BITS (4 << SAI_CR1_DS_SHIFT) /* 16 bits */
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# define SAI_CR1_DS_20BITS (5 << SAI_CR1_DS_SHIFT) /* 20 bits */
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# define SAI_CR1_DS_24BITS (6 << SAI_CR1_DS_SHIFT) /* 24 bits */
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# define SAI_CR1_DS_32BITS (7 << SAI_CR1_DS_SHIFT) /* 32 bits */
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#define SAI_CR1_LSBFIRST (1 << 8) /* Bit 8: Least significant bit first */
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#define SAI_CR1_CKSTR (1 << 9) /* Bit 9: Clock strobing edge */
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#define SAI_CR1_SYNCEN_SHIFT (10) /* Bits 10-11: Synchronization enable */
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#define SAI_CR1_SYNCEN_MASK (3 << SAI_CR1_SYNCEN_SHIFT)
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# define SAI_CR1_SYNCEN_ASYNCH (0 << SAI_CR1_SYNCEN_SHIFT) /* Asynchronous mode */
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# define SAI_CR1_SYNCEN_INTERNAL (1 << SAI_CR1_SYNCEN_SHIFT) /* Synchronous with other internal sub-block */
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# define SAI_CR1_SYNCEN_EXTERNAL (2 << SAI_CR1_SYNCEN_SHIFT) /* Aynchronous with external SAI peripheral */
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#define SAI_CR1_MONO (1 << 12) /* Bit 12: Mono mode */
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#define SAI_CR1_OUTDRIV (1 << 13) /* Bit 13: Output drive */
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/* Bits 14-15: Reserved */
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#define SAI_CR1_SAIEN (1 << 16) /* Bit 16: Audio block enable */
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#define SAI_CR1_DMAEN (1 << 17) /* Bit 17: DMA enable */
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/* Bit 18: Reserved */
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#define SAI_CR1_NODIV (1 << 19) /* Bit 19: No divider */
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#define SAI_CR1_MCKDIV_SHIFT (20) /* Bits 20-23: Master clock divider */
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#define SAI_CR1_MCKDIV_MASK (15 << SAI_CR1_MCKDIV_SHIFT)
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# define SAI_CR1_MCKDIV(n) ((uint32_t)(n) << SAI_CR1_MCKDIV_SHIFT)
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/* Bits 24-31: Reserved */
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/* SAI Configuration Register 2 */
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#define SAI_CR2_FTH_SHIFT (0) /* Bits 0-2: FIFO threshold */
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#define SAI_CR2_FTH_MASK (7 << SAI_CR2_FTH_SHIFT)
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# define SAI_CR2_FTH_EMPTY (0 << SAI_CR2_FTH_SHIFT) /* FIFO empty */
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# define SAI_CR2_FTH_1QF (1 << SAI_CR2_FTH_SHIFT) /* 1/4 FIFO */
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# define SAI_CR2_FTH_HF (2 << SAI_CR2_FTH_SHIFT) /* 1/2 FIFO */
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# define SAI_CR2_FTH_3QF (3 << SAI_CR2_FTH_SHIFT) /* 3/4 FIFO */
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# define SAI_CR2_FTH_FULL (4 << SAI_CR2_FTH_SHIFT) /* FIFO full */
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#define SAI_CR2_FFLUSH (1 << 3) /* Bit 3: FIFO flush */
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#define SAI_CR2_TRIS (1 << 4) /* Bit 4: Tristate management on data line */
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#define SAI_CR2_MUTE (1 << 5) /* Bit 5: Mute */
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#define SAI_CR2_MUTEVAL (1 << 6) /* Bit 6: Mute value */
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#define SAI_CR2_MUTECNT_SHIFT (7) /* Bits 7-12: Mute counter */
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#define SAI_CR2_MUTECNT_MASK (0x3f << SAI_CR2_MUTECNT_SHIFT)
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# define SAI_CR2_MUTECNT(n) ((uint32_t)(n) << SAI_CR2_MUTECNT_SHIFT)
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#define SAI_CR2_CPL (1 << 13) /* Bit 13: Complement */
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#define SAI_CR2_COMP_SHIFT (14) /* Bits 14-15: Companding mode */
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#define SAI_CR2_COMP_MASK (3 << SAI_CR2_COMP_SHIFT)
|
||||
# define SAI_CR2_COMP_NONE (0 << SAI_CR2_COMP_SHIFT) /* No companding algorithm */
|
||||
# define SAI_CR2_COMP_ULAW (2 << SAI_CR2_COMP_SHIFT) /* μ-Law algorithm */
|
||||
# define SAI_CR2_COMP_ALAW (3 << SAI_CR2_COMP_SHIFT) /* A-Law algorithm */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* SAI Frame Configuration Register */
|
||||
|
||||
#define SAI_FRCR_FRL_SHIFT (0) /* Bits 0-7: Frame length */
|
||||
#define SAI_FRCR_FRL_MASK (0xff << SAI_FRCR_FRL_SHIFT)
|
||||
# define SAI_FRCR_FRL(n) ((uint32_t)((n) - 1) << SAI_FRCR_FRL_SHIFT)
|
||||
#define SAI_FRCR_FSALL_SHIFT (8) /* Bits 8-14: Frame synchronization active level length */
|
||||
#define SAI_FRCR_FSALL_MASK (0x7f << SAI_FRCR_FSALL_SHIFT)
|
||||
# define SAI_FRCR_FSALL(n) ((uint32_t)((n) - 1) << SAI_FRCR_FSALL_SHIFT)
|
||||
#define SAI_FRCR_FSDEF (1 << 16) /* Bit 16: Frame synchronization definition */
|
||||
# define SAI_FRCR_FSDEF_SF (0) /* FS signal is a start frame signal */
|
||||
# define SAI_FRCR_FSDEF_CHID SAI_FRCR_FSDEF /* FS signal is a start of frame + channel side ID */
|
||||
#define SAI_FRCR_FSPOL (1 << 17) /* Bit 17: Frame synchronization polarity */
|
||||
# define SAI_FRCR_FSPOL_LOW (0) /* FS is active low */
|
||||
# define SAI_FRCR_FSPOL_HIGH SAI_FRCR_FSPOL /* FS is active high */
|
||||
#define SAI_FRCR_FSOFF (1 << 18) /* Bit 18: Frame synchronization offset */
|
||||
# define SAI_FRCR_FSOFF_FB (0) /* FS on first bit of slot 0 */
|
||||
# define SAI_FRCR_FSOFF_BFB SAI_FRCR_FSOFF /* FS one bit before first bit of slot 0 */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
/* SAI Slot Register */
|
||||
|
||||
#define SAI_SLOTR_FBOFF_SHIFT (0) /* Bits 0-4: First bit offset */
|
||||
#define SAI_SLOTR_FBOFF_MASK (31 << SAI_SLOTR_FBOFF_SHIFT)
|
||||
# define SAI_SLOTR_FBOFF(n) ((uint32_t)(n) << SAI_SLOTR_FBOFF_SHIFT)
|
||||
/* Bit 5: Reserved */
|
||||
#define SAI_SLOTR_SLOTSZ_SHIFT (6) /* Bits 6-7: Slot size */
|
||||
#define SAI_SLOTR_SLOTSZ_MASK (3 << SAI_SLOTR_SLOTSZ_SHIFT)
|
||||
# define SAI_SLOTR_SLOTSZ_DATA (0 << SAI_SLOTR_SLOTSZ_SHIFT) /* Same as data size */
|
||||
# define SAI_SLOTR_SLOTSZ_16BIT (1 << SAI_SLOTR_SLOTSZ_SHIFT) /* 16-bit */
|
||||
# define SAI_SLOTR_SLOTSZ_32BIT (2 << SAI_SLOTR_SLOTSZ_SHIFT) /* 32-bit */
|
||||
#define SAI_SLOTR_NBSLOT_SHIFT (8) /* Bits 8-11: Number of slots in an audio frame */
|
||||
#define SAI_SLOTR_NBSLOT_MASK (15 << SAI_SLOTR_NBSLOT_SHIFT)
|
||||
# define SAI_SLOTR_NBSLOT(n) ((uint32_t)((n) - 1) << SAI_SLOTR_NBSLOT_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define SAI_SLOTR_SLOTEN_SHIFT (16) /* Bits 16-31: Slot enable */
|
||||
#define SAI_SLOTR_SLOTEN_MASK (0xffff << SAI_SLOTR_SLOTEN_SHIFT)
|
||||
# define SAI_SLOTR_SLOTEN(n) ((uint32_t)(n) << SAI_SLOTR_SLOTEN_SHIFT)
|
||||
# define SAI_SLOTR_SLOTEN_0 (1 << 16) /* Bit 16: Slot 0 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_1 (1 << 17) /* Bit 17: Slot 1 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_2 (1 << 18) /* Bit 18: Slot 2 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_3 (1 << 19) /* Bit 19: Slot 3 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_4 (1 << 20) /* Bit 20: Slot 4 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_5 (1 << 21) /* Bit 21: Slot 5 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_6 (1 << 22) /* Bit 22: Slot 6 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_7 (1 << 23) /* Bit 23: Slot 7 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_8 (1 << 24) /* Bit 24: Slot 8 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_9 (1 << 25) /* Bit 25: Slot 9 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_10 (1 << 26) /* Bit 26: Slot 10 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_11 (1 << 27) /* Bit 27: Slot 11 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_12 (1 << 28) /* Bit 28: Slot 12 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_13 (1 << 29) /* Bit 29: Slot 13 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_14 (1 << 30) /* Bit 30: Slot 14 Enabled */
|
||||
# define SAI_SLOTR_SLOTEN_15 (1 << 31) /* Bit 31: Slot 15 Enabled */
|
||||
|
||||
/* SAI Interrupt Mask Register 2, SAI Status Register, and SAI Clear Flag Register */
|
||||
|
||||
#define SAI_INT_OVRUDR (1 << 0) /* Bit 0: Overrun/underrun interrupt */
|
||||
#define SAI_INT_MUTEDET (1 << 1) /* Bit 1: Mute detection interrupt */
|
||||
#define SAI_INT_WCKCFG (1 << 2) /* Bit 2: Wrong clock configuration interrupt */
|
||||
#define SAI_INT_FREQ (1 << 3) /* Bit 3: FIFO request interrupt (not CLRFFR) */
|
||||
#define SAI_INT_CNRDY (1 << 4) /* Bit 4: Codec not ready interrupt (AC97). */
|
||||
#define SAI_INT_AFSDET (1 << 5) /* Bit 5: Anticipated frame synchronization detection interrupt */
|
||||
#define SAI_INT_LFSDET (1 << 6) /* Bit 6: Late frame synchronization detection interrupt */
|
||||
/* Bits 7-31: Reserved */
|
||||
|
||||
/* SAI Data Register (32-bit data) */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SAI_H */
|
||||
@ -780,41 +780,41 @@
|
||||
|
||||
/* Serial Audio Interface */
|
||||
|
||||
#define GPIO_SAI1_FS_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SAI1_FS_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_SAI1_MCLK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_SAI1_SCK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_B_4 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SAI2_MCLK_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_SAI2_SCK_B_3 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_SAI1_FS_A (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_SAI1_FS_B (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_SAI1_MCLK_A (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_SAI1_SCK_A (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN2)
|
||||
#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_SAI2_FS_B_4 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_SAI2_MCLK_B_4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_SAI2_SCK_B_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
|
||||
/* SD/MMC
|
||||
*
|
||||
|
||||
1732
arch/arm/src/stm32f7/stm32_sai.c
Normal file
1732
arch/arm/src/stm32f7/stm32_sai.c
Normal file
File diff suppressed because it is too large
Load Diff
94
arch/arm/src/stm32f7/stm32_sai.h
Normal file
94
arch/arm/src/stm32f7/stm32_sai.h
Normal file
@ -0,0 +1,94 @@
|
||||
/******************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_sai.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Copyright (c) 2016 Motorola Mobility, LLC. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_SAI_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_SAI_H
|
||||
|
||||
/******************************************************************************
|
||||
* Included Files
|
||||
******************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_sai.h"
|
||||
|
||||
#include <nuttx/audio/i2s.h>
|
||||
|
||||
/******************************************************************************
|
||||
* Pre-processor definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define SAI1_BLOCK_A 0
|
||||
#define SAI1_BLOCK_B 1
|
||||
#define SAI2_BLOCK_A 2
|
||||
#define SAI2_BLOCK_B 3
|
||||
|
||||
/******************************************************************************
|
||||
* Public Function Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_sai_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SAI block
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - I2S interface number (identifying the "logical" SAI interface)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2S device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct i2s_dev_s *stm32_sai_initialize(int intf);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_SAI_H */
|
||||
Loading…
Reference in New Issue
Block a user