diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index f60e31883f..5f34311794 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -457,7 +457,7 @@ __start: orr r0, r0, #(SCTLR_V) #endif - /* CR_RR - Round Robin cache replacement + /* Round Robin cache replacement * * SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random * replacement strategy. @@ -466,7 +466,7 @@ __start: #ifndef CPU_CACHE_ROUND_ROBIN #endif - /* CR_C - Dcache enable + /* Dcache enable * * SCTLR_C Bit 2: DCache enable */ @@ -475,7 +475,7 @@ __start: orr r0, r0, #(SCTLR_C) #endif - /* CR_C - Icache enable + /* Icache enable * * SCTLR_I Bit 12: ICache enable */ @@ -484,7 +484,7 @@ __start: orr r0, r0, #(SCTLR_I) #endif - /* CR_A - Alignment abort enable + /* Alignment abort enable * * SCTLR_A Bit 1: Strict alignment enabled */ @@ -493,6 +493,18 @@ __start: orr r0, r0, #(SCTLR_A) #endif + /* AP[0:2] Permissions model + * + * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value). + * + * When AFE=1, the page table AP[0] is used as an access flag and AP[2:1] + * control. When AFE=0, AP[2:0] control access permissions. + */ + +#ifdef CONFIG_AFE_ENABLE + orr r0, r0, #(SCTLR_AFE) +#endif + /* Then write the configured control register */ mcr CP15_SCTLR(r0) /* Write control reg */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 08fa9231bd..7e684fe363 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -310,28 +310,57 @@ #define PMD_SSECT_XBA1_SHIFT (5) /* Bits 24-31: Extended base address, PA[31:24] */ #define PMD_SSECT_XBA1_MASK (15 << PMD_SSECT_XBA1_SHIFT) -/* Level 1 Section/Supersection Access Permissions: +/* Level 1 Section/Supersection Access Permissions. * - * WR - Read/write addess allowed - * R - Read-only access allowed - * 0,1,2 - At PL0, PL1, and/or PL2 + * Paragraph B3.7.1, Access permissions: "If address translation is using + * the Short-descriptor translation table format, it must set SCTLR.AFE to + * 1 to enable use of the Access flag.... Setting this bit to 1 redefines + * the AP[0] bit in the translation table descriptors as an Access flag, and + * limits the access permissions information in the translation table + * descriptors to AP[2:1]... * - * PL0 - User privilege level - * PL1 - Privilieged mode - * PL2 - Software executing in Hyp mode + * Key: + * + * WR - Read/write addess allowed + * R - Read-only access allowed + * 0,1,2 - At PL0, PL1, and/or PL2 + * + * PL0 - User privilege level + * PL1 - Privilieged mode + * PL2 - Software executing in Hyp mode */ -#define PMD_SECT_AP_NONE (0) -#define PMD_SECT_AP_RW12 (PMD_SECT_AP0) -#define PMD_SECT_AP_RW12_R0 (PMD_SECT_AP1) -#define PMD_SECT_AP_RW012 (PMD_SECT_AP0 | PMD_SECT_AP1) -#define PMD_SECT_AP_R12 (PMD_SECT_AP0 | PMD_SECT_AP2) -#define PMD_SECT_AP_R012 (PMD_SECT_AP0 | PMD_SECT_AP1 | PMD_SECT_AP2) +#ifdef CONFIG_AFE_ENABLE +/* AP[2:1] access permissions model. AP[0] is used as an access flag: */ + +# define PMD_SECT_AP_RW1 (0) +# define PMD_SECT_AP_RW01 (PMD_SECT_AP1) +# define PMD_SECT_AP_R1 (PMD_SECT_AP2) +# define PMD_SECT_AP_R01 (PMD_SECT_AP1 | PMD_SECT_AP2) + +#else +/* AP[2:0] access permissions control, Short-descriptor format only */ + +# define PMD_SECT_AP_NONE (0) +# define PMD_SECT_AP_RW12 (PMD_SECT_AP0) +# define PMD_SECT_AP_RW12_R0 (PMD_SECT_AP1) +# define PMD_SECT_AP_RW012 (PMD_SECT_AP0 | PMD_SECT_AP1) +# define PMD_SECT_AP_R12 (PMD_SECT_AP0 | PMD_SECT_AP2) +# define PMD_SECT_AP_R012 (PMD_SECT_AP0 | PMD_SECT_AP1 | PMD_SECT_AP2) + +/* Some mode-independent aliases */ + +# define PMD_SECT_AP_RW1 PMD_SECT_AP_RW12 +# define PMD_SECT_AP_RW01 PMD_SECT_AP_RW012 +# define PMD_SECT_AP_R1 PMD_SECT_AP_R12 +# define PMD_SECT_AP_R01 PMD_SECT_AP_R012 + +#endif /* Short-descriptor translation table second-level descriptor formats * - * A PMD_TYPE_PTE level-one table entry provides the base address of the beginning of a second - * -level page table. There are two types of page table entries: + * A PMD_TYPE_PTE level-one table entry provides the base address of the beginning + * of a second-level page table. There are two types of page table entries: * * - Large page table entries support mapping of 64KB memory regions. * - Small page table entries support mapping of 4KB memory regions. @@ -385,12 +414,32 @@ * PL2 - Software executing in Hyp mode */ -#define PTE_AP_NONE (0) -#define PTE_AP_RW12 (PTE_AP0) -#define PTE_AP_RW12_R0 (PTE_AP1) -#define PTE_AP_RW012 (PTE_AP0 | PTE_AP1) -#define PTE_AP_R12 (PTE_AP0 | PTE_AP2) -#define PTE_AP_R012 (PTE_AP0 | PTE_AP1 | PTE_AP2) +#ifdef CONFIG_AFE_ENABLE +/* AP[2:1] access permissions model. AP[0] is used as an access flag: */ + +# define PTE_AP_RW1 (0) +# define PTE_AP_RW01 (PTE_AP1) +# define PTE_AP_R1 (PTE_AP2) +# define PTE_AP_R01 (PTE_AP1 | PTE_AP2) + +#else +/* AP[2:0] access permissions control, Short-descriptor format only */ + +# define PTE_AP_NONE (0) +# define PTE_AP_RW12 (PTE_AP0) +# define PTE_AP_RW12_R0 (PTE_AP1) +# define PTE_AP_RW012 (PTE_AP0 | PTE_AP1) +# define PTE_AP_R12 (PTE_AP0 | PTE_AP2) +# define PTE_AP_R012 (PTE_AP0 | PTE_AP1 | PTE_AP2) + +/* Some mode-independent aliases */ + +# define PTE_AP_RW1 PTE_AP_RW12 +# define PTE_AP_RW01 PTE_AP_RW012 +# define PTE_AP_R1 PTE_AP_R12 +# define PTE_AP_R01 PTE_AP_R012 + +#endif /* Default MMU flags for RAM memory, IO, vector region * @@ -398,16 +447,16 @@ */ #define MMU_ROMFLAGS \ - (PMD_TYPE_SECT | PMD_SECT_AP_R12) + (PMD_TYPE_SECT | PMD_SECT_AP_RW1) #define MMU_MEMFLAGS \ - (PMD_TYPE_SECT | PMD_SECT_C | PMD_SECT_B | PMD_SECT_AP_RW12) + (PMD_TYPE_SECT | PMD_SECT_C | PMD_SECT_B | PMD_SECT_AP_RW1) #define MMU_IOFLAGS \ - (PMD_TYPE_SECT | PMD_SECT_AP_RW012) + (PMD_TYPE_SECT | PMD_SECT_AP_RW01) #define MMU_L1_VECTORFLAGS (PMD_TYPE_PTE) -#define MMU_L2_VECTORFLAGS (PTE_TYPE_SMALL | PTE_AP_RW12) +#define MMU_L2_VECTORFLAGS (PTE_TYPE_SMALL | PTE_AP_RW1) /* Mapped section size */ @@ -442,7 +491,7 @@ * using this new virtual base address of the L2 page table. */ -# undef PGTABLE_L2_VBASE +# undef PGTABLE_L2_VBASE # define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_OFFSET) #endif /* CONFIG_PAGING */ diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 1b2ff6365d..2d4f05c1c6 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -33,11 +33,11 @@ # ############################################################################ -HEAD_ASRC = arm_head.S +HEAD_ASRC = arm_vectortab.S -CMN_ASRCS = arm_vectors.S arm_vectortab.S arm_cache.S arm_fpuconfig.S -CMN_ASRCS += arm_fullcontextrestore.S arm_saveusercontext.S -CMN_ASRCS += arm_vectoraddrexcptn.S arm_vfork.S +CMN_ASRCS = arm_head.S +CMN_ASRCS += arm_vectors.S arm_cache.S arm_fpuconfig.S arm_fullcontextrestore.S +CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c diff --git a/arch/arm/src/sama5/chip/sama5d3x_memorymap.h b/arch/arm/src/sama5/chip/sama5d3x_memorymap.h index 285a76b747..f17df9b0a6 100644 --- a/arch/arm/src/sama5/chip/sama5d3x_memorymap.h +++ b/arch/arm/src/sama5/chip/sama5d3x_memorymap.h @@ -89,7 +89,7 @@ #define SAM_UHPEHCI_PSECTION 0x00700000 /* 0x00700000-0x007fffff: UHP EHCI */ #define SAM_AXIMX_PSECTION 0x00800000 /* 0x00800000-0x008fffff: AXI Matr */ #define SAM_DAP_PSECTION 0x00900000 /* 0x00900000-0x009fffff: DAP */ - /* 0x000a0000-0x0fffffff: Undefined */ + /* 0x00a00000-0x0fffffff: Undefined */ /* SAMA5 Internal Peripheral Offsets */ #define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */ @@ -129,39 +129,41 @@ # define SAM_TDES_OFFSET 0x0003c000 /* 0x0003c000-0x0003ffff: TDES */ # define SAM_TRNG_OFFSET 0x00040000 /* 0x00040000-0x00043fff: TRNG */ /* 0x00044000-0x00ffbfff: Reserved */ -#define SAM_SYSC_PSECTION 0xff000000 /* 0xff000000-0xffffffff: System Controller */ +#define SAM_SYSC_PSECTION 0xfff00000 /* 0xfff00000-0xffffffff: System Controller */ #define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */ # define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */ -/* System Controller Peripheral Offsets */ +/* System Controller Peripheral Offsets. All relative to the beginning of the + * 16KB virtual or physical SYSC region (SAM_SYSC_VADDR or SAM_SYSC_PADDR). + */ -#define SAM_HSMC_OFFSET 0x00ffc000 /* 0x0fffc000-0x0fffcfff: HSMC */ - /* 0x0fffd000-0x0fffe3ff: Reserved */ -#define SAM_FUSE_OFFSET 0x00ffe400 /* 0x0fffe400-0x0fffe5ff: FUSE */ -#define SAM_DMAC0_OFFSET 0x00ffe600 /* 0x0fffe600-0x0fffe7ff: DMAC0 */ -#define SAM_DMAC1_OFFSET 0x00ffe800 /* 0x0fffe800-0x0fffe9ff: DMAC1 */ -#define SAM_MPDDRC_OFFSET 0x00ffea00 /* 0x0fffea00-0x0fffebff: MPDDRC */ -#define SAM_MATRIX_OFFSET 0x00ffec00 /* 0x0fffec00-0x0fffedff: MATRIX */ -#define SAM_DBGU_OFFSET 0x00ffee00 /* 0x0fffee00-0x0fffefff: DBGU */ -#define SAM_AIC_OFFSET 0x00fff000 /* 0x0ffff000-0x0ffff1ff: AIC */ -#define SAM_PION_OFFSET(n) (0x00fff200+((n) << 9)) -#define SAM_PIOA_OFFSET 0x00fff200 /* 0x0ffff200-0x0ffff3ff: PIOA */ -#define SAM_PIOB_OFFSET 0x00fff400 /* 0x0ffff400-0x0ffff5ff: PIOB */ -#define SAM_PIOC_OFFSET 0x00fff600 /* 0x0ffff600-0x0ffff7ff: PIOC */ -#define SAM_PIOD_OFFSET 0x00fff800 /* 0x0ffff800-0x0ffff9ff: PIOD */ -#define SAM_PIOE_OFFSET 0x00fffa00 /* 0x0ffffa00-0x0ffffbff: PIOE */ -#define SAM_PMC_OFFSET 0x00fffc00 /* 0x0ffffc00-0x0ffffdff: PMC */ -#define SAM_RSTC_OFFSET 0x00fffe00 /* 0x0ffffe00-0x0ffffe0f: RSTC */ -#define SAM_SHDC_OFFSET 0x00fffe10 /* 0x0ffffe10-0x0ffffe1f: SHDC */ - /* 0x0ffffe20-0x0ffffe2f: Reserved */ -#define SAM_PITC_OFFSET 0x00fffe30 /* 0x0ffffe30-0x0ffffe3f: PITC */ -#define SAM_WDT_OFFSET 0x00fffe40 /* 0x0ffffe40-0x0ffffe4f: WDT */ -#define SAM_SCKCR_OFFSET 0x00fffe50 /* 0x0ffffe50-0x0ffffe53: SCKCR */ -#define SAM_BSC_OFFSET 0x00fffe54 /* 0x0ffffe54-0x0ffffe5f: BSC */ -#define SAM_GPBR_OFFSET 0x00fffe60 /* 0x0ffffe60-0x0ffffe6f: GPBR */ - /* 0x0ffffe70-0x0ffffeaf: Reserved */ -#define SAM_RTCC_OFFSET 0x00fffeb0 /* 0x0ffffeb0-0x0ffffedf: RTCC */ - /* 0x0ffffee0-0x0fffffff: Reserved */ +#define SAM_HSMC_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMC */ + /* 0x00001000-0x000023ff: Reserved */ +#define SAM_FUSE_OFFSET 0x00002400 /* 0x00002400-0x000025ff: FUSE */ +#define SAM_DMAC0_OFFSET 0x00002600 /* 0x00002600-0x000027ff: DMAC0 */ +#define SAM_DMAC1_OFFSET 0x00002800 /* 0x00002800-0x000029ff: DMAC1 */ +#define SAM_MPDDRC_OFFSET 0x00002a00 /* 0x00002a00-0x00002bff: MPDDRC */ +#define SAM_MATRIX_OFFSET 0x00002c00 /* 0x00002c00-0x00002dff: MATRIX */ +#define SAM_DBGU_OFFSET 0x00002e00 /* 0x00002e00-0x00002fff: DBGU */ +#define SAM_AIC_OFFSET 0x00003000 /* 0x00003000-0x000031ff: AIC */ +#define SAM_PION_OFFSET(n) (0x00003200+((n) << 9)) +#define SAM_PIOA_OFFSET 0x00003200 /* 0x00003200-0x000033ff: PIOA */ +#define SAM_PIOB_OFFSET 0x00003400 /* 0x00003400-0x000035ff: PIOB */ +#define SAM_PIOC_OFFSET 0x00003600 /* 0x00003600-0x000037ff: PIOC */ +#define SAM_PIOD_OFFSET 0x00003800 /* 0x00003800-0x000039ff: PIOD */ +#define SAM_PIOE_OFFSET 0x00003a00 /* 0x00003a00-0x00003bff: PIOE */ +#define SAM_PMC_OFFSET 0x00003c00 /* 0x00003c00-0x00003dff: PMC */ +#define SAM_RSTC_OFFSET 0x00003e00 /* 0x00003e00-0x00003e0f: RSTC */ +#define SAM_SHDC_OFFSET 0x00003e10 /* 0x00003e10-0x00003e1f: SHDC */ + /* 0x00003e20-0x00003e2f: Reserved */ +#define SAM_PITC_OFFSET 0x00003e30 /* 0x00003e30-0x00003e3f: PITC */ +#define SAM_WDT_OFFSET 0x00003e40 /* 0x00003e40-0x00003e4f: WDT */ +#define SAM_SCKCR_OFFSET 0x00003e50 /* 0x00003e50-0x00003e53: SCKCR */ +#define SAM_BSC_OFFSET 0x00003e54 /* 0x00003e54-0x00003e5f: BSC */ +#define SAM_GPBR_OFFSET 0x00003e60 /* 0x00003e60-0x00003e6f: GPBR */ + /* 0x00003e70-0x00003eaf: Reserved */ +#define SAM_RTCC_OFFSET 0x00003eb0 /* 0x00003eb0-0x00003edf: RTCC */ + /* 0x00003ee0-0x00003fff: Reserved */ /* Sizes of memory regions in bytes. * @@ -185,7 +187,7 @@ /* 0xf0000000-0xffffffff: Internal Peripherals */ #define SAM_PERIPHA_SIZE (15*1024) /* 0xf0000000-0xf003bfff: Internal Peripherals */ #define SAM_PERIPHB_SIZE (272*1024) /* 0xf8000000-0xf8043fff: Internal Peripherals */ -#define SAM_SYSC_SIZE (1*1024*1024) /* 0xff000000-0x0ffffedf: Internal Peripherals */ +#define SAM_SYSC_SIZE (1*1024*1024) /* 0xfff00000-0x0ffffedf: Internal Peripherals */ /* Convert size in bytes to number of sections (in Mb). */ @@ -285,7 +287,7 @@ #define SAM_PERIPH_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */ # define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */ # define SAM_PERIPHB_VSECTION 0xf8000000 /* 0xf8000000-0xffffbfff: Internal Peripherals B */ -# define SAM_SYSC_VSECTION 0xff000000 /* 0xff000000-0xffffffff: System Controller */ +# define SAM_SYSC_VSECTION 0xfff00000 /* 0xfff00000-0xffffffff: System Controller */ # define SAM_SYSC_VADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */ #endif @@ -326,29 +328,29 @@ #define SAM_TDES_VBASE (SAM_PERIPHB_VSECTION+SAM_TDES_OFFSET) #define SAM_TRNG_VBASE (SAM_PERIPHB_VSECTION+SAM_TRNG_OFFSET) -#define SAM_HSMC_VBASE (SAM_SYSC_VSECTION+SAM_HSMC_OFFSET) -#define SAM_FUSE_VBASE (SAM_SYSC_VSECTION+SAM_FUSE_OFFSET) -#define SAM_DMAC0_VBASE (SAM_SYSC_VSECTION+SAM_DMAC0_OFFSET) -#define SAM_DMAC1_VBASE (SAM_SYSC_VSECTION+SAM_DMAC1_OFFSET) -#define SAM_MPDDRC_VBASE (SAM_SYSC_VSECTION+SAM_MPDDRC_OFFSET) -#define SAM_MATRIX_VBASE (SAM_SYSC_VSECTION+SAM_MATRIX_OFFSET) -#define SAM_DBGU_VBASE (SAM_SYSC_VSECTION+SAM_DBGU_OFFSET) -#define SAM_AIC_VBASE (SAM_SYSC_VSECTION+SAM_AIC_OFFSET) -#define SAM_PION_VBASE(n) (SAM_SYSC_VSECTION+SAM_PION_OFFSET(n)) -#define SAM_PIOA_VBASE (SAM_SYSC_VSECTION+SAM_PIOA_OFFSET) -#define SAM_PIOB_VBASE (SAM_SYSC_VSECTION+SAM_PIOB_OFFSET) -#define SAM_PIOC_VBASE (SAM_SYSC_VSECTION+SAM_PIOC_OFFSET) -#define SAM_PIOD_VBASE (SAM_SYSC_VSECTION+SAM_PIOD_OFFSET) -#define SAM_PIOE_VBASE (SAM_SYSC_VSECTION+SAM_PIOE_OFFSET) -#define SAM_PMC_VBASE (SAM_SYSC_VSECTION+SAM_PMC_OFFSET) -#define SAM_RSTC_VBASE (SAM_SYSC_VSECTION+SAM_RSTC_OFFSET) -#define SAM_SHDC_VBASE (SAM_SYSC_VSECTION+SAM_SHDC_OFFSET) -#define SAM_PITC_VBASE (SAM_SYSC_VSECTION+SAM_PITC_OFFSET) -#define SAM_WDT_VBASE (SAM_SYSC_VSECTION+SAM_WDT_OFFSET) -#define SAM_SCKCR_VBASE (SAM_SYSC_VSECTION+SAM_SCKCR_OFFSET) -#define SAM_BSC_VBASE (SAM_SYSC_VSECTION+SAM_BSC_OFFSET) -#define SAM_GPBR_VBASE (SAM_SYSC_VSECTION+SAM_GPBR_OFFSET) -#define SAM_RTCC_VBASE (SAM_SYSC_VSECTION+SAM_RTCC_OFFSET) +#define SAM_HSMC_VBASE (SAM_SYSC_VADDR+SAM_HSMC_OFFSET) +#define SAM_FUSE_VBASE (SAM_SYSC_VADDR+SAM_FUSE_OFFSET) +#define SAM_DMAC0_VBASE (SAM_SYSC_VADDR+SAM_DMAC0_OFFSET) +#define SAM_DMAC1_VBASE (SAM_SYSC_VADDR+SAM_DMAC1_OFFSET) +#define SAM_MPDDRC_VBASE (SAM_SYSC_VADDR+SAM_MPDDRC_OFFSET) +#define SAM_MATRIX_VBASE (SAM_SYSC_VADDR+SAM_MATRIX_OFFSET) +#define SAM_DBGU_VBASE (SAM_SYSC_VADDR+SAM_DBGU_OFFSET) +#define SAM_AIC_VBASE (SAM_SYSC_VADDR+SAM_AIC_OFFSET) +#define SAM_PION_VBASE(n) (SAM_SYSC_VADDR+SAM_PION_OFFSET(n)) +#define SAM_PIOA_VBASE (SAM_SYSC_VADDR+SAM_PIOA_OFFSET) +#define SAM_PIOB_VBASE (SAM_SYSC_VADDR+SAM_PIOB_OFFSET) +#define SAM_PIOC_VBASE (SAM_SYSC_VADDR+SAM_PIOC_OFFSET) +#define SAM_PIOD_VBASE (SAM_SYSC_VADDR+SAM_PIOD_OFFSET) +#define SAM_PIOE_VBASE (SAM_SYSC_VADDR+SAM_PIOE_OFFSET) +#define SAM_PMC_VBASE (SAM_SYSC_VADDR+SAM_PMC_OFFSET) +#define SAM_RSTC_VBASE (SAM_SYSC_VADDR+SAM_RSTC_OFFSET) +#define SAM_SHDC_VBASE (SAM_SYSC_VADDR+SAM_SHDC_OFFSET) +#define SAM_PITC_VBASE (SAM_SYSC_VADDR+SAM_PITC_OFFSET) +#define SAM_WDT_VBASE (SAM_SYSC_VADDR+SAM_WDT_OFFSET) +#define SAM_SCKCR_VBASE (SAM_SYSC_VADDR+SAM_SCKCR_OFFSET) +#define SAM_BSC_VBASE (SAM_SYSC_VADDR+SAM_BSC_OFFSET) +#define SAM_GPBR_VBASE (SAM_SYSC_VADDR+SAM_GPBR_OFFSET) +#define SAM_RTCC_VBASE (SAM_SYSC_VADDR+SAM_RTCC_OFFSET) /* NuttX vitual base address * @@ -446,30 +448,6 @@ # endif #endif -/* Page table start addresses. - * - * 16Kb of memory is reserved hold the page table for the virtual mappings. A - * portion of this table is not accessible in the virtual address space (for - * normal operation). We will reuse this memory for coarse page tables as follows: - * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual address - * of the page table. - */ - -#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+0x00000800) -#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+0x00000800) - -/* Page table end addresses: */ - -#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE) -#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE) - -/* Page table sizes */ - -#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_VBASE) -#define PGTABLE_L2_SIZE (4*256) -#define PGTABLE_L2_NENTRIES (PGTABLE_L2_ALLOC / PGTABLE_L2_SIZE) - /* Base address of the interrupt vector table. * * SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM @@ -482,9 +460,8 @@ # define SAM_VECTOR_PADDR SAM_ISRAM0_PADDR # define SAM_VECTOR_VSRAM SAM_ISRAM0_VADDR # define SAM_VECTOR_VADDR 0x00000000 -# define SAM_VECTOR_VCOARSE 0x00000000 #else /* Vectors located at 0xffff:0000 -- this probably does not work */ -# ifdef HAVE_ISRAM1 +# ifdef SAM_ISRAM1_SIZE >= VECTOR_TABLE_SIZE # define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE) # define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE) # else @@ -492,9 +469,62 @@ # define SAM_VECTOR_VSRAM (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE) # endif # define SAM_VECTOR_VADDR 0xffff0000 -# define SAM_VECTOR_VCOARSE 0xfff00000 #endif +/* Level 2 Page table start addresses. + * + * 16Kb of memory is reserved hold the page table for the virtual mappings. A + * portion of this table is not accessible in the virtual address space (for + * normal operation). There is this large whole in the physcal address space + * for which there will never be level 1 mappings: + * + * 0x80000000-0xefffffff: Undefined (1.75 GB) + * + * That is the offset where the main L2 page table will be positioned. This + * corresponds to page table offsets 0x000002000 through 0x000003c00. That + * is 1792 entries mapping 1MB of address each for a total of 1.75 GB of virtual + * address space) + */ + +#define PGTABLE_L2_OFFSET 0x000002000 +#define PGTABLE_L2_SIZE 0x000001c00 + +/* This other small region is reserved for the vector table L2 page table + * + * 0x00a00000-0x0fffffff: Undefined (246 MB) + * + * This corresponds to page table offsets 0x000000028 through 0x00000400. That + * is 246 entries mapping 1MB of address each for a total of 246 MB of virtual + * address space) + */ + +#define VECTOR_L2_OFFSET 0x000000028 +#define VECTOR_L2_SIZE 0x000000400 + +/* If we need more L2 page tables, there additional entries can be obtained + * from other unused areas in the physical memory map: + * + * 0x0003c000-0x07ffffff: Reserved (127.8 MB) + * 0x00044000-0x00ffbfff: Reserved ( 15.7 MB) + * + * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual address + * of the page table. + */ + +#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_OFFSET) +#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_OFFSET) + +#define VECTOR_L2_PBASE (SAM_VECTOR_PADDR+VECTOR_L2_OFFSET) +#define VECTOR_L2_VBASE (SAM_VECTOR_VADDR+VECTOR_L2_OFFSET) + +/* Page table end addresses: */ + +#define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE+PGTABLE_L2_SIZE) +#define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE+PGTABLE_L2_SIZE) + +#define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE+VECTOR_L2_SIZE) +#define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE+VECTOR_L2_SIZE) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index 79c75dae4d..40f66b6ddc 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -58,8 +58,29 @@ #include "sam_lowputc.h" /**************************************************************************** - * Private Types + * Pre-processor Definitions ****************************************************************************/ +/* The vectors are, by default, positioned at the beginning of the text + * section. Under what conditions do we have to remap the these vectors? + * + * 1) If we are using high vectors. In this case, the vectors will lie at + * virtual address 0xfffc0000 and we will need to a) copy the vectors to + * another location, and 2) map the vectors to that address. + * 2) If we are using low vectors but the .text region is not already mapped + * to address 0x0000:0000 + * 3) We are not using a ROM page table. We cannot set any custom mappings in + * the case and the build must conform to the ROM page table properties + */ + +#undef NEED_VECTORMAP +#if !defined(CONFIG_ARCH_LOWVECTORS) || (NUTTX_START_VADDR & 0xfff00000) != 0 + +# if defined(CONFIG_ARCH_ROMPGTABLE) +# error Vector remap cannot be performed if we are using a ROM page table +# endif + +# define NEED_VECTORMAP +#endif /**************************************************************************** * Private Types @@ -94,64 +115,64 @@ static const struct section_mapping_s section_mapping[] = /* SAMA5 Internal Memories */ #ifndef CONFIG_ARCH_LOWVECTORS - { SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION, + { SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION, SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS}, #endif - { SAM_ROM_PSECTION, SAM_ROM_VSECTION, + { SAM_ROM_PSECTION, SAM_ROM_VSECTION, SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS}, - { SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION, + { SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION, SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS}, #ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ - { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, + { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS}, #endif - { SAM_SMD_PSECTION, SAM_SMD_VSECTION, + { SAM_SMD_PSECTION, SAM_SMD_VSECTION, SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS}, - { SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION, + { SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION, SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS}, - { SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION, + { SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION, SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS}, - { SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION, + { SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION, SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS}, - { SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION, + { SAM_AXIMX_PSECTION, SAM_AXIMX_VSECTION, SAM_AXIMX_MMUFLAGS, SAM_AXIMX_NSECTIONS}, - { SAM_DAP_PSECTION, SAM_DAP_VSECTION, + { SAM_DAP_PSECTION, SAM_DAP_VSECTION, SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS}, /* SAMA5 External Memories */ #ifdef CONFIG_SAMA5_EBICS0 - { SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION, + { SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION, SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS}, #endif #ifdef CONFIG_SAMA5_DDRCS - { SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION, + { SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION, SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS}, #endif #ifdef CONFIG_SAMA5_EBICS1 - { SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION, + { SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION, SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS}, #endif #ifdef CONFIG_SAMA5_EBICS2 - { SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION, + { SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION, SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS}, #endif #ifdef CONFIG_SAMA5_EBICS3 - { SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION, + { SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION, SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS}, #endif #ifdef CONFIG_SAMA5_NFCCR - { SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION, + { SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION, SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS}, #endif /* SAMA5 Internal Peripherals */ - { SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION, + { SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION, SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS}, - { SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION, + { SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION, SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS}, - { SAM_SYSC_PSECTION, SAM_SYSC_VSECTION, + { SAM_SYSC_PSECTION, SAM_SYSC_VSECTION, SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS}, }; #define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s)) @@ -162,12 +183,16 @@ static const struct section_mapping_s section_mapping[] = ****************************************************************************/ /**************************************************************************** - * Name: sam_setlevel1entry + * Name: sam_setl1entry + * + * Description: + * Set a level 1 translation table entry. + * ****************************************************************************/ #ifndef CONFIG_ARCH_ROMPGTABLE -static inline void sam_setlevel1entry(uint32_t paddr, uint32_t vaddr, - uint32_t mmuflags) +static inline void sam_setl1entry(uint32_t paddr, uint32_t vaddr, + uint32_t mmuflags) { uint32_t *pgtable = (uint32_t*)PGTABLE_BASE_VADDR; uint32_t index = vaddr >> 20; @@ -179,12 +204,11 @@ static inline void sam_setlevel1entry(uint32_t paddr, uint32_t vaddr, #endif /**************************************************************************** - * Name: sam_setlevel2coarseentry + * Name: sam_setl2smallentry ****************************************************************************/ -static inline void -sam_setlevel2coarseentry(uint32_t ctabvaddr, uint32_t paddr, uint32_t vaddr, - uint32_t mmuflags) +static inline void sam_setl2smallentry(uint32_t ctabvaddr, uint32_t paddr, + uint32_t vaddr, uint32_t mmuflags) { uint32_t *ctable = (uint32_t*)ctabvaddr; uint32_t index; @@ -218,7 +242,7 @@ static void sam_setupmappings(void) for (j = 0; j < section_mapping[i].nsections; j++) { - sam_setlevel1entry(sect_paddr, sect_vaddr, mmuflags); + sam_setl1entry(sect_paddr, sect_vaddr, mmuflags); sect_paddr += SECTION_SIZE; sect_vaddr += SECTION_SIZE; } @@ -234,8 +258,7 @@ static void sam_setupmappings(void) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) +#if defined(NEED_VECTORMAP) && defined(CONFIG_PAGING) static void sam_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -248,7 +271,7 @@ static void sam_vectorpermissions(uint32_t mmuflags) pte = *ptr; if (pte == 0) { - pte = PG_VECT_PBASE; + pte = PG_VECT_PBASE; } else { @@ -278,7 +301,7 @@ static void sam_vectorpermissions(uint32_t mmuflags) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS) +#ifdef NEED_VECTORMAP static void sam_vectormapping(void) { uint32_t vector_paddr = SAM_VECTOR_PADDR; @@ -293,39 +316,44 @@ static void sam_vectormapping(void) while (vector_paddr < end_paddr) { - sam_setlevel2coarseentry(PGTABLE_L2_VBASE, vector_paddr, - vector_vaddr, MMU_L2_VECTORFLAGS); + sam_setl2smallentry(VECTOR_L2_VBASE, vector_paddr, vector_vaddr, + MMU_L2_VECTORFLAGS); vector_paddr += 4096; vector_vaddr += 4096; } /* Now set the level 1 descriptor to refer to the level 2 page table. */ - sam_setlevel1entry(PGTABLE_L2_PBASE, SAM_VECTOR_VCOARSE, - MMU_L1_VECTORFLAGS); + sam_setl1entry(VECTOR_L2_PBASE, SAM_VECTOR_VADDR, MMU_L1_VECTORFLAGS); } +#else + /* No vector remap */ + +# define sam_vectormapping() #endif /**************************************************************************** * Name: sam_copyvectorblock * * Description: - * Copy the interrupt block to its final destination. + * Copy the interrupt block to its final destination. Vectors are already + * positioned at the beginning of the text region and only need to be + * copied in the case where we are using high vectors. * ****************************************************************************/ +#ifndef CONFIG_ARCH_LOWVECTORS static void sam_copyvectorblock(void) { uint32_t *src; uint32_t *end; uint32_t *dest; - /* If we are using vectors in low memory but RAM in that area has been marked + /* If we are using re-mapped vectors in an area that has been marked * read only, then temparily mark the mapping write-able (non-buffered). */ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) +#if defined(NEED_VECTORMAP) && defined(CONFIG_PAGING) sam_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif @@ -349,11 +377,15 @@ static void sam_copyvectorblock(void) /* Make the vectors read-only, cacheable again */ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) - sam_vectorpermissions(MMU_L2_VECTROFLAGS); +#if defined(NEED_VECTORMAP) && defined(CONFIG_PAGING) + sam_vectorpermissions(MMU_L2_VECTORFLAGS); #endif } +#else +/* Don't copy the vectors */ + +# define sam_copyvectorblock() +#endif /**************************************************************************** * Name: sam_wdtdisable @@ -365,7 +397,9 @@ static void sam_copyvectorblock(void) static inline void sam_wdtdisable(void) { +#if 0 // REVISIT putreg32(WDT_MR_WDDIS, SAM_WDT_MR); +#endif } /**************************************************************************** @@ -444,20 +478,19 @@ static inline void sam_wdtdisable(void) void up_boot(void) { +#ifndef CONFIG_ARCH_ROMPGTABLE /* __start provided the basic MMU mappings for SRAM. Now provide mappings * for all IO regions (Including the vector region). */ -#ifndef CONFIG_ARCH_ROMPGTABLE sam_setupmappings(); /* Provide a special mapping for the IRAM interrupt vector positioned in * high memory. */ -#ifndef CONFIG_ARCH_LOWVECTORS sam_vectormapping(); -#endif + #endif /* CONFIG_ARCH_ROMPGTABLE */ /* Setup up vector block. _vector_start and _vector_end are exported from @@ -472,7 +505,7 @@ void up_boot(void) /* Initialize clocking to settings provided by board-specific logic */ - sam_clockconfig(); + sam_clockconfig(); /* Initialize the FPU */ diff --git a/arch/arm/src/sama5/sam_clockconfig.c b/arch/arm/src/sama5/sam_clockconfig.c index b3de93fdc3..c26b64f493 100644 --- a/arch/arm/src/sama5/sam_clockconfig.c +++ b/arch/arm/src/sama5/sam_clockconfig.c @@ -464,7 +464,8 @@ void sam_clockconfig(void) #ifdef CONFIG_SAMA5_BOOT_CS0FLASH if (config) -#if define(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH) +#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */ +#if defined(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH) { /* Enable main oscillator (if it has not already been selected) */ @@ -502,5 +503,4 @@ void sam_clockconfig(void) sam_upllsetup(); } #endif /* CONFIG_SAMA5_BOOT_ISRAM || CONFIG_SAMA5_BOOT_CS0FLASH */ -#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */ } diff --git a/configs/sama5d3x-ek/scripts/ddram.ld b/configs/sama5d3x-ek/scripts/ddram.ld index 5aa3bda060..fcc213f618 100644 --- a/configs/sama5d3x-ek/scripts/ddram.ld +++ b/configs/sama5d3x-ek/scripts/ddram.ld @@ -56,7 +56,7 @@ SECTIONS { .text : { _stext = ABSOLUTE(.); - KEEP (*(.vectors)) + *(.vectors) *(.text .text.*) *(.fixup) *(.gnu.warning) diff --git a/configs/sama5d3x-ek/scripts/isram.ld b/configs/sama5d3x-ek/scripts/isram.ld index aeb1668b74..035fd57470 100644 --- a/configs/sama5d3x-ek/scripts/isram.ld +++ b/configs/sama5d3x-ek/scripts/isram.ld @@ -53,7 +53,7 @@ SECTIONS { .text : { _stext = ABSOLUTE(.); - KEEP (*(.vectors)) + *(.vectors) *(.text .text.*) *(.fixup) *(.gnu.warning) diff --git a/configs/sama5d3x-ek/scripts/pg-sram.ld b/configs/sama5d3x-ek/scripts/pg-sram.ld index ea2eb026ec..6cf0591a2c 100644 --- a/configs/sama5d3x-ek/scripts/pg-sram.ld +++ b/configs/sama5d3x-ek/scripts/pg-sram.ld @@ -81,7 +81,7 @@ SECTIONS { .locked : { _slocked = ABSOLUTE(.); - KEEP (*(.vectors)) + *(.vectors) up_head.o locked.r (.text .text.*) up_head.o locked.r (.fixup) up_head.o locked.r (.gnu.warning)