arch/xmc4: Fix CCU registers

2024-02-09 17:45:16 +01:00 · 2024-02-09 17:45:16 +01:00 · 4a85fbfd09
commit 4a85fbfd09
parent de948babbf
1 changed files with 500 additions and 120 deletions
--- a/arch/arm/src/xmc4/hardware/xmc4_ccu4.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_ccu4.h
@ -76,7 +76,7 @@
 #define XMC4_CCU4_GCST_OFFSET              0x0018   /* General Channel Status Register */
 #define XMC4_CCU4_MIDR_OFFSET              0x0080   /* Module Identification Register */

-/* CCU40 Registers */
+/* CC40 Registers */

 #define XMC4_CCU4_CC40INS_OFFSET           0x0100   /* Input Selector Unit Configuration */
 #define XMC4_CCU4_CC40CMC_OFFSET           0x0104   /* Connection Matrix Configuration */
@ -107,7 +107,7 @@
 #define XMC4_CCU4_CC40ECRD0_OFFSET         0x01B8   /* Extended Read Back 0 */
 #define XMC4_CCU4_CC40ECRD1_OFFSET         0x01BC   /* Extended Read Back 1 */

-/* CCU41 Registers */
+/* CC41 Registers */

 #define XMC4_CCU4_CC41INS_OFFSET           0x0200   /* Input Selector Unit Configuration */
 #define XMC4_CCU4_CC41CMC_OFFSET           0x0204   /* Connection Matrix Configuration */
@ -138,7 +138,7 @@
 #define XMC4_CCU4_CC41ECRD0_OFFSET         0x02B8   /* Extended Read Back 0 */
 #define XMC4_CCU4_CC41ECRD1_OFFSET         0x02BC   /* Extended Read Back 1 */

-/* CCU42 Registers */
+/* CC42 Registers */

 #define XMC4_CCU4_CC42INS_OFFSET           0x0300   /* Input Selector Unit Configuration */
 #define XMC4_CCU4_CC42CMC_OFFSET           0x0304   /* Connection Matrix Configuration */
@ -169,7 +169,7 @@
 #define XMC4_CCU4_CC42ECRD0_OFFSET         0x03B8   /* Extended Read Back 0 */
 #define XMC4_CCU4_CC42ECRD1_OFFSET         0x03BC   /* Extended Read Back 1 */

-/* CCU43 Registers */
+/* CC43 Registers */

 #define XMC4_CCU4_CC43INS_OFFSET           0x0400   /* Input Selector Unit Configuration */
 #define XMC4_CCU4_CC43CMC_OFFSET           0x0404   /* Connection Matrix Configuration */
@ -202,7 +202,7 @@

 /* Register Addresses *******************************************************/

-/* CCU40 Registers */
+/* CCU40 Global Registers */

 #define XMC4_CCU40_GCTRL             (XMC4_CCU40_BASE+XMC4_CCU4_GCTRL_OFFSET)
 #define XMC4_CCU40_GSTAT             (XMC4_CCU40_BASE+XMC4_CCU4_GSTAT_OFFSET)
@ -213,36 +213,131 @@
 #define XMC4_CCU40_GCST              (XMC4_CCU40_BASE+XMC4_CCU4_GCST_OFFSET)
 #define XMC4_CCU40_MIDR              (XMC4_CCU40_BASE+XMC4_CCU4_MIDR_OFFSET)

-#define XMC4_CCU4_CC40INS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40INS_OFFSET)
-#define XMC4_CCU4_CC40CMC            (XMC4_CCU40_BASE+XMC4_CCU4_CC40CMC_OFFSET)
-#define XMC4_CCU4_CC40TST            (XMC4_CCU40_BASE+XMC4_CCU4_CC40TST_OFFSET)
-#define XMC4_CCU4_CC40TCSET          (XMC4_CCU40_BASE+XMC4_CCU4_CC40TCSET_OFFSET)
-#define XMC4_CCU4_CC40TCCLR          (XMC4_CCU40_BASE+XMC4_CCU4_CC40TCCLR_OFFSET)
-#define XMC4_CCU4_CC40TC             (XMC4_CCU40_BASE+XMC4_CCU4_CC40TC_OFFSET)
-#define XMC4_CCU4_CC40PSL            (XMC4_CCU40_BASE+XMC4_CCU4_CC40PSL_OFFSET)
-#define XMC4_CCU4_CC40DIT            (XMC4_CCU40_BASE+XMC4_CCU4_CC40DIT_OFFSET)
-#define XMC4_CCU4_CC40DITS           (XMC4_CCU40_BASE+XMC4_CCU4_CC40DITS_OFFSET)
-#define XMC4_CCU4_CC40PSC            (XMC4_CCU40_BASE+XMC4_CCU4_CC40PSC_OFFSET)
-#define XMC4_CCU4_CC40FPC            (XMC4_CCU40_BASE+XMC4_CCU4_CC40FPC_OFFSET)
-#define XMC4_CCU4_CC40FPCS           (XMC4_CCU40_BASE+XMC4_CCU4_CC40FPCS_OFFSET)
-#define XMC4_CCU4_CC40PR             (XMC4_CCU40_BASE+XMC4_CCU4_CC40PR_OFFSET)
-#define XMC4_CCU4_CC40PRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40PRS_OFFSET)
-#define XMC4_CCU4_CC40CR             (XMC4_CCU40_BASE+XMC4_CCU4_CC40CR_OFFSET)
-#define XMC4_CCU4_CC40CRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40CRS_OFFSET)
-#define XMC4_CCU4_CC40TIMER          (XMC4_CCU40_BASE+XMC4_CCU4_CC40TIMER_OFFSET)
-#define XMC4_CCU4_CC40C0V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C0V_OFFSET)
-#define XMC4_CCU4_CC40C1V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C1V_OFFSET)
-#define XMC4_CCU4_CC40C2V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C2V_OFFSET)
-#define XMC4_CCU4_CC40C3V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C3V_OFFSET)
-#define XMC4_CCU4_CC40INTS           (XMC4_CCU40_BASE+XMC4_CCU4_CC40INTS_OFFSET)
-#define XMC4_CCU4_CC40INTE           (XMC4_CCU40_BASE+XMC4_CCU4_CC40INTE_OFFSET)
-#define XMC4_CCU4_CC40SRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40SRS_OFFSET)
-#define XMC4_CCU4_CC40SWS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40SWS_OFFSET)
-#define XMC4_CCU4_CC40SWR            (XMC4_CCU40_BASE+XMC4_CCU4_CC40SWR_OFFSET)
-#define XMC4_CCU4_CC40ECRD0          (XMC4_CCU40_BASE+XMC4_CCU4_CC40ECRD0_OFFSET)
-#define XMC4_CCU4_CC40ECRD1          (XMC4_CCU40_BASE+XMC4_CCU4_CC40ECRD1_OFFSET)
+/* CCU40 CC40 Slice Registers */

-/* CCU41 Registers */
+#define XMC4_CCU40_CC40INS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40INS_OFFSET)
+#define XMC4_CCU40_CC40CMC            (XMC4_CCU40_BASE+XMC4_CCU4_CC40CMC_OFFSET)
+#define XMC4_CCU40_CC40TST            (XMC4_CCU40_BASE+XMC4_CCU4_CC40TST_OFFSET)
+#define XMC4_CCU40_CC40TCSET          (XMC4_CCU40_BASE+XMC4_CCU4_CC40TCSET_OFFSET)
+#define XMC4_CCU40_CC40TCCLR          (XMC4_CCU40_BASE+XMC4_CCU4_CC40TCCLR_OFFSET)
+#define XMC4_CCU40_CC40TC             (XMC4_CCU40_BASE+XMC4_CCU4_CC40TC_OFFSET)
+#define XMC4_CCU40_CC40PSL            (XMC4_CCU40_BASE+XMC4_CCU4_CC40PSL_OFFSET)
+#define XMC4_CCU40_CC40DIT            (XMC4_CCU40_BASE+XMC4_CCU4_CC40DIT_OFFSET)
+#define XMC4_CCU40_CC40DITS           (XMC4_CCU40_BASE+XMC4_CCU4_CC40DITS_OFFSET)
+#define XMC4_CCU40_CC40PSC            (XMC4_CCU40_BASE+XMC4_CCU4_CC40PSC_OFFSET)
+#define XMC4_CCU40_CC40FPC            (XMC4_CCU40_BASE+XMC4_CCU4_CC40FPC_OFFSET)
+#define XMC4_CCU40_CC40FPCS           (XMC4_CCU40_BASE+XMC4_CCU4_CC40FPCS_OFFSET)
+#define XMC4_CCU40_CC40PR             (XMC4_CCU40_BASE+XMC4_CCU4_CC40PR_OFFSET)
+#define XMC4_CCU40_CC40PRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40PRS_OFFSET)
+#define XMC4_CCU40_CC40CR             (XMC4_CCU40_BASE+XMC4_CCU4_CC40CR_OFFSET)
+#define XMC4_CCU40_CC40CRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40CRS_OFFSET)
+#define XMC4_CCU40_CC40TIMER          (XMC4_CCU40_BASE+XMC4_CCU4_CC40TIMER_OFFSET)
+#define XMC4_CCU40_CC40C0V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C0V_OFFSET)
+#define XMC4_CCU40_CC40C1V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C1V_OFFSET)
+#define XMC4_CCU40_CC40C2V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C2V_OFFSET)
+#define XMC4_CCU40_CC40C3V            (XMC4_CCU40_BASE+XMC4_CCU4_CC40C3V_OFFSET)
+#define XMC4_CCU40_CC40INTS           (XMC4_CCU40_BASE+XMC4_CCU4_CC40INTS_OFFSET)
+#define XMC4_CCU40_CC40INTE           (XMC4_CCU40_BASE+XMC4_CCU4_CC40INTE_OFFSET)
+#define XMC4_CCU40_CC40SRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40SRS_OFFSET)
+#define XMC4_CCU40_CC40SWS            (XMC4_CCU40_BASE+XMC4_CCU4_CC40SWS_OFFSET)
+#define XMC4_CCU40_CC40SWR            (XMC4_CCU40_BASE+XMC4_CCU4_CC40SWR_OFFSET)
+#define XMC4_CCU40_CC40ECRD0          (XMC4_CCU40_BASE+XMC4_CCU4_CC40ECRD0_OFFSET)
+#define XMC4_CCU40_CC40ECRD1          (XMC4_CCU40_BASE+XMC4_CCU4_CC40ECRD1_OFFSET)
+
+/* CCU40 CC41 Slice Registers */
+
+#define XMC4_CCU40_CC41INS            (XMC4_CCU40_BASE+XMC4_CCU4_CC41INS_OFFSET)
+#define XMC4_CCU40_CC41CMC            (XMC4_CCU40_BASE+XMC4_CCU4_CC41CMC_OFFSET)
+#define XMC4_CCU40_CC41TST            (XMC4_CCU40_BASE+XMC4_CCU4_CC41TST_OFFSET)
+#define XMC4_CCU40_CC41TCSET          (XMC4_CCU40_BASE+XMC4_CCU4_CC41TCSET_OFFSET)
+#define XMC4_CCU40_CC41TCCLR          (XMC4_CCU40_BASE+XMC4_CCU4_CC41TCCLR_OFFSET)
+#define XMC4_CCU40_CC41TC             (XMC4_CCU40_BASE+XMC4_CCU4_CC41TC_OFFSET)
+#define XMC4_CCU40_CC41PSL            (XMC4_CCU40_BASE+XMC4_CCU4_CC41PSL_OFFSET)
+#define XMC4_CCU40_CC41DIT            (XMC4_CCU40_BASE+XMC4_CCU4_CC41DIT_OFFSET)
+#define XMC4_CCU40_CC41DITS           (XMC4_CCU40_BASE+XMC4_CCU4_CC41DITS_OFFSET)
+#define XMC4_CCU40_CC41PSC            (XMC4_CCU40_BASE+XMC4_CCU4_CC41PSC_OFFSET)
+#define XMC4_CCU40_CC41FPC            (XMC4_CCU40_BASE+XMC4_CCU4_CC41FPC_OFFSET)
+#define XMC4_CCU40_CC41FPCS           (XMC4_CCU40_BASE+XMC4_CCU4_CC41FPCS_OFFSET)
+#define XMC4_CCU40_CC41PR             (XMC4_CCU40_BASE+XMC4_CCU4_CC41PR_OFFSET)
+#define XMC4_CCU40_CC41PRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC41PRS_OFFSET)
+#define XMC4_CCU40_CC41CR             (XMC4_CCU40_BASE+XMC4_CCU4_CC41CR_OFFSET)
+#define XMC4_CCU40_CC41CRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC41CRS_OFFSET)
+#define XMC4_CCU40_CC41TIMER          (XMC4_CCU40_BASE+XMC4_CCU4_CC41TIMER_OFFSET)
+#define XMC4_CCU40_CC41C0V            (XMC4_CCU40_BASE+XMC4_CCU4_CC41C0V_OFFSET)
+#define XMC4_CCU40_CC41C1V            (XMC4_CCU40_BASE+XMC4_CCU4_CC41C1V_OFFSET)
+#define XMC4_CCU40_CC41C2V            (XMC4_CCU40_BASE+XMC4_CCU4_CC41C2V_OFFSET)
+#define XMC4_CCU40_CC41C3V            (XMC4_CCU40_BASE+XMC4_CCU4_CC41C3V_OFFSET)
+#define XMC4_CCU40_CC41INTS           (XMC4_CCU40_BASE+XMC4_CCU4_CC41INTS_OFFSET)
+#define XMC4_CCU40_CC41INTE           (XMC4_CCU40_BASE+XMC4_CCU4_CC41INTE_OFFSET)
+#define XMC4_CCU40_CC41SRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC41SRS_OFFSET)
+#define XMC4_CCU40_CC41SWS            (XMC4_CCU40_BASE+XMC4_CCU4_CC41SWS_OFFSET)
+#define XMC4_CCU40_CC41SWR            (XMC4_CCU40_BASE+XMC4_CCU4_CC41SWR_OFFSET)
+#define XMC4_CCU40_CC41ECRD0          (XMC4_CCU40_BASE+XMC4_CCU4_CC41ECRD0_OFFSET)
+#define XMC4_CCU40_CC41ECRD1          (XMC4_CCU40_BASE+XMC4_CCU4_CC41ECRD1_OFFSET)
+
+/* CCU40 CC42 Slice Registers */
+
+#define XMC4_CCU40_CC42INS            (XMC4_CCU40_BASE+XMC4_CCU4_CC42INS_OFFSET)
+#define XMC4_CCU40_CC42CMC            (XMC4_CCU40_BASE+XMC4_CCU4_CC42CMC_OFFSET)
+#define XMC4_CCU40_CC42TST            (XMC4_CCU40_BASE+XMC4_CCU4_CC42TST_OFFSET)
+#define XMC4_CCU40_CC42TCSET          (XMC4_CCU40_BASE+XMC4_CCU4_CC42TCSET_OFFSET)
+#define XMC4_CCU40_CC42TCCLR          (XMC4_CCU40_BASE+XMC4_CCU4_CC42TCCLR_OFFSET)
+#define XMC4_CCU40_CC42TC             (XMC4_CCU40_BASE+XMC4_CCU4_CC42TC_OFFSET)
+#define XMC4_CCU40_CC42PSL            (XMC4_CCU40_BASE+XMC4_CCU4_CC42PSL_OFFSET)
+#define XMC4_CCU40_CC42DIT            (XMC4_CCU40_BASE+XMC4_CCU4_CC42DIT_OFFSET)
+#define XMC4_CCU40_CC42DITS           (XMC4_CCU40_BASE+XMC4_CCU4_CC42DITS_OFFSET)
+#define XMC4_CCU40_CC42PSC            (XMC4_CCU40_BASE+XMC4_CCU4_CC42PSC_OFFSET)
+#define XMC4_CCU40_CC42FPC            (XMC4_CCU40_BASE+XMC4_CCU4_CC42FPC_OFFSET)
+#define XMC4_CCU40_CC42FPCS           (XMC4_CCU40_BASE+XMC4_CCU4_CC42FPCS_OFFSET)
+#define XMC4_CCU40_CC42PR             (XMC4_CCU40_BASE+XMC4_CCU4_CC42PR_OFFSET)
+#define XMC4_CCU40_CC42PRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC42PRS_OFFSET)
+#define XMC4_CCU40_CC42CR             (XMC4_CCU40_BASE+XMC4_CCU4_CC42CR_OFFSET)
+#define XMC4_CCU40_CC42CRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC42CRS_OFFSET)
+#define XMC4_CCU40_CC42TIMER          (XMC4_CCU40_BASE+XMC4_CCU4_CC42TIMER_OFFSET)
+#define XMC4_CCU40_CC42C0V            (XMC4_CCU40_BASE+XMC4_CCU4_CC42C0V_OFFSET)
+#define XMC4_CCU40_CC42C1V            (XMC4_CCU40_BASE+XMC4_CCU4_CC42C1V_OFFSET)
+#define XMC4_CCU40_CC42C2V            (XMC4_CCU40_BASE+XMC4_CCU4_CC42C2V_OFFSET)
+#define XMC4_CCU40_CC42C3V            (XMC4_CCU40_BASE+XMC4_CCU4_CC42C3V_OFFSET)
+#define XMC4_CCU40_CC42INTS           (XMC4_CCU40_BASE+XMC4_CCU4_CC42INTS_OFFSET)
+#define XMC4_CCU40_CC42INTE           (XMC4_CCU40_BASE+XMC4_CCU4_CC42INTE_OFFSET)
+#define XMC4_CCU40_CC42SRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC42SRS_OFFSET)
+#define XMC4_CCU40_CC42SWS            (XMC4_CCU40_BASE+XMC4_CCU4_CC42SWS_OFFSET)
+#define XMC4_CCU40_CC42SWR            (XMC4_CCU40_BASE+XMC4_CCU4_CC42SWR_OFFSET)
+#define XMC4_CCU40_CC42ECRD0          (XMC4_CCU40_BASE+XMC4_CCU4_CC42ECRD0_OFFSET)
+#define XMC4_CCU40_CC42ECRD1          (XMC4_CCU40_BASE+XMC4_CCU4_CC42ECRD1_OFFSET)
+
+/* CCU40 CC43 Slice Registers */
+
+#define XMC4_CCU40_CC43INS            (XMC4_CCU40_BASE+XMC4_CCU4_CC43INS_OFFSET)
+#define XMC4_CCU40_CC43CMC            (XMC4_CCU40_BASE+XMC4_CCU4_CC43CMC_OFFSET)
+#define XMC4_CCU40_CC43TST            (XMC4_CCU40_BASE+XMC4_CCU4_CC43TST_OFFSET)
+#define XMC4_CCU40_CC43TCSET          (XMC4_CCU40_BASE+XMC4_CCU4_CC43TCSET_OFFSET)
+#define XMC4_CCU40_CC43TCCLR          (XMC4_CCU40_BASE+XMC4_CCU4_CC43TCCLR_OFFSET)
+#define XMC4_CCU40_CC43TC             (XMC4_CCU40_BASE+XMC4_CCU4_CC43TC_OFFSET)
+#define XMC4_CCU40_CC43PSL            (XMC4_CCU40_BASE+XMC4_CCU4_CC43PSL_OFFSET)
+#define XMC4_CCU40_CC43DIT            (XMC4_CCU40_BASE+XMC4_CCU4_CC43DIT_OFFSET)
+#define XMC4_CCU40_CC43DITS           (XMC4_CCU40_BASE+XMC4_CCU4_CC43DITS_OFFSET)
+#define XMC4_CCU40_CC43PSC            (XMC4_CCU40_BASE+XMC4_CCU4_CC43PSC_OFFSET)
+#define XMC4_CCU40_CC43FPC            (XMC4_CCU40_BASE+XMC4_CCU4_CC43FPC_OFFSET)
+#define XMC4_CCU40_CC43FPCS           (XMC4_CCU40_BASE+XMC4_CCU4_CC43FPCS_OFFSET)
+#define XMC4_CCU40_CC43PR             (XMC4_CCU40_BASE+XMC4_CCU4_CC43PR_OFFSET)
+#define XMC4_CCU40_CC43PRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC43PRS_OFFSET)
+#define XMC4_CCU40_CC43CR             (XMC4_CCU40_BASE+XMC4_CCU4_CC43CR_OFFSET)
+#define XMC4_CCU40_CC43CRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC43CRS_OFFSET)
+#define XMC4_CCU40_CC43TIMER          (XMC4_CCU40_BASE+XMC4_CCU4_CC43TIMER_OFFSET)
+#define XMC4_CCU40_CC43C0V            (XMC4_CCU40_BASE+XMC4_CCU4_CC43C0V_OFFSET)
+#define XMC4_CCU40_CC43C1V            (XMC4_CCU40_BASE+XMC4_CCU4_CC43C1V_OFFSET)
+#define XMC4_CCU40_CC43C2V            (XMC4_CCU40_BASE+XMC4_CCU4_CC43C2V_OFFSET)
+#define XMC4_CCU40_CC43C3V            (XMC4_CCU40_BASE+XMC4_CCU4_CC43C3V_OFFSET)
+#define XMC4_CCU40_CC43INTS           (XMC4_CCU40_BASE+XMC4_CCU4_CC43INTS_OFFSET)
+#define XMC4_CCU40_CC43INTE           (XMC4_CCU40_BASE+XMC4_CCU4_CC43INTE_OFFSET)
+#define XMC4_CCU40_CC43SRS            (XMC4_CCU40_BASE+XMC4_CCU4_CC43SRS_OFFSET)
+#define XMC4_CCU40_CC43SWS            (XMC4_CCU40_BASE+XMC4_CCU4_CC43SWS_OFFSET)
+#define XMC4_CCU40_CC43SWR            (XMC4_CCU40_BASE+XMC4_CCU4_CC43SWR_OFFSET)
+#define XMC4_CCU40_CC43ECRD0          (XMC4_CCU40_BASE+XMC4_CCU4_CC43ECRD0_OFFSET)
+#define XMC4_CCU40_CC43ECRD1          (XMC4_CCU40_BASE+XMC4_CCU4_CC43ECRD1_OFFSET)
+
+/* CCU41 Global Registers */

 #define XMC4_CCU41_GCTRL             (XMC4_CCU41_BASE+XMC4_CCU4_GCTRL_OFFSET)
 #define XMC4_CCU41_GSTAT             (XMC4_CCU41_BASE+XMC4_CCU4_GSTAT_OFFSET)
@ -253,36 +348,131 @@
 #define XMC4_CCU41_GCST              (XMC4_CCU41_BASE+XMC4_CCU4_GCST_OFFSET)
 #define XMC4_CCU41_MIDR              (XMC4_CCU41_BASE+XMC4_CCU4_MIDR_OFFSET)

-#define XMC4_CCU4_CC41INS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41INS_OFFSET)
-#define XMC4_CCU4_CC41CMC            (XMC4_CCU41_BASE+XMC4_CCU4_CC41CMC_OFFSET)
-#define XMC4_CCU4_CC41TST            (XMC4_CCU41_BASE+XMC4_CCU4_CC41TST_OFFSET)
-#define XMC4_CCU4_CC41TCSET          (XMC4_CCU41_BASE+XMC4_CCU4_CC41TCSET_OFFSET)
-#define XMC4_CCU4_CC41TCCLR          (XMC4_CCU41_BASE+XMC4_CCU4_CC41TCCLR_OFFSET)
-#define XMC4_CCU4_CC41TC             (XMC4_CCU41_BASE+XMC4_CCU4_CC41TC_OFFSET)
-#define XMC4_CCU4_CC41PSL            (XMC4_CCU41_BASE+XMC4_CCU4_CC41PSL_OFFSET)
-#define XMC4_CCU4_CC41DIT            (XMC4_CCU41_BASE+XMC4_CCU4_CC41DIT_OFFSET)
-#define XMC4_CCU4_CC41DITS           (XMC4_CCU41_BASE+XMC4_CCU4_CC41DITS_OFFSET)
-#define XMC4_CCU4_CC41PSC            (XMC4_CCU41_BASE+XMC4_CCU4_CC41PSC_OFFSET)
-#define XMC4_CCU4_CC41FPC            (XMC4_CCU41_BASE+XMC4_CCU4_CC41FPC_OFFSET)
-#define XMC4_CCU4_CC41FPCS           (XMC4_CCU41_BASE+XMC4_CCU4_CC41FPCS_OFFSET)
-#define XMC4_CCU4_CC41PR             (XMC4_CCU41_BASE+XMC4_CCU4_CC41PR_OFFSET)
-#define XMC4_CCU4_CC41PRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41PRS_OFFSET)
-#define XMC4_CCU4_CC41CR             (XMC4_CCU41_BASE+XMC4_CCU4_CC41CR_OFFSET)
-#define XMC4_CCU4_CC41CRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41CRS_OFFSET)
-#define XMC4_CCU4_CC41TIMER          (XMC4_CCU41_BASE+XMC4_CCU4_CC41TIMER_OFFSET)
-#define XMC4_CCU4_CC41C0V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C0V_OFFSET)
-#define XMC4_CCU4_CC41C1V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C1V_OFFSET)
-#define XMC4_CCU4_CC41C2V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C2V_OFFSET)
-#define XMC4_CCU4_CC41C3V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C3V_OFFSET)
-#define XMC4_CCU4_CC41INTS           (XMC4_CCU41_BASE+XMC4_CCU4_CC41INTS_OFFSET)
-#define XMC4_CCU4_CC41INTE           (XMC4_CCU41_BASE+XMC4_CCU4_CC41INTE_OFFSET)
-#define XMC4_CCU4_CC41SRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41SRS_OFFSET)
-#define XMC4_CCU4_CC41SWS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41SWS_OFFSET)
-#define XMC4_CCU4_CC41SWR            (XMC4_CCU41_BASE+XMC4_CCU4_CC41SWR_OFFSET)
-#define XMC4_CCU4_CC41ECRD0          (XMC4_CCU41_BASE+XMC4_CCU4_CC41ECRD0_OFFSET)
-#define XMC4_CCU4_CC41ECRD1          (XMC4_CCU41_BASE+XMC4_CCU4_CC41ECRD1_OFFSET)
+/* CCU41 CC40 Slice Registers */

-/* CCU42 Registers */
+#define XMC4_CCU41_CC40INS            (XMC4_CCU41_BASE+XMC4_CCU4_CC40INS_OFFSET)
+#define XMC4_CCU41_CC40CMC            (XMC4_CCU41_BASE+XMC4_CCU4_CC40CMC_OFFSET)
+#define XMC4_CCU41_CC40TST            (XMC4_CCU41_BASE+XMC4_CCU4_CC40TST_OFFSET)
+#define XMC4_CCU41_CC40TCSET          (XMC4_CCU41_BASE+XMC4_CCU4_CC40TCSET_OFFSET)
+#define XMC4_CCU41_CC40TCCLR          (XMC4_CCU41_BASE+XMC4_CCU4_CC40TCCLR_OFFSET)
+#define XMC4_CCU41_CC40TC             (XMC4_CCU41_BASE+XMC4_CCU4_CC40TC_OFFSET)
+#define XMC4_CCU41_CC40PSL            (XMC4_CCU41_BASE+XMC4_CCU4_CC40PSL_OFFSET)
+#define XMC4_CCU41_CC40DIT            (XMC4_CCU41_BASE+XMC4_CCU4_CC40DIT_OFFSET)
+#define XMC4_CCU41_CC40DITS           (XMC4_CCU41_BASE+XMC4_CCU4_CC40DITS_OFFSET)
+#define XMC4_CCU41_CC40PSC            (XMC4_CCU41_BASE+XMC4_CCU4_CC40PSC_OFFSET)
+#define XMC4_CCU41_CC40FPC            (XMC4_CCU41_BASE+XMC4_CCU4_CC40FPC_OFFSET)
+#define XMC4_CCU41_CC40FPCS           (XMC4_CCU41_BASE+XMC4_CCU4_CC40FPCS_OFFSET)
+#define XMC4_CCU41_CC40PR             (XMC4_CCU41_BASE+XMC4_CCU4_CC40PR_OFFSET)
+#define XMC4_CCU41_CC40PRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC40PRS_OFFSET)
+#define XMC4_CCU41_CC40CR             (XMC4_CCU41_BASE+XMC4_CCU4_CC40CR_OFFSET)
+#define XMC4_CCU41_CC40CRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC40CRS_OFFSET)
+#define XMC4_CCU41_CC40TIMER          (XMC4_CCU41_BASE+XMC4_CCU4_CC40TIMER_OFFSET)
+#define XMC4_CCU41_CC40C0V            (XMC4_CCU41_BASE+XMC4_CCU4_CC40C0V_OFFSET)
+#define XMC4_CCU41_CC40C1V            (XMC4_CCU41_BASE+XMC4_CCU4_CC40C1V_OFFSET)
+#define XMC4_CCU41_CC40C2V            (XMC4_CCU41_BASE+XMC4_CCU4_CC40C2V_OFFSET)
+#define XMC4_CCU41_CC40C3V            (XMC4_CCU41_BASE+XMC4_CCU4_CC40C3V_OFFSET)
+#define XMC4_CCU41_CC40INTS           (XMC4_CCU41_BASE+XMC4_CCU4_CC40INTS_OFFSET)
+#define XMC4_CCU41_CC40INTE           (XMC4_CCU41_BASE+XMC4_CCU4_CC40INTE_OFFSET)
+#define XMC4_CCU41_CC40SRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC40SRS_OFFSET)
+#define XMC4_CCU41_CC40SWS            (XMC4_CCU41_BASE+XMC4_CCU4_CC40SWS_OFFSET)
+#define XMC4_CCU41_CC40SWR            (XMC4_CCU41_BASE+XMC4_CCU4_CC40SWR_OFFSET)
+#define XMC4_CCU41_CC40ECRD0          (XMC4_CCU41_BASE+XMC4_CCU4_CC40ECRD0_OFFSET)
+#define XMC4_CCU41_CC40ECRD1          (XMC4_CCU41_BASE+XMC4_CCU4_CC40ECRD1_OFFSET)
+
+/* CCU41 CC41 Slice Registers */
+
+#define XMC4_CCU41_CC41INS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41INS_OFFSET)
+#define XMC4_CCU41_CC41CMC            (XMC4_CCU41_BASE+XMC4_CCU4_CC41CMC_OFFSET)
+#define XMC4_CCU41_CC41TST            (XMC4_CCU41_BASE+XMC4_CCU4_CC41TST_OFFSET)
+#define XMC4_CCU41_CC41TCSET          (XMC4_CCU41_BASE+XMC4_CCU4_CC41TCSET_OFFSET)
+#define XMC4_CCU41_CC41TCCLR          (XMC4_CCU41_BASE+XMC4_CCU4_CC41TCCLR_OFFSET)
+#define XMC4_CCU41_CC41TC             (XMC4_CCU41_BASE+XMC4_CCU4_CC41TC_OFFSET)
+#define XMC4_CCU41_CC41PSL            (XMC4_CCU41_BASE+XMC4_CCU4_CC41PSL_OFFSET)
+#define XMC4_CCU41_CC41DIT            (XMC4_CCU41_BASE+XMC4_CCU4_CC41DIT_OFFSET)
+#define XMC4_CCU41_CC41DITS           (XMC4_CCU41_BASE+XMC4_CCU4_CC41DITS_OFFSET)
+#define XMC4_CCU41_CC41PSC            (XMC4_CCU41_BASE+XMC4_CCU4_CC41PSC_OFFSET)
+#define XMC4_CCU41_CC41FPC            (XMC4_CCU41_BASE+XMC4_CCU4_CC41FPC_OFFSET)
+#define XMC4_CCU41_CC41FPCS           (XMC4_CCU41_BASE+XMC4_CCU4_CC41FPCS_OFFSET)
+#define XMC4_CCU41_CC41PR             (XMC4_CCU41_BASE+XMC4_CCU4_CC41PR_OFFSET)
+#define XMC4_CCU41_CC41PRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41PRS_OFFSET)
+#define XMC4_CCU41_CC41CR             (XMC4_CCU41_BASE+XMC4_CCU4_CC41CR_OFFSET)
+#define XMC4_CCU41_CC41CRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41CRS_OFFSET)
+#define XMC4_CCU41_CC41TIMER          (XMC4_CCU41_BASE+XMC4_CCU4_CC41TIMER_OFFSET)
+#define XMC4_CCU41_CC41C0V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C0V_OFFSET)
+#define XMC4_CCU41_CC41C1V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C1V_OFFSET)
+#define XMC4_CCU41_CC41C2V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C2V_OFFSET)
+#define XMC4_CCU41_CC41C3V            (XMC4_CCU41_BASE+XMC4_CCU4_CC41C3V_OFFSET)
+#define XMC4_CCU41_CC41INTS           (XMC4_CCU41_BASE+XMC4_CCU4_CC41INTS_OFFSET)
+#define XMC4_CCU41_CC41INTE           (XMC4_CCU41_BASE+XMC4_CCU4_CC41INTE_OFFSET)
+#define XMC4_CCU41_CC41SRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41SRS_OFFSET)
+#define XMC4_CCU41_CC41SWS            (XMC4_CCU41_BASE+XMC4_CCU4_CC41SWS_OFFSET)
+#define XMC4_CCU41_CC41SWR            (XMC4_CCU41_BASE+XMC4_CCU4_CC41SWR_OFFSET)
+#define XMC4_CCU41_CC41ECRD0          (XMC4_CCU41_BASE+XMC4_CCU4_CC41ECRD0_OFFSET)
+#define XMC4_CCU41_CC41ECRD1          (XMC4_CCU41_BASE+XMC4_CCU4_CC41ECRD1_OFFSET)
+
+/* CCU41 CC42 Slice Registers */
+
+#define XMC4_CCU41_CC42INS            (XMC4_CCU41_BASE+XMC4_CCU4_CC42INS_OFFSET)
+#define XMC4_CCU41_CC42CMC            (XMC4_CCU41_BASE+XMC4_CCU4_CC42CMC_OFFSET)
+#define XMC4_CCU41_CC42TST            (XMC4_CCU41_BASE+XMC4_CCU4_CC42TST_OFFSET)
+#define XMC4_CCU41_CC42TCSET          (XMC4_CCU41_BASE+XMC4_CCU4_CC42TCSET_OFFSET)
+#define XMC4_CCU41_CC42TCCLR          (XMC4_CCU41_BASE+XMC4_CCU4_CC42TCCLR_OFFSET)
+#define XMC4_CCU41_CC42TC             (XMC4_CCU41_BASE+XMC4_CCU4_CC42TC_OFFSET)
+#define XMC4_CCU41_CC42PSL            (XMC4_CCU41_BASE+XMC4_CCU4_CC42PSL_OFFSET)
+#define XMC4_CCU41_CC42DIT            (XMC4_CCU41_BASE+XMC4_CCU4_CC42DIT_OFFSET)
+#define XMC4_CCU41_CC42DITS           (XMC4_CCU41_BASE+XMC4_CCU4_CC42DITS_OFFSET)
+#define XMC4_CCU41_CC42PSC            (XMC4_CCU41_BASE+XMC4_CCU4_CC42PSC_OFFSET)
+#define XMC4_CCU41_CC42FPC            (XMC4_CCU41_BASE+XMC4_CCU4_CC42FPC_OFFSET)
+#define XMC4_CCU41_CC42FPCS           (XMC4_CCU41_BASE+XMC4_CCU4_CC42FPCS_OFFSET)
+#define XMC4_CCU41_CC42PR             (XMC4_CCU41_BASE+XMC4_CCU4_CC42PR_OFFSET)
+#define XMC4_CCU41_CC42PRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC42PRS_OFFSET)
+#define XMC4_CCU41_CC42CR             (XMC4_CCU41_BASE+XMC4_CCU4_CC42CR_OFFSET)
+#define XMC4_CCU41_CC42CRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC42CRS_OFFSET)
+#define XMC4_CCU41_CC42TIMER          (XMC4_CCU41_BASE+XMC4_CCU4_CC42TIMER_OFFSET)
+#define XMC4_CCU41_CC42C0V            (XMC4_CCU41_BASE+XMC4_CCU4_CC42C0V_OFFSET)
+#define XMC4_CCU41_CC42C1V            (XMC4_CCU41_BASE+XMC4_CCU4_CC42C1V_OFFSET)
+#define XMC4_CCU41_CC42C2V            (XMC4_CCU41_BASE+XMC4_CCU4_CC42C2V_OFFSET)
+#define XMC4_CCU41_CC42C3V            (XMC4_CCU41_BASE+XMC4_CCU4_CC42C3V_OFFSET)
+#define XMC4_CCU41_CC42INTS           (XMC4_CCU41_BASE+XMC4_CCU4_CC42INTS_OFFSET)
+#define XMC4_CCU41_CC42INTE           (XMC4_CCU41_BASE+XMC4_CCU4_CC42INTE_OFFSET)
+#define XMC4_CCU41_CC42SRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC42SRS_OFFSET)
+#define XMC4_CCU41_CC42SWS            (XMC4_CCU41_BASE+XMC4_CCU4_CC42SWS_OFFSET)
+#define XMC4_CCU41_CC42SWR            (XMC4_CCU41_BASE+XMC4_CCU4_CC42SWR_OFFSET)
+#define XMC4_CCU41_CC42ECRD0          (XMC4_CCU41_BASE+XMC4_CCU4_CC42ECRD0_OFFSET)
+#define XMC4_CCU41_CC42ECRD1          (XMC4_CCU41_BASE+XMC4_CCU4_CC42ECRD1_OFFSET)
+
+/* CCU41 CC43 Slice Registers */
+
+#define XMC4_CCU41_CC43INS            (XMC4_CCU41_BASE+XMC4_CCU4_CC43INS_OFFSET)
+#define XMC4_CCU41_CC43CMC            (XMC4_CCU41_BASE+XMC4_CCU4_CC43CMC_OFFSET)
+#define XMC4_CCU41_CC43TST            (XMC4_CCU41_BASE+XMC4_CCU4_CC43TST_OFFSET)
+#define XMC4_CCU41_CC43TCSET          (XMC4_CCU41_BASE+XMC4_CCU4_CC43TCSET_OFFSET)
+#define XMC4_CCU41_CC43TCCLR          (XMC4_CCU41_BASE+XMC4_CCU4_CC43TCCLR_OFFSET)
+#define XMC4_CCU41_CC43TC             (XMC4_CCU41_BASE+XMC4_CCU4_CC43TC_OFFSET)
+#define XMC4_CCU41_CC43PSL            (XMC4_CCU41_BASE+XMC4_CCU4_CC43PSL_OFFSET)
+#define XMC4_CCU41_CC43DIT            (XMC4_CCU41_BASE+XMC4_CCU4_CC43DIT_OFFSET)
+#define XMC4_CCU41_CC43DITS           (XMC4_CCU41_BASE+XMC4_CCU4_CC43DITS_OFFSET)
+#define XMC4_CCU41_CC43PSC            (XMC4_CCU41_BASE+XMC4_CCU4_CC43PSC_OFFSET)
+#define XMC4_CCU41_CC43FPC            (XMC4_CCU41_BASE+XMC4_CCU4_CC43FPC_OFFSET)
+#define XMC4_CCU41_CC43FPCS           (XMC4_CCU41_BASE+XMC4_CCU4_CC43FPCS_OFFSET)
+#define XMC4_CCU41_CC43PR             (XMC4_CCU41_BASE+XMC4_CCU4_CC43PR_OFFSET)
+#define XMC4_CCU41_CC43PRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC43PRS_OFFSET)
+#define XMC4_CCU41_CC43CR             (XMC4_CCU41_BASE+XMC4_CCU4_CC43CR_OFFSET)
+#define XMC4_CCU41_CC43CRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC43CRS_OFFSET)
+#define XMC4_CCU41_CC43TIMER          (XMC4_CCU41_BASE+XMC4_CCU4_CC43TIMER_OFFSET)
+#define XMC4_CCU41_CC43C0V            (XMC4_CCU41_BASE+XMC4_CCU4_CC43C0V_OFFSET)
+#define XMC4_CCU41_CC43C1V            (XMC4_CCU41_BASE+XMC4_CCU4_CC43C1V_OFFSET)
+#define XMC4_CCU41_CC43C2V            (XMC4_CCU41_BASE+XMC4_CCU4_CC43C2V_OFFSET)
+#define XMC4_CCU41_CC43C3V            (XMC4_CCU41_BASE+XMC4_CCU4_CC43C3V_OFFSET)
+#define XMC4_CCU41_CC43INTS           (XMC4_CCU41_BASE+XMC4_CCU4_CC43INTS_OFFSET)
+#define XMC4_CCU41_CC43INTE           (XMC4_CCU41_BASE+XMC4_CCU4_CC43INTE_OFFSET)
+#define XMC4_CCU41_CC43SRS            (XMC4_CCU41_BASE+XMC4_CCU4_CC43SRS_OFFSET)
+#define XMC4_CCU41_CC43SWS            (XMC4_CCU41_BASE+XMC4_CCU4_CC43SWS_OFFSET)
+#define XMC4_CCU41_CC43SWR            (XMC4_CCU41_BASE+XMC4_CCU4_CC43SWR_OFFSET)
+#define XMC4_CCU41_CC43ECRD0          (XMC4_CCU41_BASE+XMC4_CCU4_CC43ECRD0_OFFSET)
+#define XMC4_CCU41_CC43ECRD1          (XMC4_CCU41_BASE+XMC4_CCU4_CC43ECRD1_OFFSET)
+
+/* CCU42 Global Registers */

 #define XMC4_CCU42_GCTRL             (XMC4_CCU42_BASE+XMC4_CCU4_GCTRL_OFFSET)
 #define XMC4_CCU42_GSTAT             (XMC4_CCU42_BASE+XMC4_CCU4_GSTAT_OFFSET)
@ -293,36 +483,131 @@
 #define XMC4_CCU42_GCST              (XMC4_CCU42_BASE+XMC4_CCU4_GCST_OFFSET)
 #define XMC4_CCU42_MIDR              (XMC4_CCU42_BASE+XMC4_CCU4_MIDR_OFFSET)

-#define XMC4_CCU4_CC42INS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42INS_OFFSET)
-#define XMC4_CCU4_CC42CMC            (XMC4_CCU42_BASE+XMC4_CCU4_CC42CMC_OFFSET)
-#define XMC4_CCU4_CC42TST            (XMC4_CCU42_BASE+XMC4_CCU4_CC42TST_OFFSET)
-#define XMC4_CCU4_CC42TCSET          (XMC4_CCU42_BASE+XMC4_CCU4_CC42TCSET_OFFSET)
-#define XMC4_CCU4_CC42TCCLR          (XMC4_CCU42_BASE+XMC4_CCU4_CC42TCCLR_OFFSET)
-#define XMC4_CCU4_CC42TC             (XMC4_CCU42_BASE+XMC4_CCU4_CC42TC_OFFSET)
-#define XMC4_CCU4_CC42PSL            (XMC4_CCU42_BASE+XMC4_CCU4_CC42PSL_OFFSET)
-#define XMC4_CCU4_CC42DIT            (XMC4_CCU42_BASE+XMC4_CCU4_CC42DIT_OFFSET)
-#define XMC4_CCU4_CC42DITS           (XMC4_CCU42_BASE+XMC4_CCU4_CC42DITS_OFFSET)
-#define XMC4_CCU4_CC42PSC            (XMC4_CCU42_BASE+XMC4_CCU4_CC42PSC_OFFSET)
-#define XMC4_CCU4_CC42FPC            (XMC4_CCU42_BASE+XMC4_CCU4_CC42FPC_OFFSET)
-#define XMC4_CCU4_CC42FPCS           (XMC4_CCU42_BASE+XMC4_CCU4_CC42FPCS_OFFSET)
-#define XMC4_CCU4_CC42PR             (XMC4_CCU42_BASE+XMC4_CCU4_CC42PR_OFFSET)
-#define XMC4_CCU4_CC42PRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42PRS_OFFSET)
-#define XMC4_CCU4_CC42CR             (XMC4_CCU42_BASE+XMC4_CCU4_CC42CR_OFFSET)
-#define XMC4_CCU4_CC42CRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42CRS_OFFSET)
-#define XMC4_CCU4_CC42TIMER          (XMC4_CCU42_BASE+XMC4_CCU4_CC42TIMER_OFFSET)
-#define XMC4_CCU4_CC42C0V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C0V_OFFSET)
-#define XMC4_CCU4_CC42C1V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C1V_OFFSET)
-#define XMC4_CCU4_CC42C2V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C2V_OFFSET)
-#define XMC4_CCU4_CC42C3V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C3V_OFFSET)
-#define XMC4_CCU4_CC42INTS           (XMC4_CCU42_BASE+XMC4_CCU4_CC42INTS_OFFSET)
-#define XMC4_CCU4_CC42INTE           (XMC4_CCU42_BASE+XMC4_CCU4_CC42INTE_OFFSET)
-#define XMC4_CCU4_CC42SRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42SRS_OFFSET)
-#define XMC4_CCU4_CC42SWS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42SWS_OFFSET)
-#define XMC4_CCU4_CC42SWR            (XMC4_CCU42_BASE+XMC4_CCU4_CC42SWR_OFFSET)
-#define XMC4_CCU4_CC42ECRD0          (XMC4_CCU42_BASE+XMC4_CCU4_CC42ECRD0_OFFSET)
-#define XMC4_CCU4_CC42ECRD1          (XMC4_CCU42_BASE+XMC4_CCU4_CC42ECRD1_OFFSET)
+/* CCU42 CC40 Slice Registers */

-/* CCU43 Registers */
+#define XMC4_CCU42_CC40INS            (XMC4_CCU42_BASE+XMC4_CCU4_CC40INS_OFFSET)
+#define XMC4_CCU42_CC40CMC            (XMC4_CCU42_BASE+XMC4_CCU4_CC40CMC_OFFSET)
+#define XMC4_CCU42_CC40TST            (XMC4_CCU42_BASE+XMC4_CCU4_CC40TST_OFFSET)
+#define XMC4_CCU42_CC40TCSET          (XMC4_CCU42_BASE+XMC4_CCU4_CC40TCSET_OFFSET)
+#define XMC4_CCU42_CC40TCCLR          (XMC4_CCU42_BASE+XMC4_CCU4_CC40TCCLR_OFFSET)
+#define XMC4_CCU42_CC40TC             (XMC4_CCU42_BASE+XMC4_CCU4_CC40TC_OFFSET)
+#define XMC4_CCU42_CC40PSL            (XMC4_CCU42_BASE+XMC4_CCU4_CC40PSL_OFFSET)
+#define XMC4_CCU42_CC40DIT            (XMC4_CCU42_BASE+XMC4_CCU4_CC40DIT_OFFSET)
+#define XMC4_CCU42_CC40DITS           (XMC4_CCU42_BASE+XMC4_CCU4_CC40DITS_OFFSET)
+#define XMC4_CCU42_CC40PSC            (XMC4_CCU42_BASE+XMC4_CCU4_CC40PSC_OFFSET)
+#define XMC4_CCU42_CC40FPC            (XMC4_CCU42_BASE+XMC4_CCU4_CC40FPC_OFFSET)
+#define XMC4_CCU42_CC40FPCS           (XMC4_CCU42_BASE+XMC4_CCU4_CC40FPCS_OFFSET)
+#define XMC4_CCU42_CC40PR             (XMC4_CCU42_BASE+XMC4_CCU4_CC40PR_OFFSET)
+#define XMC4_CCU42_CC40PRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC40PRS_OFFSET)
+#define XMC4_CCU42_CC40CR             (XMC4_CCU42_BASE+XMC4_CCU4_CC40CR_OFFSET)
+#define XMC4_CCU42_CC40CRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC40CRS_OFFSET)
+#define XMC4_CCU42_CC40TIMER          (XMC4_CCU42_BASE+XMC4_CCU4_CC40TIMER_OFFSET)
+#define XMC4_CCU42_CC40C0V            (XMC4_CCU42_BASE+XMC4_CCU4_CC40C0V_OFFSET)
+#define XMC4_CCU42_CC40C1V            (XMC4_CCU42_BASE+XMC4_CCU4_CC40C1V_OFFSET)
+#define XMC4_CCU42_CC40C2V            (XMC4_CCU42_BASE+XMC4_CCU4_CC40C2V_OFFSET)
+#define XMC4_CCU42_CC40C3V            (XMC4_CCU42_BASE+XMC4_CCU4_CC40C3V_OFFSET)
+#define XMC4_CCU42_CC40INTS           (XMC4_CCU42_BASE+XMC4_CCU4_CC40INTS_OFFSET)
+#define XMC4_CCU42_CC40INTE           (XMC4_CCU42_BASE+XMC4_CCU4_CC40INTE_OFFSET)
+#define XMC4_CCU42_CC40SRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC40SRS_OFFSET)
+#define XMC4_CCU42_CC40SWS            (XMC4_CCU42_BASE+XMC4_CCU4_CC40SWS_OFFSET)
+#define XMC4_CCU42_CC40SWR            (XMC4_CCU42_BASE+XMC4_CCU4_CC40SWR_OFFSET)
+#define XMC4_CCU42_CC40ECRD0          (XMC4_CCU42_BASE+XMC4_CCU4_CC40ECRD0_OFFSET)
+#define XMC4_CCU42_CC40ECRD1          (XMC4_CCU42_BASE+XMC4_CCU4_CC40ECRD1_OFFSET)
+
+/* CCU42 CC41 Slice Registers */
+
+#define XMC4_CCU42_CC41INS            (XMC4_CCU42_BASE+XMC4_CCU4_CC41INS_OFFSET)
+#define XMC4_CCU42_CC41CMC            (XMC4_CCU42_BASE+XMC4_CCU4_CC41CMC_OFFSET)
+#define XMC4_CCU42_CC41TST            (XMC4_CCU42_BASE+XMC4_CCU4_CC41TST_OFFSET)
+#define XMC4_CCU42_CC41TCSET          (XMC4_CCU42_BASE+XMC4_CCU4_CC41TCSET_OFFSET)
+#define XMC4_CCU42_CC41TCCLR          (XMC4_CCU42_BASE+XMC4_CCU4_CC41TCCLR_OFFSET)
+#define XMC4_CCU42_CC41TC             (XMC4_CCU42_BASE+XMC4_CCU4_CC41TC_OFFSET)
+#define XMC4_CCU42_CC41PSL            (XMC4_CCU42_BASE+XMC4_CCU4_CC41PSL_OFFSET)
+#define XMC4_CCU42_CC41DIT            (XMC4_CCU42_BASE+XMC4_CCU4_CC41DIT_OFFSET)
+#define XMC4_CCU42_CC41DITS           (XMC4_CCU42_BASE+XMC4_CCU4_CC41DITS_OFFSET)
+#define XMC4_CCU42_CC41PSC            (XMC4_CCU42_BASE+XMC4_CCU4_CC41PSC_OFFSET)
+#define XMC4_CCU42_CC41FPC            (XMC4_CCU42_BASE+XMC4_CCU4_CC41FPC_OFFSET)
+#define XMC4_CCU42_CC41FPCS           (XMC4_CCU42_BASE+XMC4_CCU4_CC41FPCS_OFFSET)
+#define XMC4_CCU42_CC41PR             (XMC4_CCU42_BASE+XMC4_CCU4_CC41PR_OFFSET)
+#define XMC4_CCU42_CC41PRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC41PRS_OFFSET)
+#define XMC4_CCU42_CC41CR             (XMC4_CCU42_BASE+XMC4_CCU4_CC41CR_OFFSET)
+#define XMC4_CCU42_CC41CRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC41CRS_OFFSET)
+#define XMC4_CCU42_CC41TIMER          (XMC4_CCU42_BASE+XMC4_CCU4_CC41TIMER_OFFSET)
+#define XMC4_CCU42_CC41C0V            (XMC4_CCU42_BASE+XMC4_CCU4_CC41C0V_OFFSET)
+#define XMC4_CCU42_CC41C1V            (XMC4_CCU42_BASE+XMC4_CCU4_CC41C1V_OFFSET)
+#define XMC4_CCU42_CC41C2V            (XMC4_CCU42_BASE+XMC4_CCU4_CC41C2V_OFFSET)
+#define XMC4_CCU42_CC41C3V            (XMC4_CCU42_BASE+XMC4_CCU4_CC41C3V_OFFSET)
+#define XMC4_CCU42_CC41INTS           (XMC4_CCU42_BASE+XMC4_CCU4_CC41INTS_OFFSET)
+#define XMC4_CCU42_CC41INTE           (XMC4_CCU42_BASE+XMC4_CCU4_CC41INTE_OFFSET)
+#define XMC4_CCU42_CC41SRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC41SRS_OFFSET)
+#define XMC4_CCU42_CC41SWS            (XMC4_CCU42_BASE+XMC4_CCU4_CC41SWS_OFFSET)
+#define XMC4_CCU42_CC41SWR            (XMC4_CCU42_BASE+XMC4_CCU4_CC41SWR_OFFSET)
+#define XMC4_CCU42_CC41ECRD0          (XMC4_CCU42_BASE+XMC4_CCU4_CC41ECRD0_OFFSET)
+#define XMC4_CCU42_CC41ECRD1          (XMC4_CCU42_BASE+XMC4_CCU4_CC41ECRD1_OFFSET)
+
+/* CCU42 CC42 Slice Registers */
+
+#define XMC4_CCU42_CC42INS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42INS_OFFSET)
+#define XMC4_CCU42_CC42CMC            (XMC4_CCU42_BASE+XMC4_CCU4_CC42CMC_OFFSET)
+#define XMC4_CCU42_CC42TST            (XMC4_CCU42_BASE+XMC4_CCU4_CC42TST_OFFSET)
+#define XMC4_CCU42_CC42TCSET          (XMC4_CCU42_BASE+XMC4_CCU4_CC42TCSET_OFFSET)
+#define XMC4_CCU42_CC42TCCLR          (XMC4_CCU42_BASE+XMC4_CCU4_CC42TCCLR_OFFSET)
+#define XMC4_CCU42_CC42TC             (XMC4_CCU42_BASE+XMC4_CCU4_CC42TC_OFFSET)
+#define XMC4_CCU42_CC42PSL            (XMC4_CCU42_BASE+XMC4_CCU4_CC42PSL_OFFSET)
+#define XMC4_CCU42_CC42DIT            (XMC4_CCU42_BASE+XMC4_CCU4_CC42DIT_OFFSET)
+#define XMC4_CCU42_CC42DITS           (XMC4_CCU42_BASE+XMC4_CCU4_CC42DITS_OFFSET)
+#define XMC4_CCU42_CC42PSC            (XMC4_CCU42_BASE+XMC4_CCU4_CC42PSC_OFFSET)
+#define XMC4_CCU42_CC42FPC            (XMC4_CCU42_BASE+XMC4_CCU4_CC42FPC_OFFSET)
+#define XMC4_CCU42_CC42FPCS           (XMC4_CCU42_BASE+XMC4_CCU4_CC42FPCS_OFFSET)
+#define XMC4_CCU42_CC42PR             (XMC4_CCU42_BASE+XMC4_CCU4_CC42PR_OFFSET)
+#define XMC4_CCU42_CC42PRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42PRS_OFFSET)
+#define XMC4_CCU42_CC42CR             (XMC4_CCU42_BASE+XMC4_CCU4_CC42CR_OFFSET)
+#define XMC4_CCU42_CC42CRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42CRS_OFFSET)
+#define XMC4_CCU42_CC42TIMER          (XMC4_CCU42_BASE+XMC4_CCU4_CC42TIMER_OFFSET)
+#define XMC4_CCU42_CC42C0V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C0V_OFFSET)
+#define XMC4_CCU42_CC42C1V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C1V_OFFSET)
+#define XMC4_CCU42_CC42C2V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C2V_OFFSET)
+#define XMC4_CCU42_CC42C3V            (XMC4_CCU42_BASE+XMC4_CCU4_CC42C3V_OFFSET)
+#define XMC4_CCU42_CC42INTS           (XMC4_CCU42_BASE+XMC4_CCU4_CC42INTS_OFFSET)
+#define XMC4_CCU42_CC42INTE           (XMC4_CCU42_BASE+XMC4_CCU4_CC42INTE_OFFSET)
+#define XMC4_CCU42_CC42SRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42SRS_OFFSET)
+#define XMC4_CCU42_CC42SWS            (XMC4_CCU42_BASE+XMC4_CCU4_CC42SWS_OFFSET)
+#define XMC4_CCU42_CC42SWR            (XMC4_CCU42_BASE+XMC4_CCU4_CC42SWR_OFFSET)
+#define XMC4_CCU42_CC42ECRD0          (XMC4_CCU42_BASE+XMC4_CCU4_CC42ECRD0_OFFSET)
+#define XMC4_CCU42_CC42ECRD1          (XMC4_CCU42_BASE+XMC4_CCU4_CC42ECRD1_OFFSET)
+
+/* CCU42 CC43 Slice Registers */
+
+#define XMC4_CCU42_CC43INS            (XMC4_CCU42_BASE+XMC4_CCU4_CC43INS_OFFSET)
+#define XMC4_CCU42_CC43CMC            (XMC4_CCU42_BASE+XMC4_CCU4_CC43CMC_OFFSET)
+#define XMC4_CCU42_CC43TST            (XMC4_CCU42_BASE+XMC4_CCU4_CC43TST_OFFSET)
+#define XMC4_CCU42_CC43TCSET          (XMC4_CCU42_BASE+XMC4_CCU4_CC43TCSET_OFFSET)
+#define XMC4_CCU42_CC43TCCLR          (XMC4_CCU42_BASE+XMC4_CCU4_CC43TCCLR_OFFSET)
+#define XMC4_CCU42_CC43TC             (XMC4_CCU42_BASE+XMC4_CCU4_CC43TC_OFFSET)
+#define XMC4_CCU42_CC43PSL            (XMC4_CCU42_BASE+XMC4_CCU4_CC43PSL_OFFSET)
+#define XMC4_CCU42_CC43DIT            (XMC4_CCU42_BASE+XMC4_CCU4_CC43DIT_OFFSET)
+#define XMC4_CCU42_CC43DITS           (XMC4_CCU42_BASE+XMC4_CCU4_CC43DITS_OFFSET)
+#define XMC4_CCU42_CC43PSC            (XMC4_CCU42_BASE+XMC4_CCU4_CC43PSC_OFFSET)
+#define XMC4_CCU42_CC43FPC            (XMC4_CCU42_BASE+XMC4_CCU4_CC43FPC_OFFSET)
+#define XMC4_CCU42_CC43FPCS           (XMC4_CCU42_BASE+XMC4_CCU4_CC43FPCS_OFFSET)
+#define XMC4_CCU42_CC43PR             (XMC4_CCU42_BASE+XMC4_CCU4_CC43PR_OFFSET)
+#define XMC4_CCU42_CC43PRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC43PRS_OFFSET)
+#define XMC4_CCU42_CC43CR             (XMC4_CCU42_BASE+XMC4_CCU4_CC43CR_OFFSET)
+#define XMC4_CCU42_CC43CRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC43CRS_OFFSET)
+#define XMC4_CCU42_CC43TIMER          (XMC4_CCU42_BASE+XMC4_CCU4_CC43TIMER_OFFSET)
+#define XMC4_CCU42_CC43C0V            (XMC4_CCU42_BASE+XMC4_CCU4_CC43C0V_OFFSET)
+#define XMC4_CCU42_CC43C1V            (XMC4_CCU42_BASE+XMC4_CCU4_CC43C1V_OFFSET)
+#define XMC4_CCU42_CC43C2V            (XMC4_CCU42_BASE+XMC4_CCU4_CC43C2V_OFFSET)
+#define XMC4_CCU42_CC43C3V            (XMC4_CCU42_BASE+XMC4_CCU4_CC43C3V_OFFSET)
+#define XMC4_CCU42_CC43INTS           (XMC4_CCU42_BASE+XMC4_CCU4_CC43INTS_OFFSET)
+#define XMC4_CCU42_CC43INTE           (XMC4_CCU42_BASE+XMC4_CCU4_CC43INTE_OFFSET)
+#define XMC4_CCU42_CC43SRS            (XMC4_CCU42_BASE+XMC4_CCU4_CC43SRS_OFFSET)
+#define XMC4_CCU42_CC43SWS            (XMC4_CCU42_BASE+XMC4_CCU4_CC43SWS_OFFSET)
+#define XMC4_CCU42_CC43SWR            (XMC4_CCU42_BASE+XMC4_CCU4_CC43SWR_OFFSET)
+#define XMC4_CCU42_CC43ECRD0          (XMC4_CCU42_BASE+XMC4_CCU4_CC43ECRD0_OFFSET)
+#define XMC4_CCU42_CC43ECRD1          (XMC4_CCU42_BASE+XMC4_CCU4_CC43ECRD1_OFFSET)
+
+/* CCU43 Global Registers */

 #define XMC4_CCU43_GCTRL             (XMC4_CCU43_BASE+XMC4_CCU4_GCTRL_OFFSET)
 #define XMC4_CCU43_GSTAT             (XMC4_CCU43_BASE+XMC4_CCU4_GSTAT_OFFSET)
@ -333,34 +618,129 @@
 #define XMC4_CCU43_GCST              (XMC4_CCU43_BASE+XMC4_CCU4_GCST_OFFSET)
 #define XMC4_CCU43_MIDR              (XMC4_CCU43_BASE+XMC4_CCU4_MIDR_OFFSET)

-#define XMC4_CCU4_CC43INS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43INS_OFFSET)
-#define XMC4_CCU4_CC43CMC            (XMC4_CCU43_BASE+XMC4_CCU4_CC43CMC_OFFSET)
-#define XMC4_CCU4_CC43TST            (XMC4_CCU43_BASE+XMC4_CCU4_CC43TST_OFFSET)
-#define XMC4_CCU4_CC43TCSET          (XMC4_CCU43_BASE+XMC4_CCU4_CC43TCSET_OFFSET)
-#define XMC4_CCU4_CC43TCCLR          (XMC4_CCU43_BASE+XMC4_CCU4_CC43TCCLR_OFFSET)
-#define XMC4_CCU4_CC43TC             (XMC4_CCU43_BASE+XMC4_CCU4_CC43TC_OFFSET)
-#define XMC4_CCU4_CC43PSL            (XMC4_CCU43_BASE+XMC4_CCU4_CC43PSL_OFFSET)
-#define XMC4_CCU4_CC43DIT            (XMC4_CCU43_BASE+XMC4_CCU4_CC43DIT_OFFSET)
-#define XMC4_CCU4_CC43DITS           (XMC4_CCU43_BASE+XMC4_CCU4_CC43DITS_OFFSET)
-#define XMC4_CCU4_CC43PSC            (XMC4_CCU43_BASE+XMC4_CCU4_CC43PSC_OFFSET)
-#define XMC4_CCU4_CC43FPC            (XMC4_CCU43_BASE+XMC4_CCU4_CC43FPC_OFFSET)
-#define XMC4_CCU4_CC43FPCS           (XMC4_CCU43_BASE+XMC4_CCU4_CC43FPCS_OFFSET)
-#define XMC4_CCU4_CC43PR             (XMC4_CCU43_BASE+XMC4_CCU4_CC43PR_OFFSET)
-#define XMC4_CCU4_CC43PRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43PRS_OFFSET)
-#define XMC4_CCU4_CC43CR             (XMC4_CCU43_BASE+XMC4_CCU4_CC43CR_OFFSET)
-#define XMC4_CCU4_CC43CRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43CRS_OFFSET)
-#define XMC4_CCU4_CC43TIMER          (XMC4_CCU43_BASE+XMC4_CCU4_CC43TIMER_OFFSET)
-#define XMC4_CCU4_CC43C0V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C0V_OFFSET)
-#define XMC4_CCU4_CC43C1V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C1V_OFFSET)
-#define XMC4_CCU4_CC43C2V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C2V_OFFSET)
-#define XMC4_CCU4_CC43C3V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C3V_OFFSET)
-#define XMC4_CCU4_CC43INTS           (XMC4_CCU43_BASE+XMC4_CCU4_CC43INTS_OFFSET)
-#define XMC4_CCU4_CC43INTE           (XMC4_CCU43_BASE+XMC4_CCU4_CC43INTE_OFFSET)
-#define XMC4_CCU4_CC43SRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43SRS_OFFSET)
-#define XMC4_CCU4_CC43SWS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43SWS_OFFSET)
-#define XMC4_CCU4_CC43SWR            (XMC4_CCU43_BASE+XMC4_CCU4_CC43SWR_OFFSET)
-#define XMC4_CCU4_CC43ECRD0          (XMC4_CCU43_BASE+XMC4_CCU4_CC43ECRD0_OFFSET)
-#define XMC4_CCU4_CC43ECRD1          (XMC4_CCU43_BASE+XMC4_CCU4_CC43ECRD1_OFFSET)
+/* CCU43 CC40 Slice Registers */
+
+#define XMC4_CCU43_CC40INS            (XMC4_CCU43_BASE+XMC4_CCU4_CC40INS_OFFSET)
+#define XMC4_CCU43_CC40CMC            (XMC4_CCU43_BASE+XMC4_CCU4_CC40CMC_OFFSET)
+#define XMC4_CCU43_CC40TST            (XMC4_CCU43_BASE+XMC4_CCU4_CC40TST_OFFSET)
+#define XMC4_CCU43_CC40TCSET          (XMC4_CCU43_BASE+XMC4_CCU4_CC40TCSET_OFFSET)
+#define XMC4_CCU43_CC40TCCLR          (XMC4_CCU43_BASE+XMC4_CCU4_CC40TCCLR_OFFSET)
+#define XMC4_CCU43_CC40TC             (XMC4_CCU43_BASE+XMC4_CCU4_CC40TC_OFFSET)
+#define XMC4_CCU43_CC40PSL            (XMC4_CCU43_BASE+XMC4_CCU4_CC40PSL_OFFSET)
+#define XMC4_CCU43_CC40DIT            (XMC4_CCU43_BASE+XMC4_CCU4_CC40DIT_OFFSET)
+#define XMC4_CCU43_CC40DITS           (XMC4_CCU43_BASE+XMC4_CCU4_CC40DITS_OFFSET)
+#define XMC4_CCU43_CC40PSC            (XMC4_CCU43_BASE+XMC4_CCU4_CC40PSC_OFFSET)
+#define XMC4_CCU43_CC40FPC            (XMC4_CCU43_BASE+XMC4_CCU4_CC40FPC_OFFSET)
+#define XMC4_CCU43_CC40FPCS           (XMC4_CCU43_BASE+XMC4_CCU4_CC40FPCS_OFFSET)
+#define XMC4_CCU43_CC40PR             (XMC4_CCU43_BASE+XMC4_CCU4_CC40PR_OFFSET)
+#define XMC4_CCU43_CC40PRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC40PRS_OFFSET)
+#define XMC4_CCU43_CC40CR             (XMC4_CCU43_BASE+XMC4_CCU4_CC40CR_OFFSET)
+#define XMC4_CCU43_CC40CRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC40CRS_OFFSET)
+#define XMC4_CCU43_CC40TIMER          (XMC4_CCU43_BASE+XMC4_CCU4_CC40TIMER_OFFSET)
+#define XMC4_CCU43_CC40C0V            (XMC4_CCU43_BASE+XMC4_CCU4_CC40C0V_OFFSET)
+#define XMC4_CCU43_CC40C1V            (XMC4_CCU43_BASE+XMC4_CCU4_CC40C1V_OFFSET)
+#define XMC4_CCU43_CC40C2V            (XMC4_CCU43_BASE+XMC4_CCU4_CC40C2V_OFFSET)
+#define XMC4_CCU43_CC40C3V            (XMC4_CCU43_BASE+XMC4_CCU4_CC40C3V_OFFSET)
+#define XMC4_CCU43_CC40INTS           (XMC4_CCU43_BASE+XMC4_CCU4_CC40INTS_OFFSET)
+#define XMC4_CCU43_CC40INTE           (XMC4_CCU43_BASE+XMC4_CCU4_CC40INTE_OFFSET)
+#define XMC4_CCU43_CC40SRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC40SRS_OFFSET)
+#define XMC4_CCU43_CC40SWS            (XMC4_CCU43_BASE+XMC4_CCU4_CC40SWS_OFFSET)
+#define XMC4_CCU43_CC40SWR            (XMC4_CCU43_BASE+XMC4_CCU4_CC40SWR_OFFSET)
+#define XMC4_CCU43_CC40ECRD0          (XMC4_CCU43_BASE+XMC4_CCU4_CC40ECRD0_OFFSET)
+#define XMC4_CCU43_CC40ECRD1          (XMC4_CCU43_BASE+XMC4_CCU4_CC40ECRD1_OFFSET)
+
+/* CCU43 CC41 Slice Registers */
+
+#define XMC4_CCU43_CC41INS            (XMC4_CCU43_BASE+XMC4_CCU4_CC41INS_OFFSET)
+#define XMC4_CCU43_CC41CMC            (XMC4_CCU43_BASE+XMC4_CCU4_CC41CMC_OFFSET)
+#define XMC4_CCU43_CC41TST            (XMC4_CCU43_BASE+XMC4_CCU4_CC41TST_OFFSET)
+#define XMC4_CCU43_CC41TCSET          (XMC4_CCU43_BASE+XMC4_CCU4_CC41TCSET_OFFSET)
+#define XMC4_CCU43_CC41TCCLR          (XMC4_CCU43_BASE+XMC4_CCU4_CC41TCCLR_OFFSET)
+#define XMC4_CCU43_CC41TC             (XMC4_CCU43_BASE+XMC4_CCU4_CC41TC_OFFSET)
+#define XMC4_CCU43_CC41PSL            (XMC4_CCU43_BASE+XMC4_CCU4_CC41PSL_OFFSET)
+#define XMC4_CCU43_CC41DIT            (XMC4_CCU43_BASE+XMC4_CCU4_CC41DIT_OFFSET)
+#define XMC4_CCU43_CC41DITS           (XMC4_CCU43_BASE+XMC4_CCU4_CC41DITS_OFFSET)
+#define XMC4_CCU43_CC41PSC            (XMC4_CCU43_BASE+XMC4_CCU4_CC41PSC_OFFSET)
+#define XMC4_CCU43_CC41FPC            (XMC4_CCU43_BASE+XMC4_CCU4_CC41FPC_OFFSET)
+#define XMC4_CCU43_CC41FPCS           (XMC4_CCU43_BASE+XMC4_CCU4_CC41FPCS_OFFSET)
+#define XMC4_CCU43_CC41PR             (XMC4_CCU43_BASE+XMC4_CCU4_CC41PR_OFFSET)
+#define XMC4_CCU43_CC41PRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC41PRS_OFFSET)
+#define XMC4_CCU43_CC41CR             (XMC4_CCU43_BASE+XMC4_CCU4_CC41CR_OFFSET)
+#define XMC4_CCU43_CC41CRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC41CRS_OFFSET)
+#define XMC4_CCU43_CC41TIMER          (XMC4_CCU43_BASE+XMC4_CCU4_CC41TIMER_OFFSET)
+#define XMC4_CCU43_CC41C0V            (XMC4_CCU43_BASE+XMC4_CCU4_CC41C0V_OFFSET)
+#define XMC4_CCU43_CC41C1V            (XMC4_CCU43_BASE+XMC4_CCU4_CC41C1V_OFFSET)
+#define XMC4_CCU43_CC41C2V            (XMC4_CCU43_BASE+XMC4_CCU4_CC41C2V_OFFSET)
+#define XMC4_CCU43_CC41C3V            (XMC4_CCU43_BASE+XMC4_CCU4_CC41C3V_OFFSET)
+#define XMC4_CCU43_CC41INTS           (XMC4_CCU43_BASE+XMC4_CCU4_CC41INTS_OFFSET)
+#define XMC4_CCU43_CC41INTE           (XMC4_CCU43_BASE+XMC4_CCU4_CC41INTE_OFFSET)
+#define XMC4_CCU43_CC41SRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC41SRS_OFFSET)
+#define XMC4_CCU43_CC41SWS            (XMC4_CCU43_BASE+XMC4_CCU4_CC41SWS_OFFSET)
+#define XMC4_CCU43_CC41SWR            (XMC4_CCU43_BASE+XMC4_CCU4_CC41SWR_OFFSET)
+#define XMC4_CCU43_CC41ECRD0          (XMC4_CCU43_BASE+XMC4_CCU4_CC41ECRD0_OFFSET)
+#define XMC4_CCU43_CC41ECRD1          (XMC4_CCU43_BASE+XMC4_CCU4_CC41ECRD1_OFFSET)
+
+/* CCU43 CC42 Slice Registers */
+
+#define XMC4_CCU43_CC42INS            (XMC4_CCU43_BASE+XMC4_CCU4_CC42INS_OFFSET)
+#define XMC4_CCU43_CC42CMC            (XMC4_CCU43_BASE+XMC4_CCU4_CC42CMC_OFFSET)
+#define XMC4_CCU43_CC42TST            (XMC4_CCU43_BASE+XMC4_CCU4_CC42TST_OFFSET)
+#define XMC4_CCU43_CC42TCSET          (XMC4_CCU43_BASE+XMC4_CCU4_CC42TCSET_OFFSET)
+#define XMC4_CCU43_CC42TCCLR          (XMC4_CCU43_BASE+XMC4_CCU4_CC42TCCLR_OFFSET)
+#define XMC4_CCU43_CC42TC             (XMC4_CCU43_BASE+XMC4_CCU4_CC42TC_OFFSET)
+#define XMC4_CCU43_CC42PSL            (XMC4_CCU43_BASE+XMC4_CCU4_CC42PSL_OFFSET)
+#define XMC4_CCU43_CC42DIT            (XMC4_CCU43_BASE+XMC4_CCU4_CC42DIT_OFFSET)
+#define XMC4_CCU43_CC42DITS           (XMC4_CCU43_BASE+XMC4_CCU4_CC42DITS_OFFSET)
+#define XMC4_CCU43_CC42PSC            (XMC4_CCU43_BASE+XMC4_CCU4_CC42PSC_OFFSET)
+#define XMC4_CCU43_CC42FPC            (XMC4_CCU43_BASE+XMC4_CCU4_CC42FPC_OFFSET)
+#define XMC4_CCU43_CC42FPCS           (XMC4_CCU43_BASE+XMC4_CCU4_CC42FPCS_OFFSET)
+#define XMC4_CCU43_CC42PR             (XMC4_CCU43_BASE+XMC4_CCU4_CC42PR_OFFSET)
+#define XMC4_CCU43_CC42PRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC42PRS_OFFSET)
+#define XMC4_CCU43_CC42CR             (XMC4_CCU43_BASE+XMC4_CCU4_CC42CR_OFFSET)
+#define XMC4_CCU43_CC42CRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC42CRS_OFFSET)
+#define XMC4_CCU43_CC42TIMER          (XMC4_CCU43_BASE+XMC4_CCU4_CC42TIMER_OFFSET)
+#define XMC4_CCU43_CC42C0V            (XMC4_CCU43_BASE+XMC4_CCU4_CC42C0V_OFFSET)
+#define XMC4_CCU43_CC42C1V            (XMC4_CCU43_BASE+XMC4_CCU4_CC42C1V_OFFSET)
+#define XMC4_CCU43_CC42C2V            (XMC4_CCU43_BASE+XMC4_CCU4_CC42C2V_OFFSET)
+#define XMC4_CCU43_CC42C3V            (XMC4_CCU43_BASE+XMC4_CCU4_CC42C3V_OFFSET)
+#define XMC4_CCU43_CC42INTS           (XMC4_CCU43_BASE+XMC4_CCU4_CC42INTS_OFFSET)
+#define XMC4_CCU43_CC42INTE           (XMC4_CCU43_BASE+XMC4_CCU4_CC42INTE_OFFSET)
+#define XMC4_CCU43_CC42SRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC42SRS_OFFSET)
+#define XMC4_CCU43_CC42SWS            (XMC4_CCU43_BASE+XMC4_CCU4_CC42SWS_OFFSET)
+#define XMC4_CCU43_CC42SWR            (XMC4_CCU43_BASE+XMC4_CCU4_CC42SWR_OFFSET)
+#define XMC4_CCU43_CC42ECRD0          (XMC4_CCU43_BASE+XMC4_CCU4_CC42ECRD0_OFFSET)
+#define XMC4_CCU43_CC42ECRD1          (XMC4_CCU43_BASE+XMC4_CCU4_CC42ECRD1_OFFSET)
+
+/* CCU43 CC43 Slice Registers */
+
+#define XMC4_CCU43_CC43INS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43INS_OFFSET)
+#define XMC4_CCU43_CC43CMC            (XMC4_CCU43_BASE+XMC4_CCU4_CC43CMC_OFFSET)
+#define XMC4_CCU43_CC43TST            (XMC4_CCU43_BASE+XMC4_CCU4_CC43TST_OFFSET)
+#define XMC4_CCU43_CC43TCSET          (XMC4_CCU43_BASE+XMC4_CCU4_CC43TCSET_OFFSET)
+#define XMC4_CCU43_CC43TCCLR          (XMC4_CCU43_BASE+XMC4_CCU4_CC43TCCLR_OFFSET)
+#define XMC4_CCU43_CC43TC             (XMC4_CCU43_BASE+XMC4_CCU4_CC43TC_OFFSET)
+#define XMC4_CCU43_CC43PSL            (XMC4_CCU43_BASE+XMC4_CCU4_CC43PSL_OFFSET)
+#define XMC4_CCU43_CC43DIT            (XMC4_CCU43_BASE+XMC4_CCU4_CC43DIT_OFFSET)
+#define XMC4_CCU43_CC43DITS           (XMC4_CCU43_BASE+XMC4_CCU4_CC43DITS_OFFSET)
+#define XMC4_CCU43_CC43PSC            (XMC4_CCU43_BASE+XMC4_CCU4_CC43PSC_OFFSET)
+#define XMC4_CCU43_CC43FPC            (XMC4_CCU43_BASE+XMC4_CCU4_CC43FPC_OFFSET)
+#define XMC4_CCU43_CC43FPCS           (XMC4_CCU43_BASE+XMC4_CCU4_CC43FPCS_OFFSET)
+#define XMC4_CCU43_CC43PR             (XMC4_CCU43_BASE+XMC4_CCU4_CC43PR_OFFSET)
+#define XMC4_CCU43_CC43PRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43PRS_OFFSET)
+#define XMC4_CCU43_CC43CR             (XMC4_CCU43_BASE+XMC4_CCU4_CC43CR_OFFSET)
+#define XMC4_CCU43_CC43CRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43CRS_OFFSET)
+#define XMC4_CCU43_CC43TIMER          (XMC4_CCU43_BASE+XMC4_CCU4_CC43TIMER_OFFSET)
+#define XMC4_CCU43_CC43C0V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C0V_OFFSET)
+#define XMC4_CCU43_CC43C1V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C1V_OFFSET)
+#define XMC4_CCU43_CC43C2V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C2V_OFFSET)
+#define XMC4_CCU43_CC43C3V            (XMC4_CCU43_BASE+XMC4_CCU4_CC43C3V_OFFSET)
+#define XMC4_CCU43_CC43INTS           (XMC4_CCU43_BASE+XMC4_CCU4_CC43INTS_OFFSET)
+#define XMC4_CCU43_CC43INTE           (XMC4_CCU43_BASE+XMC4_CCU4_CC43INTE_OFFSET)
+#define XMC4_CCU43_CC43SRS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43SRS_OFFSET)
+#define XMC4_CCU43_CC43SWS            (XMC4_CCU43_BASE+XMC4_CCU4_CC43SWS_OFFSET)
+#define XMC4_CCU43_CC43SWR            (XMC4_CCU43_BASE+XMC4_CCU4_CC43SWR_OFFSET)
+#define XMC4_CCU43_CC43ECRD0          (XMC4_CCU43_BASE+XMC4_CCU4_CC43ECRD0_OFFSET)
+#define XMC4_CCU43_CC43ECRD1          (XMC4_CCU43_BASE+XMC4_CCU4_CC43ECRD1_OFFSET)

 /* Register Bit-Field Definitions *******************************************/