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arch/armv7-r: Remove the nonexistent SCTLR_IE

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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Xiang Xiao 2022-11-19 04:14:45 +08:00 committed by Alan Carvalho de Assis
parent d088a48da4
commit 4abd626288
2 changed files with 1 additions and 3 deletions
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3
arch/arm/src/armv7-r/arm_head.S
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@ -191,7 +191,6 @@ __start:
* SCTLR_EE Bit 25: 0=Little endian. * SCTLR_EE Bit 25: 0=Little endian.
* SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support * SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support
* SCTLR_TE Bit 30: All exceptions handled in ARM state. * SCTLR_TE Bit 30: All exceptions handled in ARM state.
* SCTLR_IE Bit 31: Instruction endian-ness.
*/ */
/* Clear all configurable bits */ /* Clear all configurable bits */
@ -199,7 +198,7 @@ __start:
bic r0, r0, #(SCTLR_M | SCTLR_A | SCTLR_C | SCTLR_CCP15BEN | SCTLR_B) bic r0, r0, #(SCTLR_M | SCTLR_A | SCTLR_C | SCTLR_CCP15BEN | SCTLR_B)
bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR) bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR)
bic r0, r0, #(SCTLR_BR | SCTLR_DZ | SCTLR_FI | SCTLR_U) bic r0, r0, #(SCTLR_BR | SCTLR_DZ | SCTLR_FI | SCTLR_U)
bic r0, r0, #(SCTLR_VE | SCTLR_EE | SCTLR_NMFI | SCTLR_TE | SCTLR_IE) bic r0, r0, #(SCTLR_VE | SCTLR_EE | SCTLR_NMFI | SCTLR_TE)
/* Set configured bits */ /* Set configured bits */

1
arch/arm/src/armv7-r/sctlr.h
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@ -159,7 +159,6 @@
#define SCTLR_NMFI (1 << 27) /* Bit 27: Non-maskable FIQ (NMFI) support */ #define SCTLR_NMFI (1 << 27) /* Bit 27: Non-maskable FIQ (NMFI) support */
/* Bits 28-29: Reserved */ /* Bits 28-29: Reserved */
#define SCTLR_TE (1 << 30) /* Bit 30: Thumb exception enable */ #define SCTLR_TE (1 << 30) /* Bit 30: Thumb exception enable */
#define SCTLR_IE (1 << 31) /* Bit 31: Instruction endian-ness */
/* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1 /* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1
* Implementation defined * Implementation defined