tiva: Fix nxstyle warnings
arch/arm/src/tiva/tm4c/tm4c129_sysctrl.c:
* Fix nxstyle warnings. No functional changes.
arch/arm/src/tiva/tm4c/tm4c_gpio.c:
* Fix nxstyle warnings. No functional changes.
arch/arm/src/tiva/tm4c/tm4c_gpio.h:
* Fix nxstyle warnings. No functional changes.
This commit is contained in:
Nathan Hartman
Xiang Xiao
parent
d6210fcd84
commit
4ac2c73d82
@ -186,10 +186,17 @@ static uint32_t tiva_vco_frequency(uint32_t pllfreq0, uint32_t pllfreq1)
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/* Extract all of the values from the hardware register values. */
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mfrac = (pllfreq0 & SYSCON_PLLFREQ0_MFRAC_MASK) >> SYSCON_PLLFREQ0_MFRAC_SHIFT;
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mint = (pllfreq0 & SYSCON_PLLFREQ0_MINT_MASK) >> SYSCON_PLLFREQ0_MINT_SHIFT;
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q = ((pllfreq1 & SYSCON_PLLFREQ1_Q_MASK) >> SYSCON_PLLFREQ1_Q_SHIFT) + 1;
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n = ((pllfreq1 & SYSCON_PLLFREQ1_N_MASK) >> SYSCON_PLLFREQ1_N_SHIFT) + 1;
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mfrac = (pllfreq0 & SYSCON_PLLFREQ0_MFRAC_MASK) >>
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SYSCON_PLLFREQ0_MFRAC_SHIFT;
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mint = (pllfreq0 & SYSCON_PLLFREQ0_MINT_MASK) >>
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SYSCON_PLLFREQ0_MINT_SHIFT;
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q = ((pllfreq1 & SYSCON_PLLFREQ1_Q_MASK) >>
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SYSCON_PLLFREQ1_Q_SHIFT) + 1;
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n = ((pllfreq1 & SYSCON_PLLFREQ1_N_MASK) >>
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SYSCON_PLLFREQ1_N_SHIFT) + 1;
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/* Algorithm:
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*
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@ -391,8 +398,8 @@ void tiva_clock_configure(void)
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uint32_t pllfreq0;
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uint32_t pllfreq1;
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/* Set the clocking to run with the default settings provided in the board.h
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* header file
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/* Set the clocking to run with the default settings provided in the
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* board.h header file
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*/
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pllfreq0 = M2PLLFREQ0(BOARD_PLL_MINT, BOARD_PLL_MFRAC);
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@ -687,9 +687,9 @@ static inline void tiva_interrupt(pinconfig_t pinconfig)
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* corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
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* set to detect edges, bits set to High in GPIO IBE configure the
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* corresponding pin to detect both rising and falling edges, regardless
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* of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ...
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* Clearing a bit configures the pin to be controlled by GPIOIEV. All bits
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* are cleared by a reset.
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* of the corresponding bit in the GPIO Interrupt Event (GPIO IEV)
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* register ... Clearing a bit configures the pin to be controlled by
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* GPIOIEV. All bits are cleared by a reset.
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*/
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modifyreg32(base + TIVA_GPIO_IBE_OFFSET, ibeclr, ibeset);
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@ -702,12 +702,12 @@ static inline void tiva_interrupt(pinconfig_t pinconfig)
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modifyreg32(base + TIVA_GPIO_IS_OFFSET, isclr, isset);
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/* "The GPIOIEV register is the interrupt event register. Bits set to
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* High in GPIO IEV configure the corresponding pin to detect rising edges
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* or high levels, depending on the corresponding bit value in the GPIO
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* Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to
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* detect falling edges or low levels, depending on the corresponding bit
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* value in GPIOIS. All bits are cleared by a reset.
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/* "The GPIOIEV register is the interrupt event register. Bits set to High
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* in GPIO IEV configure the corresponding pin to detect rising edges or
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* high levels, depending on the corresponding bit value in the GPIO
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* Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin
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* to detect falling edges or low levels, depending on the corresponding
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* bit value in GPIOIS. All bits are cleared by a reset.
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*/
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modifyreg32(base + TIVA_GPIO_IEV_OFFSET, ievclr, ievset);
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@ -717,13 +717,13 @@ static inline void tiva_interrupt(pinconfig_t pinconfig)
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gpioinfo("reg expected actual: [interrupt type=%d]\n", inttype);
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regval = (getreg32(base+TIVA_GPIO_IS_OFFSET) & pin) ? pin : 0;
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regval = (getreg32(base + TIVA_GPIO_IS_OFFSET) & pin) ? pin : 0;
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gpioinfo("IS 0x%08x 0x%08x\n", isset, regval);
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regval = (getreg32(base+TIVA_GPIO_IBE_OFFSET) & pin) ? pin : 0;
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regval = (getreg32(base + TIVA_GPIO_IBE_OFFSET) & pin) ? pin : 0;
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gpioinfo("IBE 0x%08x 0x%08x\n", ibeset, regval);
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regval = (getreg32(base+TIVA_GPIO_IEV_OFFSET) & pin) ? pin : 0;
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regval = (getreg32(base + TIVA_GPIO_IEV_OFFSET) & pin) ? pin : 0;
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gpioinfo("IEV 0x%08x 0x%08x\n", ievset, regval);
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#endif
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}
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@ -824,9 +824,9 @@ int tiva_configgpio(pinconfig_t pinconfig)
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tiva_gpiofunc(base, pinno, &g_funcbits[0]);
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tiva_portcontrol(base, pinno, pinconfig, &g_funcbits[0]);
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/* Then set up pad strengths and pull-ups. These setups should be done before
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* setting up the function because some function settings will over-ride these
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* user options.
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/* Then set up pad strengths and pull-ups. These setups should be done
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* before setting up the function because some function settings will
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* over-ride these user options.
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*/
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tiva_gpiopadstrength(base, pin, pinconfig);
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@ -880,19 +880,20 @@ void tiva_gpiowrite(pinconfig_t pinconfig, bool value)
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base = tiva_gpiobaseaddress(port);
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/* "The GPIO DATA register is the data register. In software control mode,
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* values written in the GPIO DATA register are transferred onto the GPIO
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* port pins if the respective pins have been configured as outputs through
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* the GPIO Direction (GPIO DIR) register ...
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/* "The GPIO DATA register is the data register. In software control
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* mode, values written in the GPIO DATA register are transferred onto
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* the GPIO port pins if the respective pins have been configured as
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* outputs through the GPIO Direction (GPIO DIR) register ...
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*
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* "In order to write to GPIO DATA, the corresponding bits in the mask,
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* resulting from the address bus bits [9:2], must be High. Otherwise, the
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* bit values remain unchanged by the write.
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* resulting from the address bus bits [9:2], must be High. Otherwise,
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* the bit values remain unchanged by the write.
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*
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* "... All bits are cleared by a reset."
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*/
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putreg32((uint32_t)value << pinno, base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
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putreg32((uint32_t)value << pinno,
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base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
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}
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/****************************************************************************
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@ -918,18 +919,19 @@ bool tiva_gpioread(pinconfig_t pinconfig)
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base = tiva_gpiobaseaddress(port);
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/* "... the values read from this register are determined for each bit
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* by the mask bit derived from the address used to access the data register,
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* bits [9:2]. Bits that are 1 in the address mask cause the corresponding
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* bits in GPIODATA to be read, and bits that are 0 in the address mask cause
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* the corresponding bits in GPIO DATA to be read as 0, regardless of their
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* value.
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/* "... the values read from this register are determined for each bit by
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* the mask bit derived from the address used to access the data
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* register, bits [9:2]. Bits that are 1 in the address mask cause the
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* corresponding bits in GPIODATA to be read, and bits that are 0 in the
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* address mask cause the corresponding bits in GPIO DATA to be read as
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* 0, regardless of their value.
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*
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* "A read from GPIO DATA returns the last bit value written if the respective
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* pins are configured as outputs, or it returns the value on the
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* corresponding input pin when these are configured as inputs. All bits
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* are cleared by a reset."
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* "A read from GPIO DATA returns the last bit value written if the
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* respective pins are configured as outputs, or it returns the value on
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* the corresponding input pin when these are configured as inputs. All
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* bits are cleared by a reset."
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*/
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return (getreg32(base + TIVA_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
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}
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@ -978,5 +980,6 @@ void tiva_gpio_lockport(pinconfig_t pinconfig, bool lock)
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/* Restrict access to the TIVA_GPIO_CR_OFFSET register */
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modifyreg32(base + TIVA_GPIO_LOCK_OFFSET, GPIO_LOCK_UNLOCK, GPIO_LOCK_LOCKED);
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modifyreg32(base + TIVA_GPIO_LOCK_OFFSET, GPIO_LOCK_UNLOCK,
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GPIO_LOCK_LOCKED);
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}
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@ -115,8 +115,8 @@
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*
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* FFFS SPPP III. AAAA .... ...V PPPP PBBB
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*
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* TODO: The TM4C also supports configuration of pins to trigger ADC and/or uDMA.
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* That configuration is not addressed in this this encoding.
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* TODO: The TM4C also supports configuration of pins to trigger ADC and/or
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* uDMA. That configuration is not addressed in this encoding.
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*/
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/* These bits set the primary function of the pin:
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@ -200,7 +200,8 @@
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# define GPIO_ALT_14 (14 << GPIO_ALT_SHIFT)
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# define GPIO_ALT_15 (15 << GPIO_ALT_SHIFT)
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/* If the pin is an GPIO digital output, then this identifies the initial output value:
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/* If the pin is an GPIO digital output, then this identifies the initial
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* output value:
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* .... .... .... .... .... ...V .... ....
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*/
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