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arch/arm/kinetis: Still moving register header files to kinetis/chip directory; still incorporating K64 differences.

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This commit is contained in:
Gregory Nutt 2016-07-01 13:15:29 -06:00
parent 4f64634694
commit 4acd296926
18 changed files with 1334 additions and 488 deletions
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2
arch/arm/src/kinetis/chip.h
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@ -47,7 +47,7 @@
*/
#include <arch/kinetis/chip.h>
#include "kinetis_memorymap.h"
#include "chip/kinetis_memorymap.h"
/************************************************************************************
* Pre-processor Definitions

6
arch/arm/src/kinetis/chip/kinetis_fmc.h
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@ -49,11 +49,11 @@
*/
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
# include "kinetis_k20k40k60fmc.h"
# include "chip/kinetis_k20k40k60fmc.h"
#elif defined(KINETIS_K64)
# include "kinetis_k64fmc.h"
# include "chip/kinetis_k64fmc.h"
#else
# error "No pin multiplexing for this Kinetis part"
# error "No FMC definitions for this Kinetis part"
#endif
/********************************************************************************************

0
arch/arm/src/kinetis/kinetis_mpu.h → arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h
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180
arch/arm/src/kinetis/chip/kinetis_k20memorymap.h Normal file
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/************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef KINETIS_K20
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
/* K20 Family
*
* The memory map for the following parts is defined in Freescale document
* K20P64M72SF1RM
*/
#define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
#if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
#endif
/* 0x18000000 * –0x1bffffff Reserved */
#define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * –0x21ffffff Reserved */
#define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * –0x3fffffff Reserved */
#define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
#define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
#define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * –0x41ffffff Reserved */
#define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * –0xdfffffff Reserved */
#define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
/* 0xe0100000 * –0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
#define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
#define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
#define KINETIS_CRC_BASE 0x40032000 /* CRC */
#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* KINETIS_K20 */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H */

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arch/arm/src/kinetis/chip/kinetis_k40memormap.h Normal file
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/************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef KINETIS_K40
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
/* K40 Family
*
* The memory map for the following parts is defined in Freescale document
* K40P144M100SF2RM
*/
#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
#define KINETIS_FLEXBUS_WBBASE 0x60000000 /* -0x7fffffff FlexBus (External Memory -
* Write-back) */
#define KINETIS_FLEXBUS_WTBASE 0x80000000 /* -0x9fffffff FlexBus (External Memory -
* Write-through) */
#define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* -0xdfffffff FlexBus (External Memory -
* Non-executable) */
#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
#define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
#define KINETIS_MPU_BASE 0x4000d000 /* MPU */
#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
#define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
#define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
#define KINETIS_CRC_BASE 0x40032000 /* CRC */
#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
#define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
#define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */
#define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
#define KINETIS_SLCD_BASE 0x400be000 /* Segment LCD */
#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
#define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
#define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
#define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
#define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
#define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
#define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* KINETIS_K40 */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H */

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/************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef KINETIS_K64
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
/* K60 Family
*
* The memory map for the following parts is defined in Freescale document
* K60P144M100SF2RM
*/
#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
#if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
#endif
#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
#define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
#define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
#define KINETIS_MPU_BASE 0x4000d000 /* MPU */
#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
#define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
#define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
#define KINETIS_CRC_BASE 0x40032000 /* CRC */
#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
#define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
#define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
#define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
#define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
#define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
#define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
#define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
#define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
#define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
#define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
#define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
#define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* KINETIS_K64 */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H */

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/************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
/* K64 Family ***********************************************************************
*
* The memory map for the following parts is defined in NXP document
* K64P144M120SF5RM.pdf
*/
#if defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || \
defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or may not
* be the same as above (the family members are all very similar) This error just
* means that you have to look at the document and determine for yourself if the
* memory map is the same.
*/
# error "No memory map for this K64 part"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H */

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/****************************************************************************************************
* arch/arm/src/kinetis/kinetis_mpu.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */
#define KINETIS_MPU_EAR_OFFSET(n) (0x0010+((n)<<3)) /* Error Address Register, Slave Port n */
#define KINETIS_MPU_EDR_OFFSET(n) (0x0014+((n)<<3)) /* Error Detail Register, Slave Port n */
#define KINETIS_MPU_EAR0_OFFSET 0x0010 /* Error Address Register, Slave Port 0 */
#define KINETIS_MPU_EDR0_OFFSET 0x0014 /* Error Detail Register, Slave Port 0 */
#define KINETIS_MPU_EAR1_OFFSET 0x0018 /* Error Address Register, Slave Port 1 */
#define KINETIS_MPU_EDR1_OFFSET 0x001c /* Error Detail Register, Slave Port 1 */
#define KINETIS_MPU_EAR2_OFFSET 0x0020 /* Error Address Register, Slave Port 2 */
#define KINETIS_MPU_EDR2_OFFSET 0x0024 /* Error Detail Register, Slave Port 2 */
#define KINETIS_MPU_EAR3_OFFSET 0x0028 /* Error Address Register, Slave Port 3 */
#define KINETIS_MPU_EDR3_OFFSET 0x002c /* Error Detail Register, Slave Port 3 */
#define KINETIS_MPU_EAR4_OFFSET 0x0030 /* Error Address Register, Slave Port 4 */
#define KINETIS_MPU_EDR4_OFFSET 0x0034 /* Error Detail Register, Slave Port 4 */
#define KINETIS_MPU_RGD_WORD_OFFSET(n,m) (x0400+((n)<<4)+((m)<< 2) /* Region Descriptor n, Word m */
#define KINETIS_MPU_RGD0_WORD0_OFFSET 0x0400 /* Region Descriptor 0, Word 0 */
#define KINETIS_MPU_RGD0_WORD1_OFFSET 0x0404 /* Region Descriptor 0, Word 1 */
#define KINETIS_MPU_RGD0_WORD2_OFFSET 0x0408 /* Region Descriptor 0, Word 2 */
#define KINETIS_MPU_RGD0_WORD3_OFFSET 0x040c /* Region Descriptor 0, Word 3 */
#define KINETIS_MPU_RGD1_WORD0_OFFSET 0x0410 /* Region Descriptor 1, Word 0 */
#define KINETIS_MPU_RGD1_WORD1_OFFSET 0x0414 /* Region Descriptor 1, Word 1 */
#define KINETIS_MPU_RGD1_WORD2_OFFSET 0x0418 /* Region Descriptor 1, Word 2 */
#define KINETIS_MPU_RGD1_WORD3_OFFSET 0x041c /* Region Descriptor 1, Word 3 */
#define KINETIS_MPU_RGD2_WORD0_OFFSET 0x0420 /* Region Descriptor 2, Word 0 */
#define KINETIS_MPU_RGD2_WORD1_OFFSET 0x0424 /* Region Descriptor 2, Word 1 */
#define KINETIS_MPU_RGD2_WORD2_OFFSET 0x0428 /* Region Descriptor 2, Word 2 */
#define KINETIS_MPU_RGD2_WORD3_OFFSET 0x042c /* Region Descriptor 2, Word 3 */
#define KINETIS_MPU_RGD3_WORD0_OFFSET 0x0430 /* Region Descriptor 3, Word 0 */
#define KINETIS_MPU_RGD3_WORD1_OFFSET 0x0434 /* Region Descriptor 3, Word 1 */
#define KINETIS_MPU_RGD3_WORD2_OFFSET 0x0438 /* Region Descriptor 3, Word 2 */
#define KINETIS_MPU_RGD3_WORD3_OFFSET 0x043c /* Region Descriptor 3, Word 3 */
#define KINETIS_MPU_RGD4_WORD0_OFFSET 0x0440 /* Region Descriptor 4, Word 0 */
#define KINETIS_MPU_RGD4_WORD1_OFFSET 0x0444 /* Region Descriptor 4, Word 1 */
#define KINETIS_MPU_RGD4_WORD2_OFFSET 0x0448 /* Region Descriptor 4, Word 2 */
#define KINETIS_MPU_RGD4_WORD3_OFFSET 0x044c /* Region Descriptor 4, Word 3 */
#define KINETIS_MPU_RGD5_WORD0_OFFSET 0x0450 /* Region Descriptor 5, Word 0 */
#define KINETIS_MPU_RGD5_WORD1_OFFSET 0x0454 /* Region Descriptor 5, Word 1 */
#define KINETIS_MPU_RGD5_WORD2_OFFSET 0x0458 /* Region Descriptor 5, Word 2 */
#define KINETIS_MPU_RGD5_WORD3_OFFSET 0x045c /* Region Descriptor 5, Word 3 */
#define KINETIS_MPU_RGD6_WORD0_OFFSET 0x0460 /* Region Descriptor 6, Word 0 */
#define KINETIS_MPU_RGD6_WORD1_OFFSET 0x0464 /* Region Descriptor 6, Word 1 */
#define KINETIS_MPU_RGD6_WORD2_OFFSET 0x0468 /* Region Descriptor 6, Word 2 */
#define KINETIS_MPU_RGD6_WORD3_OFFSET 0x046c /* Region Descriptor 6, Word 3 */
#define KINETIS_MPU_RGD7_WORD0_OFFSET 0x0470 /* Region Descriptor 7, Word 0 */
#define KINETIS_MPU_RGD7_WORD1_OFFSET 0x0474 /* Region Descriptor 7, Word 1 */
#define KINETIS_MPU_RGD7_WORD2_OFFSET 0x0478 /* Region Descriptor 7, Word 2 */
#define KINETIS_MPU_RGD7_WORD3_OFFSET 0x047c /* Region Descriptor 7, Word 3 */
#define KINETIS_MPU_RGD8_WORD0_OFFSET 0x0480 /* Region Descriptor 8, Word 0 */
#define KINETIS_MPU_RGD8_WORD1_OFFSET 0x0484 /* Region Descriptor 8, Word 1 */
#define KINETIS_MPU_RGD8_WORD2_OFFSET 0x0488 /* Region Descriptor 8, Word 2 */
#define KINETIS_MPU_RGD8_WORD3_OFFSET 0x048c /* Region Descriptor 8, Word 3 */
#define KINETIS_MPU_RGD9_WORD0_OFFSET 0x0490 /* Region Descriptor 9, Word 0 */
#define KINETIS_MPU_RGD9_WORD1_OFFSET 0x0494 /* Region Descriptor 9, Word 1 */
#define KINETIS_MPU_RGD9_WORD2_OFFSET 0x0498 /* Region Descriptor 9, Word 2 */
#define KINETIS_MPU_RGD9_WORD3_OFFSET 0x049c /* Region Descriptor 9, Word 3 */
#define KINETIS_MPU_RGD10_WORD0_OFFSET 0x04a0 /* Region Descriptor 10, Word 0 */
#define KINETIS_MPU_RGD10_WORD1_OFFSET 0x04a4 /* Region Descriptor 10, Word 1 */
#define KINETIS_MPU_RGD10_WORD2_OFFSET 0x04a8 /* Region Descriptor 10, Word 2 */
#define KINETIS_MPU_RGD10_WORD3_OFFSET 0x04ac /* Region Descriptor 10, Word 3 */
#define KINETIS_MPU_RGD11_WORD0_OFFSET 0x04b0 /* Region Descriptor 11, Word 0 */
#define KINETIS_MPU_RGD11_WORD1_OFFSET 0x04b4 /* Region Descriptor 11, Word 1 */
#define KINETIS_MPU_RGD11_WORD2_OFFSET 0x04b8 /* Region Descriptor 11, Word 2 */
#define KINETIS_MPU_RGD11_WORD3_OFFSET 0x04bc /* Region Descriptor 11, Word 3 */
#define KINETIS_MPU_RGDAAC_OFFSET(n) (0x0800+((n)<<2)) /* Region Descriptor Alternate Access Control n */
#define KINETIS_MPU_RGDAAC0_OFFSET 0x0800 /* Region Descriptor Alternate Access Control 0 */
#define KINETIS_MPU_RGDAAC1_OFFSET 0x0804 /* Region Descriptor Alternate Access Control 1 */
#define KINETIS_MPU_RGDAAC2_OFFSET 0x0808 /* Region Descriptor Alternate Access Control 2 */
#define KINETIS_MPU_RGDAAC3_OFFSET 0x080c /* Region Descriptor Alternate Access Control 3 */
#define KINETIS_MPU_RGDAAC4_OFFSET 0x0810 /* Region Descriptor Alternate Access Control 4 */
#define KINETIS_MPU_RGDAAC5_OFFSET 0x0814 /* Region Descriptor Alternate Access Control 5 */
#define KINETIS_MPU_RGDAAC6_OFFSET 0x0818 /* Region Descriptor Alternate Access Control 6 */
#define KINETIS_MPU_RGDAAC7_OFFSET 0x081c /* Region Descriptor Alternate Access Control 7 */
#define KINETIS_MPU_RGDAAC8_OFFSET 0x0820 /* Region Descriptor Alternate Access Control 8 */
#define KINETIS_MPU_RGDAAC9_OFFSET 0x0824 /* Region Descriptor Alternate Access Control 9 */
#define KINETIS_MPU_RGDAAC10_OFFSET 0x0828 /* Region Descriptor Alternate Access Control 10 */
#define KINETIS_MPU_RGDAAC11_OFFSET 0x082c /* Region Descriptor Alternate Access Control 11 */
/* Register Addresses *******************************************************************************/
#define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET)
#define KINETIS_MPU_EAR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EAR_OFFSET(n))
#define KINETIS_MPU_EDR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EDR_OFFSET(n))
#define KINETIS_MPU_EAR0 (KINETIS_MPU_BASE+KINETIS_MPU_EAR0_OFFSET)
#define KINETIS_MPU_EDR0 (KINETIS_MPU_BASE+KINETIS_MPU_EDR0_OFFSET)
#define KINETIS_MPU_EAR1 (KINETIS_MPU_BASE+KINETIS_MPU_EAR1_OFFSET)
#define KINETIS_MPU_EDR1 (KINETIS_MPU_BASE+KINETIS_MPU_EDR1_OFFSET)
#define KINETIS_MPU_EAR2 (KINETIS_MPU_BASE+KINETIS_MPU_EAR2_OFFSET)
#define KINETIS_MPU_EDR2 (KINETIS_MPU_BASE+KINETIS_MPU_EDR2_OFFSET)
#define KINETIS_MPU_EAR3 (KINETIS_MPU_BASE+KINETIS_MPU_EAR3_OFFSET)
#define KINETIS_MPU_EDR3 (KINETIS_MPU_BASE+KINETIS_MPU_EDR3_OFFSET)
#define KINETIS_MPU_EAR4 (KINETIS_MPU_BASE+KINETIS_MPU_EAR4_OFFSET)
#define KINETIS_MPU_EDR4 (KINETIS_MPU_BASE+KINETIS_MPU_EDR4_OFFSET)
#define KINETIS_MPU_RGD_WORD(n,m) (KINETIS_MPU_BASE+KINETIS_MPU_RGD_WORD_OFFSET(n,m))
#define KINETIS_MPU_RGD0_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD0_OFFSET)
#define KINETIS_MPU_RGD0_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD1_OFFSET)
#define KINETIS_MPU_RGD0_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD2_OFFSET)
#define KINETIS_MPU_RGD0_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD3_OFFSET)
#define KINETIS_MPU_RGD1_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD0_OFFSET)
#define KINETIS_MPU_RGD1_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD1_OFFSET)
#define KINETIS_MPU_RGD1_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD2_OFFSET)
#define KINETIS_MPU_RGD1_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD3_OFFSET)
#define KINETIS_MPU_RGD2_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD0_OFFSET)
#define KINETIS_MPU_RGD2_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD1_OFFSET)
#define KINETIS_MPU_RGD2_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD2_OFFSET)
#define KINETIS_MPU_RGD2_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD3_OFFSET)
#define KINETIS_MPU_RGD3_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD0_OFFSET)
#define KINETIS_MPU_RGD3_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD1_OFFSET)
#define KINETIS_MPU_RGD3_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD2_OFFSET)
#define KINETIS_MPU_RGD3_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD3_OFFSET)
#define KINETIS_MPU_RGD4_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD0_OFFSET)
#define KINETIS_MPU_RGD4_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD1_OFFSET)
#define KINETIS_MPU_RGD4_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD2_OFFSET)
#define KINETIS_MPU_RGD4_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD3_OFFSET)
#define KINETIS_MPU_RGD5_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD0_OFFSET)
#define KINETIS_MPU_RGD5_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD1_OFFSET)
#define KINETIS_MPU_RGD5_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD2_OFFSET)
#define KINETIS_MPU_RGD5_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD3_OFFSET)
#define KINETIS_MPU_RGD6_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD0_OFFSET)
#define KINETIS_MPU_RGD6_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD1_OFFSET)
#define KINETIS_MPU_RGD6_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD2_OFFSET)
#define KINETIS_MPU_RGD6_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD3_OFFSET)
#define KINETIS_MPU_RGD7_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD0_OFFSET)
#define KINETIS_MPU_RGD7_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD1_OFFSET)
#define KINETIS_MPU_RGD7_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD2_OFFSET)
#define KINETIS_MPU_RGD7_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD3_OFFSET)
#define KINETIS_MPU_RGD8_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD0_OFFSET)
#define KINETIS_MPU_RGD8_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD1_OFFSET)
#define KINETIS_MPU_RGD8_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD2_OFFSET)
#define KINETIS_MPU_RGD8_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD3_OFFSET)
#define KINETIS_MPU_RGD9_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD0_OFFSET)
#define KINETIS_MPU_RGD9_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD1_OFFSET)
#define KINETIS_MPU_RGD9_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD2_OFFSET)
#define KINETIS_MPU_RGD9_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD3_OFFSET)
#define KINETIS_MPU_RGD10_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD0_OFFSET)
#define KINETIS_MPU_RGD10_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD1_OFFSET)
#define KINETIS_MPU_RGD10_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD2_OFFSET)
#define KINETIS_MPU_RGD10_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD3_OFFSET)
#define KINETIS_MPU_RGD11_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD0_OFFSET)
#define KINETIS_MPU_RGD11_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD1_OFFSET)
#define KINETIS_MPU_RGD11_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD2_OFFSET)
#define KINETIS_MPU_RGD11_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD3_OFFSET)
#define KINETIS_MPU_RGDAAC(n) (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC_OFFSET(n))
#define KINETIS_MPU_RGDAAC0 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC0_OFFSET)
#define KINETIS_MPU_RGDAAC1 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC1_OFFSET)
#define KINETIS_MPU_RGDAAC2 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC2_OFFSET)
#define KINETIS_MPU_RGDAAC3 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC3_OFFSET)
#define KINETIS_MPU_RGDAAC4 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC4_OFFSET)
#define KINETIS_MPU_RGDAAC5 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC5_OFFSET)
#define KINETIS_MPU_RGDAAC6 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC6_OFFSET)
#define KINETIS_MPU_RGDAAC7 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC7_OFFSET)
#define KINETIS_MPU_RGDAAC8 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC8_OFFSET)
#define KINETIS_MPU_RGDAAC9 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC9_OFFSET)
#define KINETIS_MPU_RGDAAC10 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC10_OFFSET)
#define KINETIS_MPU_RGDAAC11 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC11_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Control/Error Status Register */
#define MPU_CESR_VLD (1 << 0) /* Bit 0: Valid (global enable/disable for the MPU) */
/* Bits 1-7: Reserved */
#define MPU_CESR_NRGD_SHIFT (8) /* Bits 8-11: Number of region descriptors */
#define MPU_CESR_NRGD_MASK (15 << MPU_CESR_NRGD_SHIFT)
# define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */
# define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */
# define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */
#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */
#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT)
#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */
#define MPU_CESR_HRL_MASK (15 << MPU_CESR_HRL_SHIFT)
/* Bits 20-26: Reserved */
#define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */
#define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT)
# define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */
# define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */
# define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */
# define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */
# define MPU_CESR_SPERR_SPORT3 (2 << MPU_CESR_SPERR_SHIFT) /* Slave port 3 */
# define MPU_CESR_SPERR_SPORT4 (1 << MPU_CESR_SPERR_SHIFT) /* Slave port 4 */
/* Error Address Register, Slave Port n. 32-bit error address. */
/* Error Detail Register, Slave Port n */
#define MPU_EDR_ERW (1 << 0) /* Bit 0: Error read/write */
#define MPU_EDR_EATTR_SHIFT (1) /* Bits 1-3: Error attributes */
#define MPU_EDR_EATTR_MASK (7 << MPU_EDR_EATTR_SHIFT)
# define MPU_EDR_EATTR_USRINST (0 << MPU_EDR_EATTR_SHIFT) /* User mode, instruction access */
# define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */
# define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */
# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */
#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */
#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT)
/* Bits 8-15: Reserved */
#define MPU_EDR_EACD_SHIFT (26) /* Bits 16-31: Error access control detail */
#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT)
/* Region Descriptor n, Word 0 */
/* Bits 0-4: Reserved */
#define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */
#define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0)
/* Region Descriptor n, Word 1 */
/* Bits 0-4: Reserved */
#define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */
#define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0)
/* Region Descriptor n, Word 2 */
#define MPU_RGD_MSM_RWX 0 /* R/W/X; read, write and execute allowed */
#define MPU_RGD_MSM_RX 1 /* R/X; read and execute allowed, but no write */
#define MPU_RGD_MSM_RW 2 /* R/W; read and write allowed, but no execute */
#define MPU_RGD_MSM_UM 3 /* Same as user mode defined in MUM */
#define MPU_RGD_MUM_R 4 /* Read allowed */
#define MPU_RGD_MUM_W 2 /* Write allowed */
#define MPU_RGD_MUM_X 1 /* Execute allocated */
#define MPU_RGD_WORD2_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */
#define MPU_RGD_WORD2_M0UM_MASK (7 << MPU_RGD_WORD2_M0UM_SHIFT)
#define MPU_RGD_WORD2_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */
#define MPU_RGD_WORD2_M0SM_MASK (3 << MPU_RGD_WORD2_M0SM_SHIFT)
#define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier Enable */
#define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */
#define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT)
#define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */
#define MPU_RGD_WORD2_M1SM_MASK (3 << MPU_RGD_WORD2_M1SM_SHIFT)
#define MPU_RGD_WORD2_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier Enable */
#define MPU_RGD_WORD2_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */
#define MPU_RGD_WORD2_M2UM_MASK (7 << MPU_RGD_WORD2_M2UM_SHIFT)
#define MPU_RGD_WORD2_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */
#define MPU_RGD_WORD2_M2SM_MASK (3 << MPU_RGD_WORD2_M2SM_SHIFT)
#define MPU_RGD_WORD2_M2PE (1 << 17) /* Bit 17: Bus Master 2 Process Identifier Enable */
#define MPU_RGD_WORD2_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */
#define MPU_RGD_WORD2_M3UM_MASK (7 << MPU_RGD_WORD2_M3UM_SHIFT)
#define MPU_RGD_WORD2_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */
#define MPU_RGD_WORD2_M3SM_MASK (3 << MPU_RGD_WORD2_M3SM_SHIFT)
#define MPU_RGD_WORD2_M3PE (1 << 23) /* Bit 23: Bus Master 3 Process Identifier Enable */
#define MPU_RGD_WORD2_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */
#define MPU_RGD_WORD2_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */
#define MPU_RGD_WORD2_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */
#define MPU_RGD_WORD2_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */
#define MPU_RGD_WORD2_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */
#define MPU_RGD_WORD2_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */
#define MPU_RGD_WORD2_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */
#define MPU_RGD_WORD2_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */
/* Region Descriptor n, Word 3 */
#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */
/* Bits 1-31: Reserved */
/* Region Descriptor Alternate Access Control n */
#define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */
#define MPU_RGD_RBDACC_M0UM_MASK (7 << MPU_RGD_RBDACC_M0UM_SHIFT)
#define MPU_RGD_RBDACC_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */
#define MPU_RGD_RBDACC_M0SM_MASK (3 << MPU_RGD_RBDACC_M0SM_SHIFT)
/* Bit 5: Reserved */
#define MPU_RGD_RBDACC_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */
#define MPU_RGD_RBDACC_M1UM_MASK (7 << MPU_RGD_RBDACC_M1UM_SHIFT)
#define MPU_RGD_RBDACC_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */
#define MPU_RGD_RBDACC_M1SM_MASK (3 << MPU_RGD_RBDACC_M1SM_SHIFT)
/* Bit 11: Reserved */
#define MPU_RGD_RBDACC_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */
#define MPU_RGD_RBDACC_M2UM_MASK (7 << MPU_RGD_RBDACC_M2UM_SHIFT)
#define MPU_RGD_RBDACC_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */
#define MPU_RGD_RBDACC_M2SM_MASK (3 << MPU_RGD_RBDACC_M2SM_SHIFT)
/* Bit 17: Reserved */
#define MPU_RGD_RBDACC_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */
#define MPU_RGD_RBDACC_M3UM_MASK (7 << MPU_RGD_RBDACC_M3UM_SHIFT)
#define MPU_RGD_RBDACC_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */
#define MPU_RGD_RBDACC_M3SM_MASK (3 << MPU_RGD_RBDACC_M3SM_SHIFT)
/* Bit 23: Reserved */
#define MPU_RGD_RBDACC_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */
#define MPU_RGD_RBDACC_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */
#define MPU_RGD_RBDACC_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */
#define MPU_RGD_RBDACC_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */
#define MPU_RGD_RBDACC_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */
#define MPU_RGD_RBDACC_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */
#define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */
#define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H */

16
arch/arm/src/kinetis/kinetis_mcm.h → arch/arm/src/kinetis/chip/kinetis_mcm.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_mcm.h
* arch/arm/src/kinetis/chip/kinetis_mcm.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H
/************************************************************************************
* Included Files
@ -57,6 +57,9 @@
#define KINETIS_MCM_ETBCC_OFFSET 0x0014 /* ETB counter control register */
#define KINETIS_MCM_ETBRL_OFFSET 0x0018 /* ETB reload register */
#define KINETIS_MCM_ETBCNT_OFFSET 0x001c /* ETB counter value register */
#ifdef KINETIS_K64
# define KINETIS_MCM_PID_OFFSET 0x0030 /* Process ID register */
#endif
/* Register Addresses ***************************************************************/
@ -67,6 +70,9 @@
#define KINETIS_MCM_ETBCC (KINETIS_MCM_BASE+KINETIS_MCM_ETBCC_OFFSET)
#define KINETIS_MCM_ETBRL (KINETIS_MCM_BASE+KINETIS_MCM_ETBRL_OFFSET)
#define KINETIS_MCM_ETBCNT (KINETIS_MCM_BASE+KINETIS_MCM_ETBCNT_OFFSET)
#ifdef KINETIS_K64
# define KINETIS_MCM_PID (KINETIS_MCM_BASE+KINETIS_MCM_PID_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
@ -148,4 +154,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H */

79
arch/arm/src/kinetis/chip/kinetis_memorymap.h Normal file
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@ -0,0 +1,79 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_memorymap.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
* by the logic in chip.h.
*/
#if defined(KINETIS_K20)
# include "chip/kinetis_k20memorymap.h"
#elif defined(KINETIS_K40)
# include "chip/kinetis_k40memorymap.h"
#elif defined(KINETIS_K60)
# include "chip/kinetis_k60memorymap.h"
#elif defined(KINETIS_K64)
# include "chip/kinetis_k64memorymap.h"
#else
# error "No memory map for this Kinetis part"
#endif
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H */

26
arch/arm/src/kinetis/kinetis_mmcau.h → arch/arm/src/kinetis/chip/kinetis_mmcau.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_mmcau.h
* arch/arm/src/kinetis/chip/kinetis_mmcau.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H
/************************************************************************************
* Included Files
@ -61,9 +61,11 @@
#define KINETIS_CAU_CA3_OFFSET 0x0005 /* General Purpose Register 3 */
#define KINETIS_CAU_CA4_OFFSET 0x0006 /* General Purpose Register 4 */
#define KINETIS_CAU_CA5_OFFSET 0x0007 /* General Purpose Register 5 */
#define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */
#define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */
#define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */
#ifndef KINETIS_K64
# define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */
# define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */
# define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */
#endif
/* Register Addresses ***************************************************************/
@ -77,9 +79,11 @@
#define KINETIS_CAU_CA3 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA3_OFFSET)
#define KINETIS_CAU_CA4 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA4_OFFSET)
#define KINETIS_CAU_CA5 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA5_OFFSET)
#define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET)
#define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET)
#define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET)
#ifndef KINETIS_K64
# define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET)
# define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET)
# define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
@ -135,4 +139,4 @@
************************************************************************************/
#endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H */
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H */

75
arch/arm/src/kinetis/chip/kinetis_mpu.h Normal file
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@ -0,0 +1,75 @@
/********************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_mpu.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
* by the logic in chip.h.
*/
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
# include "chip/kinetis_k20k40k60mpu.h"
#elif defined(KINETIS_K64)
# include "chip/kinetis_k64mpu.h"
#else
# error "No MPU definitions for this Kinetis part"
#endif
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/********************************************************************************************
* Public Types
********************************************************************************************/
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H */

8
arch/arm/src/kinetis/chip/kinetis_pinmux.h
View File

@ -49,11 +49,13 @@
*/
#if defined(KINETIS_K20)
# include "kinetis_k20pinmux.h"
# include "chip/kinetis_k20pinmux.h"
#elif defined(KINETIS_K40)
# include "kinetis_k40pinmux.h"
# include "chip/kinetis_k40pinmux.h"
#elif defined(KINETIS_K60)
# include "kinetis_k60pinmux.h"
# include "chip/kinetis_k60pinmux.h"
#elif defined(KINETIS_K64)
# include "chip/kinetis_k64pinmux.h"
#else
# error "No pin multiplexing for this Kinetis part"
#endif

2
arch/arm/src/kinetis/kinetis_enet.c
View File

@ -67,7 +67,7 @@
#include "kinetis_config.h"
#include "chip/kinetis_pinmux.h"
#include "kinetis_sim.h"
#include "kinetis_mpu.h"
#include "chip/kinetis_mpu.h"
#include "chip/kinetis_enet.h"
#if defined(KINETIS_NENET) && KINETIS_NENET > 0

461
arch/arm/src/kinetis/kinetis_memorymap.h
View File

@ -1,461 +0,0 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_memorymap.h
*
* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
/* K20 Family
*
* The memory map for the following parts is defined in Freescale document
* K20P64M72SF1RM
*/
#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
# endif
/* 0x18000000 * –0x1bffffff Reserved */
# define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * –0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * –0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * –0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * –0xdfffffff Reserved */
# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
/* 0xe0100000 * –0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/* Memory Map ***********************************************************************/
/* K40 Family
*
* The memory map for the following parts is defined in Freescale document
* K40P144M100SF2RM
*/
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* –0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * –0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * –0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * –0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * –0x5fffffff Reserved */
# define KINETIS_FLEXBUS_WBBASE 0x60000000 /* –0x7fffffff FlexBus (External Memory -
* Write-back) */
# define KINETIS_FLEXBUS_WTBASE 0x80000000 /* –0x9fffffff FlexBus (External Memory -
* Write-through) */
# define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* –0xdfffffff FlexBus (External Memory -
* Non-executable) */
# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
/* 0xe0100000 * –0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_SLCD_BASE 0x400be000 /* Segment LCD */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/* Memory Map ***********************************************************************/
/* K60 Family
*
* The memory map for the following parts is defined in Freescale document
* K60P144M100SF2RM
*/
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \
defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* –0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * –0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * –0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * –0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * –0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* –0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
/* 0xe0100000 * –0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or may not
* be the same as above (the family members are all very similar) This error just
* means that you have to look at the document and determine for yourself if the
* memory map is the same.
*/
# error "No memory map for this Kinetis part"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H */

1
arch/arm/src/kinetis/kinetis_pin.c
View File

@ -48,7 +48,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "kinetis_memorymap.h"
#include "kinetis.h"
#include "kinetis_port.h"
#include "chip/kinetis_gpio.h"

1
arch/arm/src/kinetis/kinetis_pingpio.c
View File

@ -48,7 +48,6 @@
#include "up_arch.h"
#include "up_internal.h"
#include "kinetis_memorymap.h"
#include "kinetis.h"
#include "chip/kinetis_gpio.h"

2
arch/arm/src/kinetis/kinetis_uart.h
View File

@ -42,7 +42,7 @@
#include <nuttx/config.h>
#include "kinetis_memorymap.h"
#include "chip/kinetis_memorymap.h"
/************************************************************************************
* Pre-processor Definitions