Merged in raiden00/nuttx_h7 (pull request #835)
Improvements for H7 towards the DMA support arch/arm/include/stm32h7/stm32h7x3xx_irq.h: fix typos and rename DMA1/2 irq names to match those from other STM32 arch/arm/src/stm32h7/chip/stm32_bdma.h: add auxiliary definitions arch/arm/src/stm32h7/chip/stm32_dma.h: cosmetic changes arch/arm/src/stm32h7/chip/stm32_dmamux.h: add auxliary definitions and fix some typos arch/arm/src/stm32h7/chip/stm32_mdma.h: add auxliary definitions and fix some typos arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h: add DMAMAP definitions for MDMA, DMA1, DMA2 and BDMA arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h: fix AHB1 base adresses and add some address blocks arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h: fix some definitions to match other STM32 ports arch/arm/src/stm32h7/stm32_allocateheap.c: use SRAM from D2 domain (SRAM123) for now arch/arm/src/stm32h7/stm32h7x3xx_rcc.c: enable clock for MDMA and BDMA Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
Gregory Nutt
parent
f914ec6e2b
commit
4ae7373427
@ -92,6 +92,7 @@
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/* Peripherals */
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/* Peripherals */
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
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# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
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@ -69,13 +69,13 @@
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_DMA1STR0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream0 global interrupt */
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#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream0 global interrupt */
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#define STM32_IRQ_DMA1STR1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream1 global interrupt */
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#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream1 global interrupt */
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#define STM32_IRQ_DMA1STR2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream2 global interrupt */
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#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream2 global interrupt */
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#define STM32_IRQ_DMA1STR3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream3 global interrupt */
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#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream3 global interrupt */
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#define STM32_IRQ_DMA1STR4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream4 global interrupt */
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#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream4 global interrupt */
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#define STM32_IRQ_DMA1STR5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream5 global interrupt */
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#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream5 global interrupt */
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#define STM32_IRQ_DMA1STR6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream6 global interrupt */
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#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream6 global interrupt */
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#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
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#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
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#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 19) /* 19: FDCAN1 Interrupt 0 */
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#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 19) /* 19: FDCAN1 Interrupt 0 */
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#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 20) /* 20: FDCAN2 Interrupt 0 */
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#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 20) /* 20: FDCAN2 Interrupt 0 */
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@ -108,21 +108,21 @@
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#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 trigger /commutation interrupt */
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#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 trigger /commutation interrupt */
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#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupts */
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#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupts */
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#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 capture / compare interrupts */
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#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 capture / compare interrupts */
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#define STM32_IRQ_DMA1STR7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream7 global interrupt */
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#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream7 global interrupt */
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#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */
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#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */
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#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
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#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
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#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
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#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
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#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
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#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
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#define STM32_IRQ_ UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
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#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
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#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
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#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
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#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
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#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
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#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC underrun error interrupt */
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#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupt */
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#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
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#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
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#define STM32_IRQ_DMA2STR0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream0 interrupt */
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#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream0 interrupt */
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#define STM32_IRQ_DMA2STR1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream1 interrupt */
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#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream1 interrupt */
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#define STM32_IRQ_DMA2STR2 (STM32_IRQ_FIRST + 58) /* 58: FMA2 Stream2 interrupt */
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#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: FMA2 Stream2 interrupt */
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#define STM32_IRQ_DMA2STR3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream3 interrupt */
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#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream3 interrupt */
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#define STM32_IRQ_DMA2STR4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream4 interrupt */
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#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream4 interrupt */
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#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */
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#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */
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#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet wakeup through EXTI line interrupt */
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#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet wakeup through EXTI line interrupt */
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#define STM32_IRQ_FDCANCAL (STM32_IRQ_FIRST + 63) /* 63: CAN2TX interrupts */
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#define STM32_IRQ_FDCANCAL (STM32_IRQ_FIRST + 63) /* 63: CAN2TX interrupts */
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@ -130,9 +130,9 @@
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#define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST + 65) /* 65: Reserved */
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#define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST + 65) /* 65: Reserved */
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#define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST + 66) /* 66: Reserved */
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#define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST + 66) /* 66: Reserved */
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#define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST + 67) /* 67: Reserved */
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#define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST + 67) /* 67: Reserved */
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#define STM32_IRQ_DMA2STR5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream5 interrupt */
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#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream5 interrupt */
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#define STM32_IRQ_DMA2STR6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream6 interrupt */
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#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream6 interrupt */
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#define STM32_IRQ_DMA2STR7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream7 interrupt */
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#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream7 interrupt */
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#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */
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#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */
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#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
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#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
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#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt*/
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#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt*/
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@ -178,17 +178,17 @@
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#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST + 112) /* 112: DFSDM1 filter 2 interrupt */
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#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST + 112) /* 112: DFSDM1 filter 2 interrupt */
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#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST + 113) /* 113: DFSDM1 filter 3 interrupt */
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#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST + 113) /* 113: DFSDM1 filter 3 interrupt */
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#define STM32_IRQ_SAI3 (STM32_IRQ_FIRST + 114) /* 114: SAI3 global interrupt */
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#define STM32_IRQ_SAI3 (STM32_IRQ_FIRST + 114) /* 114: SAI3 global interrupt */
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#define STM32_IRQ_ SWPMI1 (STM32_IRQ_FIRST + 115) /* 115: SWPMI global interrupt/wakeup */
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#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 115) /* 115: SWPMI global interrupt/wakeup */
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#define STM32_IRQ_ TIM15 (STM32_IRQ_FIRST + 116) /* 116: TIM15 global interrupt */
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#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 116) /* 116: TIM15 global interrupt */
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#define STM32_IRQ_ TIM16 (STM32_IRQ_FIRST + 117) /* 117: TIM16 global interrupt */
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#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 117) /* 117: TIM16 global interrupt */
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#define STM32_IRQ_ TIM17 (STM32_IRQ_FIRST + 118) /* 118: TIM17 global interrupt */
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#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 118) /* 118: TIM17 global interrupt */
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#define STM32_IRQ_ MDIOSWKUP (STM32_IRQ_FIRST + 119) /* 119: MDIOS wakeup */
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#define STM32_IRQ_MDIOSWKUP (STM32_IRQ_FIRST + 119) /* 119: MDIOS wakeup */
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#define STM32_IRQ_ MDIOS (STM32_IRQ_FIRST + 120) /* 120: MDIOS global interrupt */
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#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST + 120) /* 120: MDIOS global interrupt */
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#define STM32_IRQ_ JPEG (STM32_IRQ_FIRST + 121) /* 121: JPEG global interrupt */
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#define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 121) /* 121: JPEG global interrupt */
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#define STM32_IRQ_ MDMA (STM32_IRQ_FIRST + 122) /* 122: MDMA */
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#define STM32_IRQ_MDMA (STM32_IRQ_FIRST + 122) /* 122: MDMA */
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#define STM32_IRQ_RESERVED123 (STM32_IRQ_FIRST + 123) /* 123: Reserved */
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#define STM32_IRQ_RESERVED123 (STM32_IRQ_FIRST + 123) /* 123: Reserved */
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#define STM32_IRQ_ SDMMC (STM32_IRQ_FIRST + 124) /* 124: SDMMC global interrupt */
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#define STM32_IRQ_SDMMC (STM32_IRQ_FIRST + 124) /* 124: SDMMC global interrupt */
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#define STM32_IRQ_ HSEM0 (STM32_IRQ_FIRST + 125) /* 125: HSEM global interrupt 1 */
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#define STM32_IRQ_HSEM0 (STM32_IRQ_FIRST + 125) /* 125: HSEM global interrupt 1 */
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#define STM32_IRQ_RESERVED126 (STM32_IRQ_FIRST + 126) /* 126: Reserved */
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#define STM32_IRQ_RESERVED126 (STM32_IRQ_FIRST + 126) /* 126: Reserved */
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#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 127) /* 127: ADC3 global interrupt */
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#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 127) /* 127: ADC3 global interrupt */
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#define STM32_IRQ_DMAMUX2OVR (STM32_IRQ_FIRST + 128) /* 128: DMAMUX2 overrun interrupt */
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#define STM32_IRQ_DMAMUX2OVR (STM32_IRQ_FIRST + 128) /* 128: DMAMUX2 overrun interrupt */
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@ -49,9 +49,16 @@
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/* Register Offsets *****************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_BDMA_OFFSET(x) (0x08+0x14*(x))
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#define STM32_BDMA_ISR_OFFSET 0x0000 /* BDMA interrupt status register */
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#define STM32_BDMA_ISR_OFFSET 0x0000 /* BDMA interrupt status register */
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#define STM32_BDMA_IFCR_OFFSET 0x0004 /* BDMA interrupt flag clear register */
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#define STM32_BDMA_IFCR_OFFSET 0x0004 /* BDMA interrupt flag clear register */
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#define STM32_BDMACH_CCR_OFFSET 0x0008
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#define STM32_BDMACH_CNDTR_OFFSET 0x000C
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#define STM32_BDMACH_CPAR_OFFSET 0x0010
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#define STM32_BDMACH_CM0AR_OFFSET 0x0014
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#define STM32_BDMACH_CM1AR_OFFSET 0x0018
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#define STM32_BDMA_CCRX_OFFSET(x) (0x0008+(x*0x0014)) /* BDMA channel x configuration register */
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#define STM32_BDMA_CCRX_OFFSET(x) (0x0008+(x*0x0014)) /* BDMA channel x configuration register */
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#define STM32_BDMA_CCR0_OFFSET STM32_BDMA_CCRX_OFFSET(0)
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#define STM32_BDMA_CCR0_OFFSET STM32_BDMA_CCRX_OFFSET(0)
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#define STM32_BDMA_CCR1_OFFSET STM32_BDMA_CCRX_OFFSET(1)
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#define STM32_BDMA_CCR1_OFFSET STM32_BDMA_CCRX_OFFSET(1)
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@ -49,12 +49,12 @@
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/* 2 DMA controllers + 1 MDMA + 1 BDMA*/
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/* 2 DMA controllers + 1 MDMA + 1 BDMA*/
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#define DMA1 (0)
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#define MDMA (0)
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#define DMA2 (1)
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#define DMA1 (1)
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#define MDMA (3)
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#define DMA2 (2)
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#define BDMA (4)
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#define BDMA (3)
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/* 8 DMA streams */
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/* 8 DMA streams for standard DMA */
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#define DMA_STREAM0 (0)
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#define DMA_STREAM0 (0)
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#define DMA_STREAM1 (1)
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#define DMA_STREAM1 (1)
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@ -47,6 +47,9 @@
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* Pre-processor Definitions
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* Pre-processor Definitions
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************************************************************************************/
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************************************************************************************/
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#define DMAMUX1 0
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#define DMAMUX2 0
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/* Register Offsets *****************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */
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#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */
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/* DMAMUX12 request line multiplexer channel x configuration register */
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/* DMAMUX12 request line multiplexer channel x configuration register */
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#define DMAMUX_CXCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */
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#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */
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#define DMAMUX_CXCR_DMAREQID_MASK (0x7f << DMAMUX_CXCR_DMAREQID_SHIFT)
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#define DMAMUX_CCR_DMAREQID_MASK (0x7f << DMAMUX_CCR_DMAREQID_SHIFT)
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#define DMAMUX_CXCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
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#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
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#define DMAMUX_CXCR_EGE (9) /* Bit 9: Event generation enable */
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#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */
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#define DMAMUX_CXCR_SE (16) /* Bit 16: Synchronization enable */
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#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */
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#define DMAMUX_CXCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
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#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
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#define DMAMUX_CXCR_SPOL_MASK (3 << DMAMUX_CXCR_SPOL_SHIFT)
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#define DMAMUX_CCR_SPOL_MASK (3 << DMAMUX_CCR_SPOL_SHIFT)
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#define DMAMUX_CXCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */
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#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */
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#define DMAMUX_CXCR_NBREQ_MASK (0x1f << DMAMUX_CXCR_NBREQ_SHIFT)
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#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT)
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#define DMAMUX_CXCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */
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#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */
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#define DMAMUX_CXCR_SYNCID_MASK (7 << DMAMUX_CXCR_SYNCID_SHIFT)
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#define DMAMUX_CCR_SYNCID_MASK (7 << DMAMUX_CCR_SYNCID_SHIFT)
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/* DMAMUX12 request line multiplexer interrupt channel status register */
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/* DMAMUX12 request line multiplexer interrupt channel status register */
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/* DMAMUX12 request generator channel x configuration register */
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/* DMAMUX12 request generator channel x configuration register */
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#define DMAMUX_RGXCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
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#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
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/* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
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/* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
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#define DMAMUX_RGXCR_SIGID_MASK (0x1f << DMAMUX_RGXCR_SIGID_SHIFT)
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#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT)
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#define DMAMUX_RGXCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
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#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
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#define DMAMUX_RGXCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
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#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
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#define DMAMUX_RGXCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
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#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
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#define DMAMUX_RGXCR_GPOL_MASK (7 << DMAMUX_RGXCR_GPOL_SHIFT)
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#define DMAMUX_RGCR_GPOL_MASK (7 << DMAMUX_RGCR_GPOL_SHIFT)
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#define DMAMUX_RGXCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */
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#define DMAMUX_RGCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */
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#define DMAMUX_RGXCR_GNBREQL_MASK (7 << DMAMUX_RGXCR_GNBREQ_SHIFT)
|
#define DMAMUX_RGCR_GNBREQL_MASK (7 << DMAMUX_RGCR_GNBREQ_SHIFT)
|
||||||
|
|
||||||
/* DMAMUX12 request generator interrupt status register */
|
/* DMAMUX12 request generator interrupt status register */
|
||||||
|
|
||||||
@ -185,14 +188,17 @@
|
|||||||
|
|
||||||
#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */
|
#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */
|
||||||
|
|
||||||
/* DMA Stream mapping.
|
/* DMA channel mapping
|
||||||
* TODO:
|
*
|
||||||
|
* XXXXX.DDD.CCCCCCCC
|
||||||
|
* C - DMAMUX request
|
||||||
|
* D - DMA controller
|
||||||
|
* X - free bits
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define STM32_DMA_MAP(d,s,c) ((d) << 7 | (s) << 4 | (c))
|
#define DMAMAP_MAP(d,c) ((d) << 8 | c)
|
||||||
#define STM32_DMA_CONTROLLER(m) (((m) >> 7) & 1)
|
#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07)
|
||||||
#define STM32_DMA_STREAM(m) (((m) >> 4) & 7)
|
#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff)
|
||||||
#define STM32_DMA_CHANNEL(m) ((m) & 15)
|
|
||||||
|
|
||||||
/* Import DMAMUX map */
|
/* Import DMAMUX map */
|
||||||
|
|
||||||
|
|||||||
@ -49,8 +49,24 @@
|
|||||||
|
|
||||||
/* Register Offsets *****************************************************************/
|
/* Register Offsets *****************************************************************/
|
||||||
|
|
||||||
|
#define STM32_MDMA_OFFSET(x) (0x40+0x40*(x))
|
||||||
#define STM32_MDMA_GISR0_OFFSET 0x0000 /* MDMA global interrupt/status register */
|
#define STM32_MDMA_GISR0_OFFSET 0x0000 /* MDMA global interrupt/status register */
|
||||||
/* 0x0004-0x003C: Reserved */
|
/* 0x0004-0x003C: Reserved */
|
||||||
|
|
||||||
|
#define STM32_MDMACH_CISR_OFFSET 0x0040
|
||||||
|
#define STM32_MDMACH_CIFCR_OFFSET 0x0044
|
||||||
|
#define STM32_MDMACH_CESR_OFFSET 0x0048
|
||||||
|
#define STM32_MDMACH_CCR_OFFSET 0x004C
|
||||||
|
#define STM32_MDMACH_CTCR_OFFSET 0x0050
|
||||||
|
#define STM32_MDMACH_CBNDTR_OFFSET 0x0054
|
||||||
|
#define STM32_MDMACH_CSAR_OFFSET 0x0058
|
||||||
|
#define STM32_MDMACH_CDAR_OFFSET 0x005C
|
||||||
|
#define STM32_MDMACH_CBRUR_OFFSET 0x0060
|
||||||
|
#define STM32_MDMACH_CLAR_OFFSET 0x0064
|
||||||
|
#define STM32_MDMACH_CTBR_OFFSET 0x0068
|
||||||
|
#define STM32_MDMACH_CMAR_OFFSET 0x0070
|
||||||
|
#define STM32_MDMACH_CMDR_OFFSET 0x0074
|
||||||
|
|
||||||
#define STM32_MDMA_CXISR_OFFSET(x) (0x0040+0x040*(x)) /* MDMA channel x interrupt/status register*/
|
#define STM32_MDMA_CXISR_OFFSET(x) (0x0040+0x040*(x)) /* MDMA channel x interrupt/status register*/
|
||||||
#define STM32_MDMA_C0ISR_OFFSET STM32_MDMA_CXISR_OFFSET(0)
|
#define STM32_MDMA_C0ISR_OFFSET STM32_MDMA_CXISR_OFFSET(0)
|
||||||
#define STM32_MDMA_C1ISR_OFFSET STM32_MDMA_CXISR_OFFSET(1)
|
#define STM32_MDMA_C1ISR_OFFSET STM32_MDMA_CXISR_OFFSET(1)
|
||||||
@ -231,7 +247,7 @@
|
|||||||
#define STM32_MDMA_C14LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(14)
|
#define STM32_MDMA_C14LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(14)
|
||||||
#define STM32_MDMA_C15LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(15)
|
#define STM32_MDMA_C15LAR_OFFSET STM32_MDMA_CXLAR_OFFSET(15)
|
||||||
|
|
||||||
#define STM32_MDMA_CXTBR_OFFSET(x) (0x0064+0x040*(x)) /* MDMA channel x trigger and bus selection register */
|
#define STM32_MDMA_CXTBR_OFFSET(x) (0x0068+0x040*(x)) /* MDMA channel x trigger and bus selection register */
|
||||||
#define STM32_MDMA_C0TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(0)
|
#define STM32_MDMA_C0TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(0)
|
||||||
#define STM32_MDMA_C1TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(1)
|
#define STM32_MDMA_C1TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(1)
|
||||||
#define STM32_MDMA_C2TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(2)
|
#define STM32_MDMA_C2TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(2)
|
||||||
@ -249,7 +265,7 @@
|
|||||||
#define STM32_MDMA_C14TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(14)
|
#define STM32_MDMA_C14TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(14)
|
||||||
#define STM32_MDMA_C15TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(15)
|
#define STM32_MDMA_C15TBR_OFFSET STM32_MDMA_CXTBR_OFFSET(15)
|
||||||
|
|
||||||
#define STM32_MDMA_CXMAR_OFFSET(x) (0x0068+0x040*(x)) /* MDMA channel x mask address register */
|
#define STM32_MDMA_CXMAR_OFFSET(x) (0x0070+0x040*(x)) /* MDMA channel x mask address register */
|
||||||
#define STM32_MDMA_C0MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(0)
|
#define STM32_MDMA_C0MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(0)
|
||||||
#define STM32_MDMA_C1MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(1)
|
#define STM32_MDMA_C1MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(1)
|
||||||
#define STM32_MDMA_C2MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(2)
|
#define STM32_MDMA_C2MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(2)
|
||||||
@ -267,7 +283,7 @@
|
|||||||
#define STM32_MDMA_C14MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(14)
|
#define STM32_MDMA_C14MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(14)
|
||||||
#define STM32_MDMA_C15MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(15)
|
#define STM32_MDMA_C15MAR_OFFSET STM32_MDMA_CXMAR_OFFSET(15)
|
||||||
|
|
||||||
#define STM32_MDMA_CXMDR_OFFSET(x) (0x0070+0x040*(x)) /* MDMA channel x mask data register */
|
#define STM32_MDMA_CXMDR_OFFSET(x) (0x0074+0x040*(x)) /* MDMA channel x mask data register */
|
||||||
#define STM32_MDMA_C0MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(0)
|
#define STM32_MDMA_C0MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(0)
|
||||||
#define STM32_MDMA_C1MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(1)
|
#define STM32_MDMA_C1MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(1)
|
||||||
#define STM32_MDMA_C2MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(2)
|
#define STM32_MDMA_C2MDR_OFFSET STM32_MDMA_CXMDR_OFFSET(2)
|
||||||
@ -609,10 +625,10 @@
|
|||||||
|
|
||||||
#define MDMA_CBNDTR_BNDT_SHIFT (0) /* Bits 0-16: Block number of data bytes to transfer */
|
#define MDMA_CBNDTR_BNDT_SHIFT (0) /* Bits 0-16: Block number of data bytes to transfer */
|
||||||
#define MDMA_CBNDTR_BNDT_MASK (0x1ffff << MDMA_CBNDTR_BNDT_SHIFT)
|
#define MDMA_CBNDTR_BNDT_MASK (0x1ffff << MDMA_CBNDTR_BNDT_SHIFT)
|
||||||
#define MDMA_CBNDTR_BNDT_BRSUM (18) /* Bit 18: Block repeat source address update mode */
|
#define MDMA_CBNDTR_BRSUM (18) /* Bit 18: Block repeat source address update mode */
|
||||||
#define MDMA_CBNDTR_BNDT_BRDUM (19) /* Bit 19: Block repeat destination address update mode */
|
#define MDMA_CBNDTR_BRDUM (19) /* Bit 19: Block repeat destination address update mode */
|
||||||
#define MDMA_CBNDTR_BNDT_SHIFT (20) /* Bits 20-31: Block repeat count */
|
#define MDMA_CBNDTR_BRC_SHIFT (20) /* Bits 20-31: Block repeat count */
|
||||||
#define MDMA_CBNDTR_BNDT_MASK (0xfff << MDMA_CBNDTR_BNDT_SHIFT)
|
#define MDMA_CBNDTR_BRC_MASK (0xfff << MDMA_CBNDTR_BNDT_SHIFT)
|
||||||
|
|
||||||
/* MDMA channel x block repeat address update register */
|
/* MDMA channel x block repeat address update register */
|
||||||
|
|
||||||
|
|||||||
@ -92,8 +92,8 @@
|
|||||||
#define DMAMUX1_SPI1_TX (38)
|
#define DMAMUX1_SPI1_TX (38)
|
||||||
#define DMAMUX1_SPI2_RX (39)
|
#define DMAMUX1_SPI2_RX (39)
|
||||||
#define DMAMUX1_SPI2_TX (40)
|
#define DMAMUX1_SPI2_TX (40)
|
||||||
#define DMAMUX1_USART1_TX (41)
|
#define DMAMUX1_USART1_RX (41)
|
||||||
#define DMAMUX1_USART1_RX (42)
|
#define DMAMUX1_USART1_TX (42)
|
||||||
#define DMAMUX1_USART2_RX (43)
|
#define DMAMUX1_USART2_RX (43)
|
||||||
#define DMAMUX1_USART2_TX (44)
|
#define DMAMUX1_USART2_TX (44)
|
||||||
#define DMAMUX1_USART3_RX (45)
|
#define DMAMUX1_USART3_RX (45)
|
||||||
@ -118,8 +118,8 @@
|
|||||||
#define DMAMUX1_UART4_TX (64)
|
#define DMAMUX1_UART4_TX (64)
|
||||||
#define DMAMUX1_UART5_RX (65)
|
#define DMAMUX1_UART5_RX (65)
|
||||||
#define DMAMUX1_UART5_TX (66)
|
#define DMAMUX1_UART5_TX (66)
|
||||||
#define DMAMUX1_DAC_CH1 (67)
|
#define DMAMUX1_DAC1_CH1 (67)
|
||||||
#define DMAMUX1_DAC_CH2 (68)
|
#define DMAMUX1_DAC1_CH2 (68)
|
||||||
#define DMAMUX1_TIM6_UP (69)
|
#define DMAMUX1_TIM6_UP (69)
|
||||||
#define DMAMUX1_TIM7_UP (70)
|
#define DMAMUX1_TIM7_UP (70)
|
||||||
#define DMAMUX1_USART6_RX (71)
|
#define DMAMUX1_USART6_RX (71)
|
||||||
@ -192,4 +192,313 @@
|
|||||||
#define DMAMUX2_ADC3 (17)
|
#define DMAMUX2_ADC3 (17)
|
||||||
/* DMAMUX2 18-32: Reserved */
|
/* DMAMUX2 18-32: Reserved */
|
||||||
|
|
||||||
|
/* DMAMAP for MDMA */
|
||||||
|
|
||||||
|
#define MDMA_STR_DMA1S0 0
|
||||||
|
#define MDMA_STR_DMA1S1 1
|
||||||
|
#define MDMA_STR_DMA1S2 2
|
||||||
|
#define MDMA_STR_DMA1S3 3
|
||||||
|
#define MDMA_STR_DMA1S4 4
|
||||||
|
#define MDMA_STR_DMA1S5 5
|
||||||
|
#define MDMA_STR_DMA1S6 6
|
||||||
|
#define MDMA_STR_DMA1S7 7
|
||||||
|
#define MDMA_STR_DMA2S0 8
|
||||||
|
#define MDMA_STR_DMA2S1 9
|
||||||
|
#define MDMA_STR_DMA2S2 10
|
||||||
|
#define MDMA_STR_DMA2S3 11
|
||||||
|
#define MDMA_STR_DMA2S4 12
|
||||||
|
#define MDMA_STR_DMA2S5 13
|
||||||
|
#define MDMA_STR_DMA2S6 14
|
||||||
|
#define MDMA_STR_DMA2S7 15
|
||||||
|
#define MDMA_STR_LTDC 16
|
||||||
|
#define MDMA_STR_JPEG_IFT 17
|
||||||
|
#define MDMA_STR_JPEG_IFNT 18
|
||||||
|
#define MDMA_STR_JPEG_OFT 19
|
||||||
|
#define MDMA_STR_JPEG_OFNE 20
|
||||||
|
#define MDMA_STR_JPEG_OEC 21
|
||||||
|
#define MDMA_STR_QUADSPI_FT 22
|
||||||
|
#define MDMA_STR_QUADSPI_TC 23
|
||||||
|
#define MDMA_STR_DMA2D_CLUT 24
|
||||||
|
#define MDMA_STR_DMA2D_TC 25
|
||||||
|
#define MDMA_STR_DMA2D_TW 26
|
||||||
|
#define MDMA_STR_SDMMC1 29
|
||||||
|
|
||||||
|
/* DMAP for MDMA (no DMAMUX) */
|
||||||
|
|
||||||
|
#define DMAP_MDMA_DMA1S0 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S0)
|
||||||
|
#define DMAP_MDMA_DMA1S1 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S1)
|
||||||
|
#define DMAP_MDMA_DMA1S2 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S2)
|
||||||
|
#define DMAP_MDMA_DMA1S3 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S3)
|
||||||
|
#define DMAP_MDMA_DMA1S4 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S4)
|
||||||
|
#define DMAP_MDMA_DMA1S5 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S5)
|
||||||
|
#define DMAP_MDMA_DMA1S6 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S6)
|
||||||
|
#define DMAP_MDMA_DMA1S7 DMAMAP_MAP(MDMA, MDMA_STR_DMA1S7)
|
||||||
|
#define DMAP_MDMA_DMA2S0 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S0)
|
||||||
|
#define DMAP_MDMA_DMA2S1 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S1)
|
||||||
|
#define DMAP_MDMA_DMA2S2 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S2)
|
||||||
|
#define DMAP_MDMA_DMA2S3 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S3)
|
||||||
|
#define DMAP_MDMA_DMA2S4 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S4)
|
||||||
|
#define DMAP_MDMA_DMA2S5 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S5)
|
||||||
|
#define DMAP_MDMA_DMA2S6 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S6)
|
||||||
|
#define DMAP_MDMA_DMA2S7 DMAMAP_MAP(MDMA, MDMA_STR_DMA2S7)
|
||||||
|
#define DMAP_MDMA_LTDC DMAMAP_MAP(MDMA, MDMA_STR_LTDC)
|
||||||
|
#define DMAP_MDMA_JPEG_IFT DMAMAP_MAP(MDMA, MDMA_STR_JPEG_IFT)
|
||||||
|
#define DMAP_MDMA_JPEG_IFNT DMAMAP_MAP(MDMA, MDMA_STR_JPEG_IFNT)
|
||||||
|
#define DMAP_MDMA_JPEG_OFT DMAMAP_MAP(MDMA, MDMA_STR_JPEG_OFT)
|
||||||
|
#define DMAP_MDMA_JPEG_OFNE DMAMAP_MAP(MDMA, MDMA_STR_JPEG_OFNE)
|
||||||
|
#define DMAP_MDMA_JPEG_OEC DMAMAP_MAP(MDMA, MDMA_STR_JPEG_OEC)
|
||||||
|
#define DMAP_MDMA_QUADSPI_FT DMAMAP_MAP(MDMA, MDMA_STR_QUADSPI_FT)
|
||||||
|
#define DMAP_MDMA_QUADSPI_TC DMAMAP_MAP(MDMA, MDMA_STR_QUADSPI_TC)
|
||||||
|
#define DMAP_MDMA_DMA2D_CLUT DMAMAP_MAP(MDMA, MDMA_STR_QUADSPI_CLUT)
|
||||||
|
#define DMAP_MDMA_DMA2D_TC DMAMAP_MAP(MDMA, MDMA_STR_DMA2d_TC)
|
||||||
|
#define DMAP_MDMA_DMA2D_TW DMAMAP_MAP(MDMA, MDMA_STR_DMA2D_TW)
|
||||||
|
#define DMAP_MDMA_SDMMC1 DMAMAP_MAP(MDMA, MDMA_STR_SDMMC1)
|
||||||
|
|
||||||
|
/* DMAMAP for DMA1 and DMA2 (DMAMUX1) */
|
||||||
|
|
||||||
|
#define DMAMAP_DMA12_REGGEN0_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0)
|
||||||
|
#define DMAMAP_DMA12_REGGEN0_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN0)
|
||||||
|
#define DMAMAP_DMA12_REGGEN1_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1)
|
||||||
|
#define DMAMAP_DMA12_REGGEN1_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN1)
|
||||||
|
#define DMAMAP_DMA12_REGGEN2_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2)
|
||||||
|
#define DMAMAP_DMA12_REGGEN2_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN2)
|
||||||
|
#define DMAMAP_DMA12_REGGEN3_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3)
|
||||||
|
#define DMAMAP_DMA12_REGGEN3_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN3)
|
||||||
|
#define DMAMAP_DMA12_REGGEN4_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN4)
|
||||||
|
#define DMAMAP_DMA12_REGGEN4_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN4)
|
||||||
|
#define DMAMAP_DMA12_REGGEN5_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN5)
|
||||||
|
#define DMAMAP_DMA12_REGGEN5_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN5)
|
||||||
|
#define DMAMAP_DMA12_REGGEN6_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN6)
|
||||||
|
#define DMAMAP_DMA12_REGGEN6_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN6)
|
||||||
|
#define DMAMAP_DMA12_REGGEN7_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN7)
|
||||||
|
#define DMAMAP_DMA12_REGGEN7_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN7)
|
||||||
|
#define DMAMAP_DMA12_ADC1_0 DMAMAP_MAP(DMA1, DMAMUX1_ADC1)
|
||||||
|
#define DMAMAP_DMA12_ADC1_1 DMAMAP_MAP(DMA2, DMAMUX1_ADC1)
|
||||||
|
#define DMAMAP_DMA12_ADC2_0 DMAMAP_MAP(DMA1, DMAMUX1_ADC2)
|
||||||
|
#define DMAMAP_DMA12_ADC2_1 DMAMAP_MAP(DMA2, DMAMUX1_ADC2)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM1CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM1UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1UP)
|
||||||
|
#define DMAMAP_DMA12_TIM1UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1UP)
|
||||||
|
#define DMAMAP_DMA12_TIM1TRIG_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM1TRIG_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM1COM_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1COM)
|
||||||
|
#define DMAMAP_DMA12_TIM1COM_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1COM)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM2CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM2UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2UP)
|
||||||
|
#define DMAMAP_DMA12_TIM2UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2UP)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM3CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM3CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM3CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM3CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM3CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM3UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM3UP)
|
||||||
|
#define DMAMAP_DMA12_TIM3UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3UP)
|
||||||
|
#define DMAMAP_DMA12_TIM3TRIG_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM3TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM3TRIG_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM4CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM4CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM4CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM4CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM4CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM4CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM4CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM4CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM4CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM4CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM4CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM4CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM4UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM4UP)
|
||||||
|
#define DMAMAP_DMA12_TIM4UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM4UP)
|
||||||
|
#define DMAMAP_DMA12_I2C1RX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C1_RX)
|
||||||
|
#define DMAMAP_DMA12_I2C1RX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C1_RX)
|
||||||
|
#define DMAMAP_DMA12_I2C2TX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C2_TX)
|
||||||
|
#define DMAMAP_DMA12_I2C2TX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C2_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI1RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI1_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI1RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI1_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI1TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI1_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI1TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI1_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI2RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI2_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI2RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI2_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI2TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI2_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI2TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI2_TX)
|
||||||
|
#define DMAMAP_DMA12_USART1RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART1_RX)
|
||||||
|
#define DMAMAP_DMA12_USART1RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART1_RX)
|
||||||
|
#define DMAMAP_DMA12_USART1TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART1_TX)
|
||||||
|
#define DMAMAP_DMA12_USART1TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART1_TX)
|
||||||
|
#define DMAMAP_DMA12_USART2RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART2_RX)
|
||||||
|
#define DMAMAP_DMA12_USART2RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART2_RX)
|
||||||
|
#define DMAMAP_DMA12_USART2TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART2_TX)
|
||||||
|
#define DMAMAP_DMA12_USART2TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART2_TX)
|
||||||
|
#define DMAMAP_DMA12_USART3RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART3_RX)
|
||||||
|
#define DMAMAP_DMA12_USART3RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART3_RX)
|
||||||
|
#define DMAMAP_DMA12_USART3TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART3_TX)
|
||||||
|
#define DMAMAP_DMA12_USART3TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART3_TX)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM8CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM8UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8UP)
|
||||||
|
#define DMAMAP_DMA12_TIM8UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8UP)
|
||||||
|
#define DMAMAP_DMA12_TIM8TRIG_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM8TRIG_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM8COM_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM8COM)
|
||||||
|
#define DMAMAP_DMA12_TIM8COM_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM8COM)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM5CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM5CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM5CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM5CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM5CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM5CH3)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM5CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM5CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM5CH4)
|
||||||
|
#define DMAMAP_DMA12_TIM5UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM5UP)
|
||||||
|
#define DMAMAP_DMA12_TIM5UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM5UP)
|
||||||
|
#define DMAMAP_DMA12_TIM5TRIG_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM5TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM5TRIG_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM5TRIG)
|
||||||
|
#define DMAMAP_DMA12_SPI3RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI3_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI3RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI3_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI3TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI3_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI3TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI3_TX)
|
||||||
|
#define DMAMAP_DMA12_UART4RX_0 DMAMAP_MAP(DMA1, DMAMUX1_UART4_RX)
|
||||||
|
#define DMAMAP_DMA12_UART4RX_1 DMAMAP_MAP(DMA2, DMAMUX1_UART4_RX)
|
||||||
|
#define DMAMAP_DMA12_UART4TX_0 DMAMAP_MAP(DMA1, DMAMUX1_UART4_TX)
|
||||||
|
#define DMAMAP_DMA12_UART4TX_1 DMAMAP_MAP(DMA2, DMAMUX1_UART4_TX)
|
||||||
|
#define DMAMAP_DMA12_UART5RX_0 DMAMAP_MAP(DMA1, DMAMUX1_UART5_RX)
|
||||||
|
#define DMAMAP_DMA12_UART5RX_1 DMAMAP_MAP(DMA2, DMAMUX1_UART5_RX)
|
||||||
|
#define DMAMAP_DMA12_UART5TX_0 DMAMAP_MAP(DMA1, DMAMUX1_UART5_TX)
|
||||||
|
#define DMAMAP_DMA12_UART5TX_1 DMAMAP_MAP(DMA2, DMAMUX1_UART5_TX)
|
||||||
|
#define DMAMAP_DMA12_DAC1CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_DAC1_CH1)
|
||||||
|
#define DMAMAP_DMA12_DAC1CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_DAC1_CH1)
|
||||||
|
#define DMAMAP_DMA12_DAC1CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_DAC1_CH2)
|
||||||
|
#define DMAMAP_DMA12_DAC1CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_DAC1_CH2)
|
||||||
|
#define DMAMAP_DMA12_TIM6UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM6_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM6UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM6_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM7UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM7_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM7UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM7_UP)
|
||||||
|
#define DMAMAP_DMA12_USART6RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART6_RX)
|
||||||
|
#define DMAMAP_DMA12_USART6RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART6_RX)
|
||||||
|
#define DMAMAP_DMA12_USART6TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART6_TX)
|
||||||
|
#define DMAMAP_DMA12_USART6TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART6_TX)
|
||||||
|
#define DMAMAP_DMA12_I2C3RX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C3_RX)
|
||||||
|
#define DMAMAP_DMA12_I2C3RX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C3_RX)
|
||||||
|
#define DMAMAP_DMA12_I2C3TX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C3_TX)
|
||||||
|
#define DMAMAP_DMA12_I2C3TX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C3_TX)
|
||||||
|
#define DMAMAP_DMA12_DCMI_0 DMAMAP_MAP(DMA1, DMAMUX1_DCMI)
|
||||||
|
#define DMAMAP_DMA12_DCMI_1 DMAMAP_MAP(DMA2, DMAMUX1_DCMI)
|
||||||
|
#define DMAMAP_DMA12_CRYPTOIN_0 DMAMAP_MAP(DMA1, DMAMUX1_CRYPTO_IN)
|
||||||
|
#define DMAMAP_DMA12_CRYPTOIN_1 DMAMAP_MAP(DMA2, DMAMUX1_CRYPTO_IN)
|
||||||
|
#define DMAMAP_DMA12_CRYPTOOUT_0 DMAMAP_MAP(DMA1, DMAMUX1_CRYPTO_OUT)
|
||||||
|
#define DMAMAP_DMA12_CRYPTOOUT_1 DMAMAP_MAP(DMA2, DMAMUX1_CRYPTO_OUT)
|
||||||
|
#define DMAMAP_DMA12_HASHIN_0 DMAMAP_MAP(DMA1, DMAMUX1_HASH_IN)
|
||||||
|
#define DMAMAP_DMA12_HASHIN_1 DMAMAP_MAP(DMA2, DMAMUX1_HASH_IN)
|
||||||
|
#define DMAMAP_DMA12_USART7RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART7_RX)
|
||||||
|
#define DMAMAP_DMA12_USART7RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART7_RX)
|
||||||
|
#define DMAMAP_DMA12_USART7TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART7_TX)
|
||||||
|
#define DMAMAP_DMA12_USART7TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART7_TX)
|
||||||
|
#define DMAMAP_DMA12_USART8RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART8_RX)
|
||||||
|
#define DMAMAP_DMA12_USART8RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART8_RX)
|
||||||
|
#define DMAMAP_DMA12_USART8TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART8_TX)
|
||||||
|
#define DMAMAP_DMA12_USART8TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART8_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI4RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI4_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI4RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI4_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI4TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI4_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI4TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI4_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI5RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI5_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI5RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI5_RX)
|
||||||
|
#define DMAMAP_DMA12_SPI5TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI5_TX)
|
||||||
|
#define DMAMAP_DMA12_SPI5TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI5_TX)
|
||||||
|
#define DMAMAP_DMA12_SAI1A_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI1A)
|
||||||
|
#define DMAMAP_DMA12_SAI1A_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI1A)
|
||||||
|
#define DMAMAP_DMA12_SAI1B_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI1B)
|
||||||
|
#define DMAMAP_DMA12_SAI1B_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI1B)
|
||||||
|
#define DMAMAP_DMA12_SAI2A_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI2A)
|
||||||
|
#define DMAMAP_DMA12_SAI2A_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI2A)
|
||||||
|
#define DMAMAP_DMA12_SAI2B_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI2B)
|
||||||
|
#define DMAMAP_DMA12_SAI2B_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI2B)
|
||||||
|
#define DMAMAP_DMA12_SWPMIRX_0 DMAMAP_MAP(DMA1, DMAMUX1_SWPMI_RX)
|
||||||
|
#define DMAMAP_DMA12_SWPMIRX_1 DMAMAP_MAP(DMA2, DMAMUX1_SWPMI_RX)
|
||||||
|
#define DMAMAP_DMA12_SWPMITX_0 DMAMAP_MAP(DMA1, DMAMUX1_SWPMI_TX)
|
||||||
|
#define DMAMAP_DMA12_SWPMITX_1 DMAMAP_MAP(DMA2, DMAMUX1_SWPMI_TX)
|
||||||
|
#define DMAMAP_DMA12_SPDIFRFDAT_0 DMAMAP_MAP(DMA1, DMAMUX1_SPDIFRX_DAT)
|
||||||
|
#define DMAMAP_DMA12_SPDIFRFDAT_1 DMAMAP_MAP(DMA2, DMAMUX1_SPDIFRX_DAT)
|
||||||
|
#define DMAMAP_DMA12_SPDIFRFCTRL_0 DMAMAP_MAP(DMA1, DMAMUX1_SPDIFRX_CTRL)
|
||||||
|
#define DMAMAP_DMA12_SPDIFRFCTRL_1 DMAMAP_MAP(DMA2, DMAMUX1_SPDIFRX_CTRL)
|
||||||
|
#define DMAMAP_DMA12_HRREQ1_0 DMAMAP_MAP(DMA1, DMAMUX1_HR_REQ1)
|
||||||
|
#define DMAMAP_DMA12_HRREQ1_1 DMAMAP_MAP(DMA2, DMAMUX1_HR_REQ1)
|
||||||
|
#define DMAMAP_DMA12_HRREQ2_0 DMAMAP_MAP(DMA1, DMAMUX1_HR_REQ2)
|
||||||
|
#define DMAMAP_DMA12_HRREQ2_1 DMAMAP_MAP(DMA2, DMAMUX1_HR_REQ2)
|
||||||
|
#define DMAMAP_DMA12_HRREQ3_0 DMAMAP_MAP(DMA1, DMAMUX1_HR_REQ3)
|
||||||
|
#define DMAMAP_DMA12_HRREQ3_1 DMAMAP_MAP(DMA2, DMAMUX1_HR_REQ3)
|
||||||
|
#define DMAMAP_DMA12_HRREQ4_0 DMAMAP_MAP(DMA1, DMAMUX1_HR_REQ4)
|
||||||
|
#define DMAMAP_DMA12_HRREQ4_1 DMAMAP_MAP(DMA2, DMAMUX1_HR_REQ4)
|
||||||
|
#define DMAMAP_DMA12_HRREQ5_0 DMAMAP_MAP(DMA1, DMAMUX1_HR_REQ5)
|
||||||
|
#define DMAMAP_DMA12_HRREQ5_1 DMAMAP_MAP(DMA2, DMAMUX1_HR_REQ5)
|
||||||
|
#define DMAMAP_DMA12_HRREQ6_0 DMAMAP_MAP(DMA1, DMAMUX1_HR_REQ6)
|
||||||
|
#define DMAMAP_DMA12_HRREQ6_1 DMAMAP_MAP(DMA2, DMAMUX1_HR_REQ6)
|
||||||
|
#define DMAMAP_DMA12_DFSDM10_0 DMAMAP_MAP(DMA1, DMAMUX1_DFSDM1_0)
|
||||||
|
#define DMAMAP_DMA12_DFSDM10_1 DMAMAP_MAP(DMA2, DMAMUX1_DFSDM1_0)
|
||||||
|
#define DMAMAP_DMA12_DFSDM11_0 DMAMAP_MAP(DMA1, DMAMUX1_DFSDM1_1)
|
||||||
|
#define DMAMAP_DMA12_DFSDM11_1 DMAMAP_MAP(DMA2, DMAMUX1_DFSDM1_1)
|
||||||
|
#define DMAMAP_DMA12_DFSDM12_0 DMAMAP_MAP(DMA1, DMAMUX1_DFSDM1_2)
|
||||||
|
#define DMAMAP_DMA12_DFSDM12_1 DMAMAP_MAP(DMA2, DMAMUX1_DFSDM1_2)
|
||||||
|
#define DMAMAP_DMA12_DFSDM13_0 DMAMAP_MAP(DMA1, DMAMUX1_DFSDM1_3)
|
||||||
|
#define DMAMAP_DMA12_DFSDM13_1 DMAMAP_MAP(DMA2, DMAMUX1_DFSDM1_3)
|
||||||
|
#define DMAMAP_DMA12_TIM15CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM15CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM15UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM15UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM15TRIG_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM15TRIG_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_TRIG)
|
||||||
|
#define DMAMAP_DMA12_TIM15COM_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_COM)
|
||||||
|
#define DMAMAP_DMA12_TIM15COM_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_COM)
|
||||||
|
#define DMAMAP_DMA12_TIM16CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM16_CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM16CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM16_CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM16UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM16_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM16UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM16_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM17CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM17_CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM17CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM17_CH1)
|
||||||
|
#define DMAMAP_DMA12_TIM17UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM17_UP)
|
||||||
|
#define DMAMAP_DMA12_TIM17UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM17_UP)
|
||||||
|
#define DMAMAP_DMA12_SAI3A_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI3A)
|
||||||
|
#define DMAMAP_DMA12_SAI3A_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI3A)
|
||||||
|
#define DMAMAP_DMA12_SAI3B_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI3B)
|
||||||
|
#define DMAMAP_DMA12_SAI3B_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI3B)
|
||||||
|
#define DMAMAP_DMA12_ADC3_0 DMAMAP_MAP(DMA1, DMAMUX1_ADC3)
|
||||||
|
#define DMAMAP_DMA12_ADC3_1 DMAMAP_MAP(DMA2, DMAMUX1_ADC3)
|
||||||
|
|
||||||
|
/* DMAMAP for BDMA (DMAMUX2) */
|
||||||
|
|
||||||
|
#define DMAMAP_BDMA_REGGEN0 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN0)
|
||||||
|
#define DMAMAP_BDMA_REGGEN1 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN1)
|
||||||
|
#define DMAMAP_BDMA_REGGEN2 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN2)
|
||||||
|
#define DMAMAP_BDMA_REGGEN3 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN3)
|
||||||
|
#define DMAMAP_BDMA_REGGEN4 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN4)
|
||||||
|
#define DMAMAP_BDMA_REGGEN5 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN5)
|
||||||
|
#define DMAMAP_BDMA_REGGEN6 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN6)
|
||||||
|
#define DMAMAP_BDMA_REGGEN7 DMAMAP_MAP(BDMA, DMAMUX2_REQ_GEN7)
|
||||||
|
#define DMAMAP_BDMA_LPUART1_RX DMAMAP_MAP(BDMA, DMAMUX2_LPUART_RX)
|
||||||
|
#define DMAMAP_BDMA_LPUART1_TX DMAMAP_MAP(BDMA, DMAMUX2_LPUART_TX)
|
||||||
|
#define DMAMAP_BDMA_SPI6_RX DMAMAP_MAP(BDMA, DMAMUX2_SPI6_RX)
|
||||||
|
#define DMAMAP_BDMA_SPI6_TX DMAMAP_MAP(BDMA, DMAMUX2_SPI6_TX)
|
||||||
|
#define DMAMAP_BDMA_I2C4_RX DMAMAP_MAP(BDMA, DMAMUX2_I2C4_RX)
|
||||||
|
#define DMAMAP_BDMA_I2C4_TX DMAMAP_MAP(BDMA, DMAMUX2_I2C4_TX)
|
||||||
|
#define DMAMAP_BDMA_SAI4A DMAMAP_MAP(BDMA, DMAMUX2_SAI4A)
|
||||||
|
#define DMAMAP_BDMA_SAI4B DMAMAP_MAP(BDMA, DMAMUX2_SAI4B)
|
||||||
|
#define DMAMAP_BDMA_ADC3 DMAMAP_MAP(BDMA, DMAMUX2_ADC3)
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H */
|
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H */
|
||||||
|
|||||||
@ -47,12 +47,35 @@
|
|||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
/* STM32H7X3XX Address Blocks *******************************************************/
|
/* STM32H7X3XX Address Blocks *******************************************************/
|
||||||
/* To be provided */
|
|
||||||
|
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb CODE block */
|
||||||
|
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb SRAM block */
|
||||||
|
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */
|
||||||
|
#define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRMA/SRAM */
|
||||||
|
#define STM32_FMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb SDRAM */
|
||||||
|
#define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||||
|
#define STM32_FMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||||
|
#define STM32_FMC_BANK5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC SDRAM Bank 1 */
|
||||||
|
#define STM32_FMC_BANK6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC SDRAM Bank 2 */
|
||||||
|
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */
|
||||||
|
|
||||||
|
#define STM32_REGION_MASK 0xf0000000
|
||||||
|
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||||
|
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1)
|
||||||
|
|
||||||
|
|
||||||
|
/* Code Base Addresses **************************************************************/
|
||||||
|
|
||||||
|
#define STM32_ITCM_BASE 0x00000000 /* 0x00000000-0x0000ffff: ITCM */
|
||||||
|
#define STM32_FLASH_BANK1 0x08000000 /* 0x08000000-0x080fffff: FLASH memory 1 */
|
||||||
|
#define STM32_FLASH_BANK2 0x08100000 /* 0x08100000-0x081fffff: FLASH memory 2 */
|
||||||
|
#define STM32_FLASH_BASE STM32_FLASH_BANK1
|
||||||
|
#define STM32_SYSMEM_MEM 0x1ff00000 /* 0x1ff00000-0x1ff1ffff: System memory */
|
||||||
|
|
||||||
/* SRAM Base Addresses **************************************************************/
|
/* SRAM Base Addresses **************************************************************/
|
||||||
|
|
||||||
#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
|
#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
|
||||||
#define STM32_SRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System SRAM */
|
#define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */
|
||||||
#define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */
|
#define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */
|
||||||
#define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
|
#define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
|
||||||
#define STM32_SRAM3_BASE 0x3004c000 /* 0x30040000-0x30047fff: System SRAM3 */
|
#define STM32_SRAM3_BASE 0x3004c000 /* 0x30040000-0x30047fff: System SRAM3 */
|
||||||
@ -129,13 +152,13 @@
|
|||||||
|
|
||||||
/* AHB1 Base Addresses **************************************************************/
|
/* AHB1 Base Addresses **************************************************************/
|
||||||
|
|
||||||
#define STM32_DMA1_BASE 0x52007000 /* 0x40020000-0x400203ff DMA1 */
|
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff DMA1 */
|
||||||
#define STM32_DMA2_BASE 0x52007000 /* 0x40020400-0x400207ff DMA2 */
|
#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff DMA2 */
|
||||||
#define STM32_DMAMUX1_BASE 0x52007000 /* 0x40020800-0x40020bff DMAMUX1 */
|
#define STM32_DMAMUX1_BASE 0x40020800 /* 0x40020800-0x40020bff DMAMUX1 */
|
||||||
#define STM32_ADC12_BASE 0x52007000 /* 0x40022000-0x400223ff ADC1-ADC2 */
|
#define STM32_ADC12_BASE 0x40022000 /* 0x40022000-0x400223ff ADC1-ADC2 */
|
||||||
#define STM32_EMAC_BASE 0x52007000 /* 0x40028000-0x400293ff Ethernet MAC */
|
#define STM32_EMAC_BASE 0x40028000 /* 0x40028000-0x400293ff Ethernet MAC */
|
||||||
#define STM32_USB1_BASE 0x52007000 /* 0x40040000-0x4007ffff USB1 OTG HS/FS */
|
#define STM32_USB1_BASE 0x40040000 /* 0x40040000-0x4007ffff USB1 OTG HS/FS */
|
||||||
#define STM32_USB2_BASE 0x52007000 /* 0x40080000-0x400bffff USB2 OTG FS */
|
#define STM32_USB2_BASE 0x40080000 /* 0x40080000-0x400bffff USB2 OTG FS */
|
||||||
|
|
||||||
/* AHB2 Base Addresses **************************************************************/
|
/* AHB2 Base Addresses **************************************************************/
|
||||||
|
|
||||||
@ -156,7 +179,7 @@
|
|||||||
#define STM32_GPV_BASE 0x51000000 /* 0x51000000-0x510fffff AXI interconnect */
|
#define STM32_GPV_BASE 0x51000000 /* 0x51000000-0x510fffff AXI interconnect */
|
||||||
#define STM32_MDMA_BASE 0x52000000 /* 0x52000000-0x52000fff MDMA */
|
#define STM32_MDMA_BASE 0x52000000 /* 0x52000000-0x52000fff MDMA */
|
||||||
#define STM32_DMA2D_BASE 0x52001000 /* 0x52001000-0x52001fff Chrom-Art (DMA2D) */
|
#define STM32_DMA2D_BASE 0x52001000 /* 0x52001000-0x52001fff Chrom-Art (DMA2D) */
|
||||||
#define STM32_FLASH_BASE 0x52002000 /* 0x52002000-0x52002fff FLASH interface */
|
#define STM32_FLASHIF_BASE 0x52002000 /* 0x52002000-0x52002fff FLASH interface */
|
||||||
#define STM32_JPEG_BASE 0x52003000 /* 0x52003000-0x52003fff JPEG codec */
|
#define STM32_JPEG_BASE 0x52003000 /* 0x52003000-0x52003fff JPEG codec */
|
||||||
#define STM32_FMC_BASE 0x52004000 /* 0x52004000-0x52004fff FMC control */
|
#define STM32_FMC_BASE 0x52004000 /* 0x52004000-0x52004fff FMC control */
|
||||||
#define STM32_NORC_BASE 0x52004000 /* NOR/PSRAM controller */
|
#define STM32_NORC_BASE 0x52004000 /* NOR/PSRAM controller */
|
||||||
|
|||||||
@ -85,9 +85,9 @@
|
|||||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0098 /* APB2 Peripheral reset register */
|
#define STM32_RCC_APB2RSTR_OFFSET 0x0098 /* APB2 Peripheral reset register */
|
||||||
#define STM32_RCC_APB3RSTR_OFFSET 0x008c /* APB3 Peripheral reset register */
|
#define STM32_RCC_APB3RSTR_OFFSET 0x008c /* APB3 Peripheral reset register */
|
||||||
#define STM32_RCC_APB4RSTR_OFFSET 0x009c /* APB4 Peripheral reset register */
|
#define STM32_RCC_APB4RSTR_OFFSET 0x009c /* APB4 Peripheral reset register */
|
||||||
#define STM32_RCC_GCR_OFFSET 0x00a0 /* */
|
#define STM32_RCC_GCR_OFFSET 0x00a0 /* RCC Global Control register */
|
||||||
#define STM32_RCC_D3AMR_OFFSET 0x00a8 /* */
|
#define STM32_RCC_D3AMR_OFFSET 0x00a8 /* D3 Autonomous mode register */
|
||||||
#define STM32_RCC_RSR_OFFSET 0x00d0 /* */
|
#define STM32_RCC_RSR_OFFSET 0x00d0 /* RCC Reset Status register */
|
||||||
#define STM32_RCC_AHB1ENR_OFFSET 0x00d8 /* AHB1 Peripheral Clock enable register */
|
#define STM32_RCC_AHB1ENR_OFFSET 0x00d8 /* AHB1 Peripheral Clock enable register */
|
||||||
#define STM32_RCC_AHB2ENR_OFFSET 0x00dc /* AHB2 Peripheral Clock enable register */
|
#define STM32_RCC_AHB2ENR_OFFSET 0x00dc /* AHB2 Peripheral Clock enable register */
|
||||||
#define STM32_RCC_AHB3ENR_OFFSET 0x00d4 /* AHB3 Peripheral Clock enable register */
|
#define STM32_RCC_AHB3ENR_OFFSET 0x00d4 /* AHB3 Peripheral Clock enable register */
|
||||||
@ -765,7 +765,7 @@
|
|||||||
/* Bits 24-26: Reserved */
|
/* Bits 24-26: Reserved */
|
||||||
#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */
|
#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */
|
||||||
/* Bit 28: Reserved */
|
/* Bit 28: Reserved */
|
||||||
#define RCC_APB1LRSTR_DAC12RST (1 << 29) /* RCC APB1LRSTR: DAC12RST */
|
#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */
|
||||||
#define RCC_APB1LRSTR_USART7RST (1 << 30) /* RCC APB1LRSTR: USART7RST */
|
#define RCC_APB1LRSTR_USART7RST (1 << 30) /* RCC APB1LRSTR: USART7RST */
|
||||||
#define RCC_APB1LRSTR_USART8RST (1 << 31) /* RCC APB1LRSTR: USART8RST */
|
#define RCC_APB1LRSTR_USART8RST (1 << 31) /* RCC APB1LRSTR: USART8RST */
|
||||||
|
|
||||||
@ -783,92 +783,99 @@
|
|||||||
|
|
||||||
/* APB2 peripheral reset register */
|
/* APB2 peripheral reset register */
|
||||||
|
|
||||||
#define RCC_APB2RSTR_TIM1RST (0x1ul) /* RCC APB2RSTR: TIM1RST */
|
#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */
|
||||||
#define RCC_APB2RSTR_TIM8RST (0x2ul) /* RCC APB2RSTR: TIM8RST */
|
#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */
|
||||||
#define RCC_APB2RSTR_USART1RST (0x10ul) /* RCC APB2RSTR: USART1RST */
|
#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */
|
||||||
#define RCC_APB2RSTR_USART6RST (0x20ul) /* RCC APB2RSTR: USART6RST */
|
#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */
|
||||||
#define RCC_APB2RSTR_SPI1RST (0x1000ul) /* RCC APB2RSTR: SPI1RST */
|
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */
|
||||||
#define RCC_APB2RSTR_SPI4RST (0x2000ul) /* RCC APB2RSTR: SPI4RST */
|
#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */
|
||||||
#define RCC_APB2RSTR_TIM15RST (0x10000ul) /* RCC APB2RSTR: TIM15RST */
|
#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */
|
||||||
#define RCC_APB2RSTR_TIM16RST (0x20000ul) /* RCC APB2RSTR: TIM16RST */
|
#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */
|
||||||
#define RCC_APB2RSTR_TIM17RST (0x40000ul) /* RCC APB2RSTR: TIM17RST */
|
#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */
|
||||||
#define RCC_APB2RSTR_SPI5RST (0x100000ul) /* RCC APB2RSTR: SPI5RST */
|
#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */
|
||||||
#define RCC_APB2RSTR_SAI1RST (0x400000ul) /* RCC APB2RSTR: SAI1RST */
|
#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */
|
||||||
#define RCC_APB2RSTR_SAI2RST (0x800000ul) /* RCC APB2RSTR: SAI2RST */
|
#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */
|
||||||
#define RCC_APB2RSTR_SAI3RST (0x1000000ul) /* RCC APB2RSTR: SAI3RST */
|
#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */
|
||||||
#define RCC_APB2RSTR_DFSDM1RST (0x10000000ul) /* RCC APB2RSTR: DFSDM1RST */
|
#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */
|
||||||
#define RCC_APB2RSTR_HRTIMRST (0x20000000ul) /* RCC APB2RSTR: HRTIMRST */
|
#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */
|
||||||
|
|
||||||
/* APB4 peripheral reset register */
|
/* APB4 peripheral reset register */
|
||||||
|
|
||||||
#define RCC_APB4RSTR_SYSCFGRST (0x2ul) /* RCC APB4RSTR: SYSCFGRST */
|
#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */
|
||||||
#define RCC_APB4RSTR_LPUART1RST (0x8ul) /* RCC APB4RSTR: LPUART1RST */
|
#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */
|
||||||
#define RCC_APB4RSTR_SPI6RST (0x20ul) /* RCC APB4RSTR: SPI6RST */
|
#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */
|
||||||
#define RCC_APB4RSTR_I2C4RST (0x80ul) /* RCC APB4RSTR: I2C4RST */
|
#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */
|
||||||
#define RCC_APB4RSTR_LPTIM2RST (0x200ul) /* RCC APB4RSTR: LPTIM2RST */
|
#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */
|
||||||
#define RCC_APB4RSTR_LPTIM3RST (0x400ul) /* RCC APB4RSTR: LPTIM3RST */
|
#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */
|
||||||
#define RCC_APB4RSTR_LPTIM4RST (0x800ul) /* RCC APB4RSTR: LPTIM4RST */
|
#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */
|
||||||
#define RCC_APB4RSTR_LPTIM5RST (0x1000ul) /* RCC APB4RSTR: LPTIM5RST */
|
#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */
|
||||||
#define RCC_APB4RSTR_COMP12RST (0x4000ul) /* RCC APB4RSTR: COMP12RST */
|
#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */
|
||||||
#define RCC_APB4RSTR_VREFRST (0x8000ul) /* RCC APB4RSTR: VREFRST */
|
#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */
|
||||||
#define RCC_APB4RSTR_SAI4RST (0x200000ul) /* RCC APB4RSTR: SAI4RST */
|
#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */
|
||||||
|
|
||||||
|
/* RCC Global Control resgister */
|
||||||
|
|
||||||
|
#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */
|
||||||
|
|
||||||
|
/* TODO: D3 Autonomous mode register */
|
||||||
|
|
||||||
|
/* TODO: RCC Reset Status register */
|
||||||
|
|
||||||
/* AHB3 Peripheral Clock enable register */
|
/* AHB3 Peripheral Clock enable register */
|
||||||
|
|
||||||
#define RCC_AHB3ENR_MDMAEN (0x1ul) /* RCC AHB3ENR: MDMAEN */
|
#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */
|
||||||
#define RCC_AHB3ENR_DMA2DEN (0x10ul) /* RCC AHB3ENR: DMA2DEN */
|
#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */
|
||||||
#define RCC_AHB3ENR_JPGDECEN (0x20ul) /* RCC AHB3ENR: JPGDECEN */
|
#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */
|
||||||
#define RCC_AHB3ENR_FMCEN (0x1000ul) /* RCC AHB3ENR: FMCEN */
|
#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */
|
||||||
#define RCC_AHB3ENR_QSPIEN (0x4000ul) /* RCC AHB3ENR: QSPIEN */
|
#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */
|
||||||
#define RCC_AHB3ENR_SDMMC1EN (0x10000ul) /* RCC AHB3ENR: SDMMC1EN */
|
#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */
|
||||||
|
|
||||||
/* AHB1 Peripheral Clock enable register */
|
/* AHB1 Peripheral Clock enable register */
|
||||||
|
|
||||||
#define RCC_AHB1ENR_DMA1EN (0x1ul) /* RCC AHB1ENR: DMA1EN */
|
#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */
|
||||||
#define RCC_AHB1ENR_DMA2EN (0x2ul) /* RCC AHB1ENR: DMA2EN */
|
#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */
|
||||||
#define RCC_AHB1ENR_ADC12EN (0x20ul) /* RCC AHB1ENR: ADC12EN */
|
#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */
|
||||||
#define RCC_AHB1ENR_ETH1MACEN (0x8000ul) /* RCC AHB1ENR: ETH1MACEN */
|
#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */
|
||||||
#define RCC_AHB1ENR_ETH1TXEN (0x10000ul) /* RCC AHB1ENR: ETH1TXEN */
|
#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */
|
||||||
#define RCC_AHB1ENR_ETH1RXEN (0x20000ul) /* RCC AHB1ENR: ETH1RXEN */
|
#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */
|
||||||
#define RCC_AHB1ENR_USB1OTGEN (0x2000000ul) /* RCC AHB1ENR: USB1OTGEN */
|
#define RCC_AHB1ENR_USB1OTGEN (1 << 25) /* RCC AHB1ENR: USB1OTGEN */
|
||||||
#define RCC_AHB1ENR_USB1ULPIEN (0x4000000ul) /* RCC AHB1ENR: USB1ULPIEN */
|
#define RCC_AHB1ENR_USB1ULPIEN (1 << 26) /* RCC AHB1ENR: USB1ULPIEN */
|
||||||
#define RCC_AHB1ENR_USB2OTGEN (0x8000000ul) /* RCC AHB1ENR: USB2OTGEN */
|
#define RCC_AHB1ENR_USB2OTGEN (1 << 27) /* RCC AHB1ENR: USB2OTGEN */
|
||||||
#define RCC_AHB1ENR_USB2ULPIEN (0x10000000ul) /* RCC AHB1ENR: USB2ULPIEN */
|
#define RCC_AHB1ENR_USB2ULPIEN (1 << 28) /* RCC AHB1ENR: USB2ULPIEN */
|
||||||
|
|
||||||
/* AHB2 Peripheral Clock enable register */
|
/* AHB2 Peripheral Clock enable register */
|
||||||
|
|
||||||
#define RCC_AHB2ENR_CAMITFEN (0x1ul) /* RCC AHB2ENR: CAMITFEN */
|
#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */
|
||||||
#define RCC_AHB2ENR_CRYPTEN (0x10ul) /* RCC AHB2ENR: CRYPTEN */
|
#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */
|
||||||
#define RCC_AHB2ENR_HASHEN (0x20ul) /* RCC AHB2ENR: HASHEN */
|
#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */
|
||||||
#define RCC_AHB2ENR_RNGEN (0x40ul) /* RCC AHB2ENR: RNGEN */
|
#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */
|
||||||
#define RCC_AHB2ENR_SDMMC2EN (0x200ul) /* RCC AHB2ENR: SDMMC2EN */
|
#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */
|
||||||
#define RCC_AHB2ENR_SRAM1EN (0x20000000ul) /* RCC AHB2ENR: SRAM1EN */
|
#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */
|
||||||
#define RCC_AHB2ENR_SRAM2EN (0x40000000ul) /* RCC AHB2ENR: SRAM2EN */
|
#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */
|
||||||
#define RCC_AHB2ENR_SRAM3EN (0x80000000ul) /* RCC AHB2ENR: SRAM3EN */
|
#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */
|
||||||
|
|
||||||
/* AHB4 Peripheral Clock enable register */
|
/* AHB4 Peripheral Clock enable register */
|
||||||
|
|
||||||
#define RCC_AHB4ENR_GPIOAEN (0x1ul) /* RCC AHB4ENR: GPIOAEN */
|
#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */
|
||||||
#define RCC_AHB4ENR_GPIOBEN (0x2ul) /* RCC AHB4ENR: GPIOBEN */
|
#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */
|
||||||
#define RCC_AHB4ENR_GPIOCEN (0x4ul) /* RCC AHB4ENR: GPIOCEN */
|
#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */
|
||||||
#define RCC_AHB4ENR_GPIODEN (0x8ul) /* RCC AHB4ENR: GPIODEN */
|
#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */
|
||||||
#define RCC_AHB4ENR_GPIOEEN (0x10ul) /* RCC AHB4ENR: GPIOEEN */
|
#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */
|
||||||
#define RCC_AHB4ENR_GPIOFEN (0x20ul) /* RCC AHB4ENR: GPIOFEN */
|
#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */
|
||||||
#define RCC_AHB4ENR_GPIOGEN (0x40ul) /* RCC AHB4ENR: GPIOGEN */
|
#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */
|
||||||
#define RCC_AHB4ENR_GPIOHEN (0x80ul) /* RCC AHB4ENR: GPIOHEN */
|
#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */
|
||||||
#define RCC_AHB4ENR_GPIOIEN (0x100ul) /* RCC AHB4ENR: GPIOIEN */
|
#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */
|
||||||
#define RCC_AHB4ENR_GPIOJEN (0x200ul) /* RCC AHB4ENR: GPIOJEN */
|
#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */
|
||||||
#define RCC_AHB4ENR_GPIOKEN (0x400ul) /* RCC AHB4ENR: GPIOKEN */
|
#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */
|
||||||
#define RCC_AHB4ENR_CRCEN (0x80000ul) /* RCC AHB4ENR: CRCEN */
|
#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */
|
||||||
#define RCC_AHB4ENR_BDMAEN (0x200000ul) /* RCC AHB4ENR: BDMAEN */
|
#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */
|
||||||
#define RCC_AHB4ENR_ADC3EN (0x1000000ul) /* RCC AHB4ENR: ADC3EN */
|
#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */
|
||||||
#define RCC_AHB4ENR_HSEMEN (0x2000000ul) /* RCC AHB4ENR: HSEMEN */
|
#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */
|
||||||
#define RCC_AHB4ENR_BKPRAMEN (0x10000000ul) /* RCC AHB4ENR: BKPRAMEN */
|
#define RCC_AHB4ENR_BKPRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */
|
||||||
|
|
||||||
/* APB3 Peripheral Clock enable register */
|
/* APB3 Peripheral Clock enable register */
|
||||||
|
|
||||||
#define RCC_APB3ENR_LTDCEN (0x8ul) /* RCC APB3ENR: LTDCEN */
|
#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */
|
||||||
#define RCC_APB3ENR_WWDG1EN (0x40ul) /* RCC APB3ENR: WWDG1EN */
|
#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */
|
||||||
|
|
||||||
/* APB1 L Peripheral Clock enable register */
|
/* APB1 L Peripheral Clock enable register */
|
||||||
|
|
||||||
@ -896,7 +903,7 @@
|
|||||||
/* Bits 24-25: Reserved */
|
/* Bits 24-25: Reserved */
|
||||||
#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */
|
#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */
|
||||||
/* Bit 28: Reserved */
|
/* Bit 28: Reserved */
|
||||||
#define RCC_APB1LENR_DAC12EN (1 << 29) /* RCC APB1LENR: DAC12EN */
|
#define RCC_APB1LENR_DAC1EN (1 << 29) /* RCC APB1LENR: DAC1EN */
|
||||||
#define RCC_APB1LENR_USART7EN (1 << 30) /* RCC APB1LENR: USART7EN */
|
#define RCC_APB1LENR_USART7EN (1 << 30) /* RCC APB1LENR: USART7EN */
|
||||||
#define RCC_APB1LENR_USART8EN (1 << 31) /* RCC APB1LENR: USART8EN */
|
#define RCC_APB1LENR_USART8EN (1 << 31) /* RCC APB1LENR: USART8EN */
|
||||||
|
|
||||||
@ -1045,7 +1052,7 @@
|
|||||||
#define RCC_APB1LLPENR_I2C2LPEN (0x400000ul) /* RCC APB1LLPENR: I2C2LPEN */
|
#define RCC_APB1LLPENR_I2C2LPEN (0x400000ul) /* RCC APB1LLPENR: I2C2LPEN */
|
||||||
#define RCC_APB1LLPENR_I2C3LPEN (0x800000ul) /* RCC APB1LLPENR: I2C3LPEN */
|
#define RCC_APB1LLPENR_I2C3LPEN (0x800000ul) /* RCC APB1LLPENR: I2C3LPEN */
|
||||||
#define RCC_APB1LLPENR_HDMICECLPEN (0x8000000ul) /* RCC APB1LLPENR: HDMICECLPEN */
|
#define RCC_APB1LLPENR_HDMICECLPEN (0x8000000ul) /* RCC APB1LLPENR: HDMICECLPEN */
|
||||||
#define RCC_APB1LLPENR_DAC12LPEN (0x20000000ul) /* RCC APB1LLPENR: DAC12LPEN */
|
#define RCC_APB1LLPENR_DAC1LPEN (0x20000000ul) /* RCC APB1LLPENR: DAC1LPEN */
|
||||||
#define RCC_APB1LLPENR_USART7LPEN (0x40000000ul) /* RCC APB1LLPENR: USART7LPEN */
|
#define RCC_APB1LLPENR_USART7LPEN (0x40000000ul) /* RCC APB1LLPENR: USART7LPEN */
|
||||||
#define RCC_APB1LLPENR_USART8LPEN (0x80000000ul) /* RCC APB1LLPENR: USART8LPEN */
|
#define RCC_APB1LLPENR_USART8LPEN (0x80000000ul) /* RCC APB1LLPENR: USART8LPEN */
|
||||||
|
|
||||||
|
|||||||
@ -92,9 +92,6 @@
|
|||||||
|
|
||||||
/* Set the start and end of the SRAMs */
|
/* Set the start and end of the SRAMs */
|
||||||
|
|
||||||
#define SRAM_START STM32_SRAM_BASE
|
|
||||||
#define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE)
|
|
||||||
|
|
||||||
#define SRAM123_START STM32_SRAM123_BASE
|
#define SRAM123_START STM32_SRAM123_BASE
|
||||||
#define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE)
|
#define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE)
|
||||||
|
|
||||||
@ -203,21 +200,21 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
|
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
|
||||||
size_t usize = SRAM_END - ubase;
|
size_t usize = SRAM123_END - ubase;
|
||||||
int log2;
|
int log2;
|
||||||
|
|
||||||
DEBUGASSERT(ubase < (uintptr_t)SRAM_END);
|
DEBUGASSERT(ubase < (uintptr_t)SRAM_END);
|
||||||
|
|
||||||
/* Adjust that size to account for MPU alignment requirements.
|
/* Adjust that size to account for MPU alignment requirements.
|
||||||
* NOTE that there is an implicit assumption that the SRAM_END
|
* NOTE that there is an implicit assumption that the SRAM123_END
|
||||||
* is aligned to the MPU requirement.
|
* is aligned to the MPU requirement.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
log2 = (int)mpu_log2regionfloor(usize);
|
log2 = (int)mpu_log2regionfloor(usize);
|
||||||
DEBUGASSERT((SRAM_END & ((1 << log2) - 1)) == 0);
|
DEBUGASSERT((SRAM123_END & ((1 << log2) - 1)) == 0);
|
||||||
|
|
||||||
usize = (1 << log2);
|
usize = (1 << log2);
|
||||||
ubase = SRAM_END - usize;
|
ubase = SRAM123_END - usize;
|
||||||
|
|
||||||
/* Return the user-space heap settings */
|
/* Return the user-space heap settings */
|
||||||
|
|
||||||
@ -238,7 +235,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
|
|||||||
|
|
||||||
board_autoled_on(LED_HEAPALLOCATE);
|
board_autoled_on(LED_HEAPALLOCATE);
|
||||||
*heap_start = (FAR void *)g_idle_topstack;
|
*heap_start = (FAR void *)g_idle_topstack;
|
||||||
*heap_size = SRAM_END - g_idle_topstack;
|
*heap_size = SRAM123_END - g_idle_topstack;
|
||||||
|
|
||||||
/* Colorize the heap for debug */
|
/* Colorize the heap for debug */
|
||||||
|
|
||||||
@ -265,21 +262,21 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
|
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
|
||||||
size_t usize = SRAM_END - ubase;
|
size_t usize = SRAM123_END - ubase;
|
||||||
int log2;
|
int log2;
|
||||||
|
|
||||||
DEBUGASSERT(ubase < (uintptr_t)SRAM_END);
|
DEBUGASSERT(ubase < (uintptr_t)SRAM123_END);
|
||||||
|
|
||||||
/* Adjust that size to account for MPU alignment requirements.
|
/* Adjust that size to account for MPU alignment requirements.
|
||||||
* NOTE that there is an implicit assumption that the SRAM_END
|
* NOTE that there is an implicit assumption that the SRAM123_END
|
||||||
* is aligned to the MPU requirement.
|
* is aligned to the MPU requirement.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
log2 = (int)mpu_log2regionfloor(usize);
|
log2 = (int)mpu_log2regionfloor(usize);
|
||||||
DEBUGASSERT((SRAM_END & ((1 << log2) - 1)) == 0);
|
DEBUGASSERT((SRAM123_END & ((1 << log2) - 1)) == 0);
|
||||||
|
|
||||||
usize = (1 << log2);
|
usize = (1 << log2);
|
||||||
ubase = SRAM_END - usize;
|
ubase = SRAM123_END - usize;
|
||||||
|
|
||||||
/* Return the kernel heap settings (i.e., the part of the heap region
|
/* Return the kernel heap settings (i.e., the part of the heap region
|
||||||
* that was not dedicated to the user heap).
|
* that was not dedicated to the user heap).
|
||||||
|
|||||||
@ -196,6 +196,12 @@ static inline void rcc_enableahb3(void)
|
|||||||
|
|
||||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32H7_MDMA
|
||||||
|
/* MDMA clock enable */
|
||||||
|
|
||||||
|
regval |= RCC_AHB3ENR_MDMAEN;
|
||||||
|
#endif
|
||||||
|
|
||||||
// TODO: ...
|
// TODO: ...
|
||||||
|
|
||||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||||
@ -256,6 +262,12 @@ static inline void rcc_enableahb4(void)
|
|||||||
);
|
);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32H7_BDMA
|
||||||
|
/* BDMA clock enable */
|
||||||
|
|
||||||
|
regval |= RCC_AHB4ENR_BDMAEN;
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_STM32H7_CRC
|
#ifdef CONFIG_STM32H7_CRC
|
||||||
/* CRC clock enable */
|
/* CRC clock enable */
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user