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arch/arm/samv7: correct number on interrupts

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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This commit is contained in:
Petro Karashchenko 2022-01-03 14:53:34 +02:00 committed by Xiang Xiao
parent 6c2b40f98a
commit 4b190fbce1
2 changed files with 22 additions and 2 deletions
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12
arch/arm/include/samv7/same70_irq.h
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@ -104,8 +104,13 @@
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */ #define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
#define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */ #define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */
#define SAM_PID_FPIXC (68) /* ARM Cache ECC Warning */ #define SAM_PID_FPIXC (68) /* ARM Cache ECC Warning */
#define SAM_PID_I2SC0 (69) /* Inter-IC Sound Controller 0 */
#define SAM_PID_I2SC1 (70) /* Inter-IC Sound Controller 1 */
#define SAM_PID_EMACQ3 (71) /* EMAC Queue 3 Interrupt */
#define SAM_PID_EMACQ4 (72) /* EMAC Queue 4 Interrupt */
#define SAM_PID_EMACQ5 (73) /* EMAC Queue 5 Interrupt */
#define NR_PIDS (69) /* Number of peripheral identifiers */ #define NR_PIDS (74) /* Number of peripheral identifiers */
/* External interrupts (priority levels >= 256 */ /* External interrupts (priority levels >= 256 */
@ -180,6 +185,11 @@
#define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */ #define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */
#define SAM_IRQ_EMACQ2 (SAM_IRQ_EXTINT+SAM_PID_EMACQ2) /* EMAC Queue 2 Interrupt */ #define SAM_IRQ_EMACQ2 (SAM_IRQ_EXTINT+SAM_PID_EMACQ2) /* EMAC Queue 2 Interrupt */
#define SAM_IRQ_FPIXC (SAM_IRQ_EXTINT+SAM_PID_FPIXC) /* ARM Cache ECC Warning */ #define SAM_IRQ_FPIXC (SAM_IRQ_EXTINT+SAM_PID_FPIXC) /* ARM Cache ECC Warning */
#define SAM_IRQ_I2SC0 (SAM_IRQ_EXTINT+SAM_PID_I2SC0) /* Inter-IC Sound Controller 0 */
#define SAM_IRQ_I2SC1 (SAM_IRQ_EXTINT+SAM_PID_I2SC1) /* Inter-IC Sound Controller 1 */
#define SAM_IRQ_EMACQ3 (SAM_IRQ_EXTINT+SAM_PID_EMACQ3) /* EMAC Queue 3 Interrupt */
#define SAM_IRQ_EMACQ4 (SAM_IRQ_EXTINT+SAM_PID_EMACQ4) /* EMAC Queue 4 Interrupt */
#define SAM_IRQ_EMACQ5 (SAM_IRQ_EXTINT+SAM_PID_EMACQ5) /* EMAC Queue 5 Interrupt */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ #define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */ #define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */

12
arch/arm/include/samv7/samv71_irq.h
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@ -104,8 +104,13 @@
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */ #define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
#define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */ #define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */
#define SAM_PID_FPIXC (68) /* ARM Cache ECC Warning */ #define SAM_PID_FPIXC (68) /* ARM Cache ECC Warning */
#define SAM_PID_I2SC0 (69) /* Inter-IC Sound Controller 0 */
#define SAM_PID_I2SC1 (70) /* Inter-IC Sound Controller 1 */
#define SAM_PID_EMACQ3 (71) /* EMAC Queue 3 Interrupt */
#define SAM_PID_EMACQ4 (72) /* EMAC Queue 4 Interrupt */
#define SAM_PID_EMACQ5 (73) /* EMAC Queue 5 Interrupt */
#define NR_PIDS (69) /* Number of peripheral identifiers */ #define NR_PIDS (74) /* Number of peripheral identifiers */
/* External interrupts (priority levels >= 256 */ /* External interrupts (priority levels >= 256 */
@ -180,6 +185,11 @@
#define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */ #define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */
#define SAM_IRQ_EMACQ2 (SAM_IRQ_EXTINT+SAM_PID_EMACQ2) /* EMAC Queue 2 Interrupt */ #define SAM_IRQ_EMACQ2 (SAM_IRQ_EXTINT+SAM_PID_EMACQ2) /* EMAC Queue 2 Interrupt */
#define SAM_IRQ_FPIXC (SAM_IRQ_EXTINT+SAM_PID_FPIXC) /* ARM Cache ECC Warning */ #define SAM_IRQ_FPIXC (SAM_IRQ_EXTINT+SAM_PID_FPIXC) /* ARM Cache ECC Warning */
#define SAM_IRQ_I2SC0 (SAM_IRQ_EXTINT+SAM_PID_I2SC0) /* Inter-IC Sound Controller 0 */
#define SAM_IRQ_I2SC1 (SAM_IRQ_EXTINT+SAM_PID_I2SC1) /* Inter-IC Sound Controller 1 */
#define SAM_IRQ_EMACQ3 (SAM_IRQ_EXTINT+SAM_PID_EMACQ3) /* EMAC Queue 3 Interrupt */
#define SAM_IRQ_EMACQ4 (SAM_IRQ_EXTINT+SAM_PID_EMACQ4) /* EMAC Queue 4 Interrupt */
#define SAM_IRQ_EMACQ5 (SAM_IRQ_EXTINT+SAM_PID_EMACQ5) /* EMAC Queue 5 Interrupt */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */ #define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */ #define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */