From 4b6166548b80c3db79b986197a253ec55a0db40a Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Mon, 15 May 2023 13:05:36 +0300 Subject: [PATCH] mpfs/mpfs_corespi: Add Kconfig for instance/irq offsets Also change the defaults --- arch/risc-v/src/mpfs/Kconfig | 14 ++++++++++++-- arch/risc-v/src/mpfs/mpfs_corespi.c | 4 ++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig index 99eec4bd0d..dc4e3984d0 100644 --- a/arch/risc-v/src/mpfs/Kconfig +++ b/arch/risc-v/src/mpfs/Kconfig @@ -452,7 +452,12 @@ config MPFS_CORESPI config MPFS_CORESPI_BASE hex "Base address for the (first) CoreSPI instance" - default 0x4A000000 + default 0x4B008000 + depends on MPFS_CORESPI + +config MPFS_CORESPI_INST_OFFSET + hex "Offset of instances in memory, base + n * offset finds instance n" + default 0x1000 depends on MPFS_CORESPI config MPFS_CORESPI_INSTANCES @@ -463,10 +468,15 @@ config MPFS_CORESPI_INSTANCES config MPFS_CORESPI_IRQNUM int "Number of (first) F2H interrupt" - default 4 + default 20 range 0 63 depends on MPFS_CORESPI +config MPFS_CORESPI_IRQNUM_OFFSET + int "Offset of interrupt source for instance n" + default 1 + depends on MPFS_CORESPI + endif # MPFS_HAVE_CORESPI comment "CorePWM Options" diff --git a/arch/risc-v/src/mpfs/mpfs_corespi.c b/arch/risc-v/src/mpfs/mpfs_corespi.c index ecd5a177d2..6180fa5ff1 100644 --- a/arch/risc-v/src/mpfs/mpfs_corespi.c +++ b/arch/risc-v/src/mpfs/mpfs_corespi.c @@ -90,8 +90,8 @@ #define MPFS_CORESPI_BASE CONFIG_MPFS_CORESPI_BASE #define MPFS_CORESPI_IRQNUM (MPFS_IRQ_FABRIC_F2H_0 + \ CONFIG_MPFS_CORESPI_IRQNUM) -#define MPFS_CORESPI_INST_OFFSET(n) ((n) * 0x1000000) -#define MPFS_CORESPI_IRQ_OFFSET(n) ((n) * 1) +#define MPFS_CORESPI_INST_OFFSET(n) ((n) * CONFIG_MPFS_CORESPI_INST_OFFSET) +#define MPFS_CORESPI_IRQ_OFFSET(n) ((n) * CONFIG_MPFS_CORESPI_IRQNUM_OFFSET) /* Gives TTOA in microseconds, ~4.8% bias, +1 rounds up */