SAMA5 NAND: Don't use HSMC interrupts. They occur to quickly and cause mysterious race conditions
This commit is contained in:
Gregory Nutt
parent
49bcf2da73
commit
4b8ba0cddc
@ -662,6 +662,7 @@ static void nand_nfc_configure(struct sam_nandcs_s *priv, uint8_t mode,
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static void nand_wait_cmddone(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqstate_t flags;
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int ret;
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@ -683,6 +684,12 @@ static void nand_wait_cmddone(struct sam_nandcs_s *priv)
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g_nand.cmddone = false;
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nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_CMDDONE);
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irqrestore(flags);
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#else
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/* Poll for the CMDDONE event */
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while((nand_getreg(SAM_HSMC_SR) & HSMC_NFCINT_CMDDONE) == 0);
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#endif
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}
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/****************************************************************************
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@ -701,6 +708,7 @@ static void nand_wait_cmddone(struct sam_nandcs_s *priv)
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static void nand_setup_cmddone(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqstate_t flags;
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/* Clear all pending interrupts. This must be done with interrupts
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@ -718,6 +726,11 @@ static void nand_setup_cmddone(struct sam_nandcs_s *priv)
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nand_putreg(SAM_HSMC_IER, HSMC_NFCINT_CMDDONE);
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irqrestore(flags);
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#else
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/* Just clear any pending CMDDONE status */
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nand_getreg(SAM_HSMC_SR);
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#endif
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}
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/****************************************************************************
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@ -736,6 +749,7 @@ static void nand_setup_cmddone(struct sam_nandcs_s *priv)
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static void nand_wait_xfrdone(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqstate_t flags;
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int ret;
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@ -757,6 +771,12 @@ static void nand_wait_xfrdone(struct sam_nandcs_s *priv)
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g_nand.xfrdone = false;
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nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_XFRDONE);
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irqrestore(flags);
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#else
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/* Poll for the XFRDONE event */
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while((nand_getreg(SAM_HSMC_SR) & HSMC_NFCINT_XFRDONE) == 0);
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#endif
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}
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/****************************************************************************
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@ -775,6 +795,7 @@ static void nand_wait_xfrdone(struct sam_nandcs_s *priv)
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static void nand_setup_xfrdone(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqstate_t flags;
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/* Clear all pending interrupts. This must be done with interrupts
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@ -792,6 +813,11 @@ static void nand_setup_xfrdone(struct sam_nandcs_s *priv)
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nand_putreg(SAM_HSMC_IER, HSMC_NFCINT_XFRDONE);
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irqrestore(flags);
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#else
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/* Just clear any pending XFRDONE status */
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nand_getreg(SAM_HSMC_SR);
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#endif
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}
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/****************************************************************************
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@ -810,6 +836,7 @@ static void nand_setup_xfrdone(struct sam_nandcs_s *priv)
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static void nand_wait_rbedge(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqstate_t flags;
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int ret;
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@ -831,6 +858,12 @@ static void nand_wait_rbedge(struct sam_nandcs_s *priv)
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g_nand.rbedge = false;
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nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_RBEDGE0);
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irqrestore(flags);
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#else
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/* Poll for the RBEDGE0 event */
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while((nand_getreg(SAM_HSMC_SR) & HSMC_NFCINT_RBEDGE0) == 0);
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#endif
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}
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/****************************************************************************
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@ -849,6 +882,7 @@ static void nand_wait_rbedge(struct sam_nandcs_s *priv)
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static void nand_setup_rbedge(struct sam_nandcs_s *priv)
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{
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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irqstate_t flags;
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/* Clear all pending interrupts. This must be done with interrupts
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@ -866,6 +900,12 @@ static void nand_setup_rbedge(struct sam_nandcs_s *priv)
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nand_putreg(SAM_HSMC_IER, HSMC_NFCINT_RBEDGE0);
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irqrestore(flags);
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#else
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/* Just clear any pending RBEDGE0 status */
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nand_getreg(SAM_HSMC_SR);
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#endif
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}
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/****************************************************************************
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@ -882,6 +922,7 @@ static void nand_setup_rbedge(struct sam_nandcs_s *priv)
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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static int hsmc_interrupt(int irq, void *context)
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{
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uint32_t sr = nand_getreg(SAM_HSMC_SR);
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@ -924,6 +965,7 @@ static int hsmc_interrupt(int irq, void *context)
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return OK;
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}
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#endif /* CONFIG_SAMA5_NAND_HSMCINTERRUPTS */
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/****************************************************************************
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* Name: nand_wait_dma
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@ -1251,6 +1293,8 @@ static int nand_read(struct sam_nandcs_s *priv, bool nfcsram,
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#endif
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int buswidth;
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fvdbg("nfcsram=%d buffer=%p buflen=%d\n", nfcsram, buffer, (int)buflen);
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/* Get the buswidth */
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buswidth = nandmodel_getbuswidth(&priv->raw.model);
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@ -1550,6 +1594,9 @@ static int nand_write(struct sam_nandcs_s *priv, bool nfcsram,
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#endif
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int buswidth;
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fvdbg("nfcsram=%d buffer=%p buflen=%d offset=%d\n",
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nfcsram, buffer, (int)buflen, (int)offset);
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/* Get the buswidth */
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buswidth = nandmodel_getbuswidth(&priv->raw.model);
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@ -2615,7 +2662,9 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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#if NAND_NBANKS > 1
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sem_init(&g_nand.exclsem, 0, 1);
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#endif
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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sem_init(&g_nand.waitsem, 0, 0);
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#endif
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/* Enable the NAND FLASH Controller (The NFC is always used) */
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@ -2634,6 +2683,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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nand_putreg(SAM_HSMC_PMECCFG, 0);
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#endif
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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/* Attach the CAN interrupt handler */
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ret = irq_attach(SAM_IRQ_HSMC, hsmc_interrupt);
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@ -2642,15 +2692,17 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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fdbg("Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC);
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return NULL;
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}
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#endif
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/* Disable all interrupts at the HSMC */
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nand_putreg(SAM_HSMC_IDR, HSMC_NFCINT_ALL);
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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/* Enable the HSMC interrupts at the interrupt controller */
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up_enable_irq(SAM_IRQ_HSMC);
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g_nand.initialized = true;
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#endif
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}
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/* Initialize the NAND hardware for this CS */
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@ -233,6 +233,17 @@
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#ifdef CONFIG_SAMA5_HAVE_NAND
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/* An early version of this driver used SMC interrupts to determine when
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* NAND commands completed, transfers completed, and RB edges occurred. It
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* turns out that those interrupts occurred so quickly that some really
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* nasty race conditions were created. Rather than resolve those, I simply
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* disabled the interrupt logic with this setting. The setting is retained
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* in case, for some reason, someone wants to restore the interrupt-driven
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* logic. Polling should be better solution in this case.
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*/
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#undef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -274,10 +285,12 @@ struct sam_nand_s
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/* Dynamic state */
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#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
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volatile bool cmddone; /* True: NFC command has completed */
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volatile bool xfrdone; /* True: Transfer has completed */
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volatile bool rbedge; /* True: Ready/busy edge detected */
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sem_t waitsem; /* Used to wait for one of the above states */
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#endif
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#ifdef CONFIG_SAMA5_HAVE_PMECC
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uint8_t ecctab[CONFIG_MTD_NAND_MAX_PMECCSIZE];
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