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XMC4xxx: Fix for early bringup problems

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This commit is contained in:
Gregory Nutt 2017-03-20 16:31:35 -06:00
parent e1f86f407f
commit 4ba091933e
6 changed files with 102 additions and 61 deletions
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5
arch/arm/include/xmc4/chip.h
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@ -50,7 +50,10 @@
#if defined(CONFIG_ARCH_CHIP_XMC4500)
# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */
# undef XMC4_SCU_GATING /* No clock gating registers */
#elif defined(CONFIG_ARCH_CHIP_XMC4700)
# define XMC4_NUSIC 3 /* Three USIC modules: USCI0-2 */
# define XMC4_SCU_GATING 1 /* Has clock gating registers */
#else
# error "Unsupported XMC4xxx chip"
#endif

3
arch/arm/src/xmc4/Kconfig
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@ -13,6 +13,9 @@ choice
config ARCH_CHIP_XMC4500
bool "XMC4500"
config ARCH_CHIP_XMC4700
bool "XMC4700"
endchoice
# These "hidden" settings determine is a peripheral option is available for

114
arch/arm/src/xmc4/chip/xmc4_scu.h
View File

@ -163,18 +163,20 @@
#define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */
#define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */
#define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */
#define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */
#define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */
#define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */
#define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */
#define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */
#define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */
#define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */
#define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */
#define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */
#define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */
#define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */
#define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */
#ifdef XMC4_SCU_GATING
# define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */
# define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */
# define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */
# define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */
# define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */
# define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */
# define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */
# define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */
# define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */
# define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */
# define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */
# define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */
#endif
/* Oscillator Control SCU Registers */
@ -292,18 +294,20 @@
#define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET)
#define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET)
#define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET)
#define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET)
#define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET)
#define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET)
#define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET)
#define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET)
#define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET)
#define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET)
#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET)
#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET)
#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET)
#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET)
#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET)
#ifdef XMC4_SCU_GATING
# define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET)
# define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET)
# define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET)
# define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET)
# define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET)
# define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET)
# define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET)
# define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET)
# define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET)
# define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET)
# define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET)
# define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET)
#endif
/* Oscillator Control SCU Registers */
@ -959,42 +963,50 @@
/* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set, Peripheral 0 Clock Gating Clear */
#define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */
#define SCU_CGAT0_DSD (1 << 1) /* Bit 1: DSD Gating Status */
#define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: CCU40 Gating Status */
#define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: CCU41 Gating Status */
#define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: CCU42 Gating Status */
#define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: CCU80 Gating Status */
#define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: CCU81 Gating Status */
#define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */
#define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */
#define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */
#define SCU_CGAT0_ERU1 (1 << 16) /* Bit 16: ERU1 Gating Status */
#ifdef XMC4_SCU_GATING
# define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */
# define SCU_CGAT0_DSD (1 << 1) /* Bit 1: DSD Gating Status */
# define SCU_CGAT0_CCU40 (1 << 2) /* Bit 2: CCU40 Gating Status */
# define SCU_CGAT0_CCU41 (1 << 3) /* Bit 3: CCU41 Gating Status */
# define SCU_CGAT0_CCU42 (1 << 4) /* Bit 4: CCU42 Gating Status */
# define SCU_CGAT0_CCU80 (1 << 7) /* Bit 7: CCU80 Gating Status */
# define SCU_CGAT0_CCU81 (1 << 8) /* Bit 8: CCU81 Gating Status */
# define SCU_CGAT0_POSIF0 (1 << 9) /* Bit 9: POSIF0 Gating Status */
# define SCU_CGAT0_POSIF1 (1 << 10) /* Bit 10: POSIF1 Gating Status */
# define SCU_CGAT0_USIC0 (1 << 11) /* Bit 11: USIC0 Gating Status */
# define SCU_CGAT0_ERU1 (1 << 16) /* Bit 16: ERU1 Gating Status */
#endif
/* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */
#define SCU_CGAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */
#define SCU_CGAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */
#define SCU_CGAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */
#define SCU_CGAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */
#define SCU_CGAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */
#define SCU_CGAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */
#define SCU_CGAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */
#define SCU_CGAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */
#ifdef XMC4_SCU_GATING
# define SCU_CGAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */
# define SCU_CGAT1_LEDTSCU0 (1 << 3) /* Bit 3: LEDTS Gating Status */
# define SCU_CGAT1_MCAN0 (1 << 4) /* Bit 4: MultiCAN Gating Status */
# define SCU_CGAT1_DAC (1 << 5) /* Bit 5: DAC Gating Status */
# define SCU_CGAT1_MMCI (1 << 6) /* Bit 6: MMC Interface Gating Status */
# define SCU_CGAT1_USIC1 (1 << 7) /* Bit 7: USIC1 Gating Status */
# define SCU_CGAT1_USIC2 (1 << 8) /* Bit 8: USIC1 Gating Status */
# define SCU_CGAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */
#endif
/* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */
#define SCU_CGAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */
#define SCU_CGAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */
#define SCU_CGAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */
#define SCU_CGAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */
#define SCU_CGAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */
#define SCU_CGAT2_USB (1 << 7) /* Bit 7: USB Gating Status */
#define SCU_CGAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */
#ifdef XMC4_SCU_GATING
# define SCU_CGAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */
# define SCU_CGAT2_ETH0 (1 << 2) /* Bit 2: ETH0 Gating Status */
# define SCU_CGAT2_DMA0 (1 << 4) /* Bit 4: DMA0 Gating Status */
# define SCU_CGAT2_DMA1 (1 << 5) /* Bit 5: DMA1 Gating Status */
# define SCU_CGAT2_FCE (1 << 6) /* Bit 6: FCE Gating Status */
# define SCU_CGAT2_USB (1 << 7) /* Bit 7: USB Gating Status */
# define SCU_CGAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */
#endif
/* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */
#define SCU_CGAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */
#ifdef XMC4_SCU_GATING
# define SCU_CGAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */
#endif
/* Oscillator Control SCU Registers */

6
arch/arm/src/xmc4/xmc4_clockconfig.c
View File

@ -313,9 +313,9 @@ void xmc4_clock_configure(void)
{
}
regval = getreg32(SCU_TRAP_SOSCWDGT);
regval &= ~bitset;
putreg32(regval, SCU_TRAP_SOSCWDGT);
regval = getreg32(XMC4_SCU_TRAPDIS);
regval &= ~SCU_TRAP_SOSCWDGT;
putreg32(regval, XMC4_SCU_TRAPDIS);
}
#else /* BOARD_PLL_CLOCKSRC_XTAL */

31
arch/arm/src/xmc4/xmc4_usic.c
View File

@ -112,6 +112,7 @@ int xmc4_enable_usic(enum usic_e usic)
switch (usic)
{
case USIC0:
#ifdef XMC4_SCU_GATING
/* Check if USIC0 is already ungated */
if ((getreg32(XMC4_SCU_CGATSTAT0) & SCU_CGAT0_USIC0) == 0)
@ -124,11 +125,16 @@ int xmc4_enable_usic(enum usic_e usic)
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0);
}
#else
/* De-assert peripheral reset USIC0 */
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0);
#endif
break;
#if XMC4_NUSIC > 1
case USIC1:
#ifdef XMC4_SCU_GATING
/* Check if USIC1 is already ungated */
if ((getreg32(XMC4_SCU_CGATSTAT1) & SCU_CGAT1_USIC1) == 0)
@ -141,11 +147,16 @@ int xmc4_enable_usic(enum usic_e usic)
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1);
}
#else
/* De-assert peripheral reset USIC1 */
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1);
#endif
break;
#if XMC4_NUSIC > 2
case USIC2:
#ifdef XMC4_SCU_GATING
/* Check if USIC2 is already ungated */
if ((getreg32(XMC4_SCU_CGATSTAT1) & SCU_CGAT1_USIC2) == 0)
@ -158,10 +169,15 @@ int xmc4_enable_usic(enum usic_e usic)
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1);
}
#else
/* De-assert peripheral reset USIC2 */
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1);
#endif
break;
#endif
#endif
#endif /* XMC4_NUSIC > 2 */
#endif /* XMC4_NUSIC > 1 */
default:
return -EINVAL;
@ -191,9 +207,11 @@ int xmc4_disable_usic(enum usic_e usic)
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0);
#ifdef XMC4_SCU_GATING
/* Gate USIC0 clocking */
putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATSET0);
#endif
break;
#if XMC4_NUSIC > 1
@ -202,9 +220,11 @@ int xmc4_disable_usic(enum usic_e usic)
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1);
#ifdef XMC4_SCU_GATING
/* Gate USIC0 clocking */
putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATSET1);
#endif
break;
#if XMC4_NUSIC > 2
@ -213,12 +233,15 @@ int xmc4_disable_usic(enum usic_e usic)
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1);
#ifdef XMC4_SCU_GATING
/* Gate USIC0 clocking */
putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATSET1);
#endif
break;
#endif
#endif
#endif /* XMC4_NUSIC > 2 */
#endif /* XMC4_NUSIC > 1 */
default:
return -EINVAL;

4
configs/xmc4500-relax/nsh/defconfig
View File

@ -250,8 +250,8 @@ CONFIG_BOOT_RUNFROMFLASH=y
#
# Boot Memory Configuration
#
CONFIG_RAM_START=0x20400000
CONFIG_RAM_SIZE=393216
CONFIG_RAM_START=0x20000000
CONFIG_RAM_SIZE=65536
# CONFIG_ARCH_HAVE_SDRAM is not set
#