/arch/arm/src/lpc54xx: Add some GPIO pin interrupt header files (still missing one). Also add a file that was missing in previous commit.
This commit is contained in:
Gregory Nutt
parent
52f9128562
commit
4bc7b966f4
102
arch/arm/src/lpc54xx/chip/lpc54_gint.h
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102
arch/arm/src/lpc54xx/chip/lpc54_gint.h
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/****************************************************************************************************
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* arch/arm/src/lpc54xx/lpc54_gint.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H
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#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/lpc54_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register offsets *********************************************************************************/
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#define LPC54_GINT_CTRL_OFFSET 0x0000 /* GPIO grouped interrupt control */
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#define LPC54_GINT_PORT_POL0_OFFSET 0x0020 /* GPIO grouped interrupt port 0 polarity */
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#define LPC54_GINT_PORT_POL0_OFFSET 0x0024 /* GPIO grouped interrupt port 1 polarity */
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#define LPC54_GINT_PORT_ENA0_OFFSET 0x0040 /* GPIO grouped interrupt port 0 enable */
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#define LPC54_GINT_PORT_ENA1_OFFSET 0x0044 /* GPIO grouped interrupt port 1 enable */
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/* Register addresses *******************************************************************************/
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#define LPC54_GINT0_CTRL (LPC54_GINT0_BASE + LPC54_GINT_CTRL_OFFSET)
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#define LPC54_GINT0_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL0_OFFSET)
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#define LPC54_GINT0_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL1_OFFSET)
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#define LPC54_GINT0_PORT_ENA0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA0_OFFSET)
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#define LPC54_GINT0_PORT_ENA1 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA1_OFFSET)
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#define LPC54_GINT1_CTRL (LPC54_GINT0_BASE + LPC54_GINT_CTRL_OFFSET)
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#define LPC54_GINT1_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL0_OFFSET)
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#define LPC54_GINT1_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL1_OFFSET)
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#define LPC54_GINT1_PORT_ENA0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA0_OFFSET)
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#define LPC54_GINT1_PORT_ENA1 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA1_OFFSET)
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/* Register bit definitions *************************************************************************/
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/* GPIO grouped interrupt control */
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#define GINT_CTRL_INT (1 << 0) /* Bit 0: Group interrupt status */
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#define GINT_CTRL_COMB (1 << 1) /* Bit 1: Combine enabled inputs for group interrupt 0 */
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#define GINT_CTRL_TRIG (1 << 2) /* Bit 2" Group interrupt trigger 0 */
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/* GPIO grouped interrupt port 0/1 polarity */
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#define GINT_PORT_POL0(n) (1 << (n)) /* Configure pin polarity of port0 pins for group interrupt */
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#define GINT_PORT_POL1(n) (1 << (n)) /* Configure pin polarity of port1 pins for group interrupt */
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/* GPIO grouped interrupt port 0/1 enable */
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#define GINT_PORT_ENA0(n) (1 << (n)) /* Enable port0 pin for group interrupt */
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#define GINT_PORT_ENA1(n) (1 << (n)) /* Enable port1 pin for group interrupt */
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H */
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53
arch/arm/src/lpc54xx/chip/lpc54_pinmux.h
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53
arch/arm/src/lpc54xx/chip/lpc54_pinmux.h
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@ -0,0 +1,53 @@
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/************************************************************************************
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* arch/arm/src/lpc54xx/chip/lpc54_pinmux.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H
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#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "lpc54_gpio.h"
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#if defined(CONFIG_ARCH_FAMILY_LPC546XX)
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# include "chip/lpc546x_pinmux.h"
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#else
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# error "Unsupported LPC54 family"
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#endif
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H */
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@ -82,30 +82,120 @@
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/* Register bit definitions *************************************************************************/
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/* Pin interrupt mode */
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#define PINT_ISEL_
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/* Pin interrupt level or rising edge interrupt enable */
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#define PINT_IENR_
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/* Pin interrupt level or rising edge interrupt enable set */
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#define PINT_SIENR_
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/* Pin interrupt level or rising edge interrupt enable clear */
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#define PINT_CIENR_
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/* Pin interrupt active level or falling edge interrupt enable */
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#define PINT_IENF_
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/* Pin interrupt active level or falling edge interrupt set */
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#define PINT_SIENF_
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/* Pin interrupt active level or falling edge interrupt clear */
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#define PINT_CIENF_
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#define PINT_PMODE(n) (1 << (n)) /* Pin n level(1) or edge(0) sensitive. n=0..7 */
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/* Pin interrupt level or rising edge interrupt enable, set, and clear registers */
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#define PINT_ENRL(n) (1 << (n)) /* Pin n enable(1) or disable(0) rising/level. n=0..7 */
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/* Pin interrupt active level or falling edge interrupt enable, set, and clear registers */
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#define PINT_ENAF(n) (1 << (n)) /* Pin n enable(1) or disable(0) falling/active. n=0..7 */
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/* Pin interrupt rising edge */
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#define PINT_RISE_
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#define PINT_RDET(n) (1 << (n)) /* R:Rising edge detected, W:Clear. n=0..7 */
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/* Pin interrupt falling edge */
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#define PINT_FALL_
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#define PINT_FDET(n) (1 << (n)) /* R:Falling edge detected, W:Clear. n=0..7 */
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/* Pin interrupt status */
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#define PINT_IST_
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#define PINT_PSTAT(n) (1 << (n)) /* R:Interrupt pending, W:Clear edge or toggle level. n=0..7 */
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/* Pattern match interrupt control */
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#define PINT_PMCTRL_
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#define PINT_PMCTRL_SELPMATCH (1 << 0) /* Bit 0: Rin interrupts interrupt or pattern match function */
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#define PINT_PMCTRL_ENARXEV (1 << 1) /* Bit 1: Enables RXEV output to CPU */
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#define PINT_PMCTRL_PMAT_SHIFT (24) /* Bits 24-31: Current state of pattern matches */
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/* Pattern match interrupt bit-slice source */
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#define PINT_PMSRC_
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/* PINTSELn=1 indicates that PINSETn is the source to bit slice m. */
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#define PINT_PMSRC_PINTSEL0 0
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#define PINT_PMSRC_PINTSEL1 1
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#define PINT_PMSRC_PINTSEL2 2
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#define PINT_PMSRC_PINTSEL3 3
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#define PINT_PMSRC_PINTSEL4 4
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#define PINT_PMSRC_PINTSEL5 5
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#define PINT_PMSRC_PINTSEL6 6
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#define PINT_PMSRC_PINTSEL7 7
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#define PINT_PMSRC_SRC0_SHIFT (8) /* Bits 8-10: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC0_MASK (7 << PINT_PMSRC_SRC0_SHIFT)
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# define PINT_PMSRC_SRC0(n) ((uint32_t)(n) << PINT_PMSRC_SRC0_SHIFT)
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#define PINT_PMSRC_SRC1_SHIFT (11) /* Bits 11-13: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC1_MASK (7 << PINT_PMSRC_SRC1_SHIFT)
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# define PINT_PMSRC_SRC1(n) ((uint32_t)(n) << PINT_PMSRC_SRC1_SHIFT)
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#define PINT_PMSRC_SRC2_SHIFT (14) /* Bits 14-16: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC2_MASK (7 << PINT_PMSRC_SRC2_SHIFT)
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# define PINT_PMSRC_SRC2(n) ((uint32_t)(n) << PINT_PMSRC_SRC2_SHIFT)
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#define PINT_PMSRC_SRC3_SHIFT (17) /* Bits 17-19: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC3_MASK (7 << PINT_PMSRC_SRC3_SHIFT)
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# define PINT_PMSRC_SRC3(n) ((uint32_t)(n) << PINT_PMSRC_SRC3_SHIFT)
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#define PINT_PMSRC_SRC4_SHIFT (20) /* Bits 20-22: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC4_MASK (7 << PINT_PMSRC_SRC4_SHIFT)
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# define PINT_PMSRC_SRC4(n) ((uint32_t)(n) << PINT_PMSRC_SRC4_SHIFT)
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#define PINT_PMSRC_SRC5_SHIFT (23) /* Bits 23-25: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC5_MASK (7 << PINT_PMSRC_SRC5_SHIFT)
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# define PINT_PMSRC_SRC5(n) ((uint32_t)(n) << PINT_PMSRC_SRC5_SHIFT)
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#define PINT_PMSRC_SRC6_SHIFT (26) /* Bits 26-28: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC6_MASK (7 << PINT_PMSRC_SRC6_SHIFT)
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# define PINT_PMSRC_SRC6(n) ((uint32_t)(n) << PINT_PMSRC_SRC6_SHIFT)
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#define PINT_PMSRC_SRC7_SHIFT (29) /* Bits 29-31: Selects PINSELn as input source for bit slice 0 */
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#define PINT_PMSRC_SRC7_MASK (7 << PINT_PMSRC_SRC7_SHIFT)
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# define PINT_PMSRC_SRC7(n) ((uint32_t)(n) << PINT_PMSRC_SRC7_SHIFT)
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/* Pattern match interrupt bit slice configuration */
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#define PINT_PMCFG_
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/* PINT_PMCFG_ENDPTSn: Determines whether slice n is an endpoint of a product term (minterm). Pin
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* interrupt n in the NVIC is raised if the minterm evaluates as true.
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*/
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#define PINT_PMCFG_ENDPTS0 (1 << 0) /* Bit 0: Slice n is an endpoint */
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#define PINT_PMCFG_ENDPTS1 (1 << 1) /* Bit 1: Slice n is an endpoint */
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#define PINT_PMCFG_ENDPTS2 (1 << 2) /* Bit 2: Slice n is an endpoint */
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#define PINT_PMCFG_ENDPTS3 (1 << 3) /* Bit 3: Slice n is an endpoint */
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#define PINT_PMCFG_ENDPTS4 (1 << 4) /* Bit 4: Slice n is an endpoint */
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#define PINT_PMCFG_ENDPTS5 (1 << 5) /* Bit 5: Slice n is an endpoint */
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#define PINT_PMCFG_ENDPTS6 (1 << 6) /* Bit 6: Slice n is an endpoint */
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#define PINT_PMCFG_HIGH 0 /* Constant HIGH */
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#define PINT_PMCFG_RISING 1 /* Sticky rising edge */
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#define PINT_PMCFG_FALLING 2 /* Sticky falling edge */
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#define PINT_PMCFG_BOTH 3 /* Sticky rising or falling edge */
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#define PINT_PMCFG_HIGH_LEVEL 4 /* High level */
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#define PINT_PMCFG_LOW_LEVEL 5 /* Low level */
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#define PINT_PMCFG_ZERO 6 /* Constant 0 */
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#define PINT_PMCFG_EVENT 7 /* Event */
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#define PINT_PMCFG_CFG0_SHIFT (8) /* Bits 8-10: Match condition for bit slice 0 */
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#define PINT_PMCFG_CFG0_MASK (7 << PINT_PMCFG_CFG0_SHIFT)
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# define PINT_PMCFG_CFG0(n) ((uint32_t)(n) << PINT_PMCFG_CFG0_SHIFT)
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#define PINT_PMCFG_CFG1_SHIFT (8) /* Bits 11-13: Match condition for bit slice 1 */
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#define PINT_PMCFG_CFG1_MASK (7 << PINT_PMCFG_CFG1_SHIFT)
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# define PINT_PMCFG_CFG1(n) ((uint32_t)(n) << PINT_PMCFG_CFG1_SHIFT)
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#define PINT_PMCFG_CFG2_SHIFT (8) /* Bits 14-16: Match condition for bit slice 2 */
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#define PINT_PMCFG_CFG2_MASK (7 << PINT_PMCFG_CFG2_SHIFT)
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# define PINT_PMCFG_CFG2(n) ((uint32_t)(n) << PINT_PMCFG_CFG2_SHIFT)
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#define PINT_PMCFG_CFG3_SHIFT (8) /* Bits 17-19: Match condition for bit slice 3 */
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#define PINT_PMCFG_CFG3_MASK (7 << PINT_PMCFG_CFG3_SHIFT)
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# define PINT_PMCFG_CFG3(n) ((uint32_t)(n) << PINT_PMCFG_CFG3_SHIFT)
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#define PINT_PMCFG_CFG4_SHIFT (8) /* Bits 20-22: Match condition for bit slice 4 */
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#define PINT_PMCFG_CFG4_MASK (7 << PINT_PMCFG_CFG4_SHIFT)
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# define PINT_PMCFG_CFG4(n) ((uint32_t)(n) << PINT_PMCFG_CFG4_SHIFT)
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#define PINT_PMCFG_CFG5_SHIFT (8) /* Bits 23-25: Match condition for bit slice 5 */
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#define PINT_PMCFG_CFG5_MASK (7 << PINT_PMCFG_CFG5_SHIFT)
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# define PINT_PMCFG_CFG5(n) ((uint32_t)(n) << PINT_PMCFG_CFG5_SHIFT)
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#define PINT_PMCFG_CFG6_SHIFT (8) /* Bits 26-28: Match condition for bit slice 6 */
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#define PINT_PMCFG_CFG6_MASK (7 << PINT_PMCFG_CFG6_SHIFT)
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# define PINT_PMCFG_CFG6(n) ((uint32_t)(n) << PINT_PMCFG_CFG6_SHIFT)
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#define PINT_PMCFG_CFG7_SHIFT (8) /* Bits 29-31: Match condition for bit slice 7 */
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#define PINT_PMCFG_CFG7_MASK (7 << PINT_PMCFG_CFG7_SHIFT)
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# define PINT_PMCFG_CFG7(n) ((uint32_t)(n) << PINT_PMCFG_CFG7_SHIFT)
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H */
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