From 4c0aa6133cbab0712c20093a92fd032115c1ae6d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 16 Jun 2018 14:41:47 -0600 Subject: [PATCH] Update TODO list --- TODO | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/TODO b/TODO index caf40853c8..e9dcf61970 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated June 6, 2018) +NuttX TODO List (Last updated June 16, 2018) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -10,7 +10,7 @@ issues related to each board port. nuttx/: (15) Task/Scheduler (sched/) - (1) SMP + (3) SMP (1) Memory Management (mm/) (0) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -431,6 +431,57 @@ o SMP Status: Closed Priority: High on platforms that may have the issue. + Title: MISUSE OF sched_lock() IN SMP MODE + Description: The OS API sched_lock() disables pre-emption and locks a + task in place. In the single CPU case, it is also often + used to enforce a simple critical section since not other + task can run while pre-emption is locked. + + This, however, does not generalize to the SMP case. In the + SMP case, there are multiple tasks running on multiple CPUs. + The basic behavior is still correct: The task that has + locked pre-emption will not be suspended. However, there + is no longer any protection for use as a critical section: + tasks running on other CPUs may still execute that that + unprotect code regsion. + + The solution is to replace the use of sched_lock() with + stronger protection such as spin_lock_irqsave(). + Status: Open + Priority: Medium for SMP system. Not critical to single CPU systems. + NOTE: There are no known bugs from this protential problem. + + Title: CORTEX-A GIC SGI INTERRUPT MASKING + Description: In the ARMv7-A GICv2 architecture, the inter-processor + interrupts (SGIs) are non maskable and will occur even if + interrupts are disabled. This addes a lot of complexity + to the ARMV7-A critical section design. + + Masayuki Ishakawa has suggest the use of the GICv2 ICCMPR + register to control SGI interrupts. This register (much like + the ARMv7-M BASEPRI register) can be used to mask interrupts + by interrupt priority. Since SGIs may be assigned priorities + the ICCMPR should be able to block execution of SGIs as well. + + Such an implementation would be very similar to the BASEPRI + (vs PRIMASK) implementation for the ARMv7-M: (1) The + up_irq_save() and up_irq_restore() registers would have to + set/restore the ICCMPR register, (2) register setup logic in + arch/arm/src/armv7-a for task start-up and signal dispatch + would have to set the ICCMPR correctly, and (3) the 'xcp' + structure sould have to be extended to hold the ICCMPR + register; logic would have to added be save/restore the + ICCMPR register in the 'xcp' structure on each interrupt and + context switch. + + This would also be an essential part of a high priority, + nested interrupt implementation (unrelated). + Status: Open + Priority: Low. There are no know issues with the current non-maskable + SGI implementation. This change would, however, lead to + simplification in the design and permit commonality with + other, non-GIC imoplementations. + o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^