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Fix an error introduced into stm32_pwr_enablebkp(). That function must preserve the previous state of backup domain access on return.

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This commit is contained in:
Gregory Nutt 2015-04-18 07:31:20 -06:00
parent 383f6c52dd
commit 4c0b8fba52
6 changed files with 47 additions and 25 deletions
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6
arch/arm/src/stm32/stm32_bbsram.c
View File

@ -246,9 +246,9 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
*
****************************************************************************/
static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_unlock(void)
{
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
}
/****************************************************************************
@ -268,7 +268,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
}
/****************************************************************************

11
arch/arm/src/stm32/stm32_lse.c
View File

@ -74,12 +74,14 @@
void stm32_rcc_enablelse(void)
{
bool bkpenabled;
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
stm32_pwr_enablebkp(true);
bkpenabled = stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
@ -111,5 +113,10 @@ void stm32_rcc_enablelse(void)
#endif
stm32_pwr_enablebkp(false);
/* Disable backup domain access if it was disabled on entry */
if (!bkpenabled)
{
(void)stm32_pwr_enablebkp(false);
}
}

33
arch/arm/src/stm32/stm32_pwr.c
View File

@ -88,28 +88,43 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
* Input Parameters:
* protect - sets the write protections
*
* Returned Values:
* None
* Returned Value:
* True: The backup domain was previously writable.
*
************************************************************************************/
void stm32_pwr_enablebkp(bool writable)
bool stm32_pwr_enablebkp(bool writable)
{
uint16_t regval;
bool waswritable;
/* Enable or disable the ability to write*/
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
regval &= ~PWR_CR_DBP;
regval |= writable ? PWR_CR_DBP : 0;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
waswritable = ((regval & PWR_CR_DBP) != 0);
if (writable)
/* Enable or disable the ability to write */
if (waswritable && !writable)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
else if (!waswritable && writable)
{
/* Enable backup domain access */
regval |= PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/************************************************************************************

6
arch/arm/src/stm32/stm32_pwr.h
View File

@ -76,12 +76,12 @@ extern "C"
* Input Parameters:
* writable - sets the write protections
*
* Returned Values:
* None
* Returned Value:
* True: The backup domain was previously writable.
*
************************************************************************************/
void stm32_pwr_enablebkp(bool writable);
bool stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg

12
arch/arm/src/stm32/stm32_rtcc.c
View File

@ -253,7 +253,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@ -292,7 +292,7 @@ static inline void rtc_wprlock(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
}
/************************************************************************************
@ -627,7 +627,7 @@ int up_rtcinitialize(void)
regval = getreg32(RTC_MAGIC_REG);
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@ -705,7 +705,7 @@ int up_rtcinitialize(void)
}
}
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the RTC
@ -756,7 +756,7 @@ int up_rtcinitialize(void)
* backup data registers and backup SRAM).
*/
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
@ -776,7 +776,7 @@ int up_rtcinitialize(void)
* data registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
if (ret != OK && nretry > 0)
{

4
arch/arm/src/stm32/stm32_rtcounter.c
View File

@ -370,7 +370,7 @@ int up_rtcinitialize(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* Set access to the peripheral, enable the backup domain (BKP) and the lower
* power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the
@ -421,7 +421,7 @@ int up_rtcinitialize(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
return OK;
}