From 4c5cbdfae35b2738d3dc818fbd73d99c5959ced3 Mon Sep 17 00:00:00 2001 From: Daniel Pereira Volpato Date: Mon, 4 Nov 2019 14:11:36 -0600 Subject: [PATCH] boards/arm/stm32f0l0g0/nucleo-g070rb: boards/arm/stm32f0l0g0/nucleo-g070rb: Add button driver support, Add driver support. Add GPIO example. Includes fixes to the GPIO driver support from Guillherme Amaral . --- .../arm/stm32f0l0g0/nucleo-g070rb/README.txt | 2 + .../nucleo-g070rb/configs/nsh/defconfig | 8 + .../stm32f0l0g0/nucleo-g070rb/src/Makefile | 4 + .../nucleo-g070rb/src/nucleo-g070rb.h | 22 ++ .../nucleo-g070rb/src/stm32_bringup.c | 22 ++ .../nucleo-g070rb/src/stm32_gpio.c | 365 ++++++++++++++++++ 6 files changed, 423 insertions(+) create mode 100644 boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt b/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt index 9923171b74..73c0433a05 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/README.txt @@ -10,3 +10,5 @@ STATUS Basic NSH configuration is functional. 2019-09-16: Enable PWR peripheral and increase sysclk to max. frequency. 2019-10-04: Enable basic timer TIM6. Timer example working. + 2019-10-17: Add PWM support. PWM example working. + 2019-11-04: Add button driver and GPIO driver support. Buttons and GPIO examples working. diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index b3ebaf9543..35de07098a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -10,23 +10,31 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g070rb" CONFIG_ARCH_BOARD_NUCLEO_G070RB=y +CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" CONFIG_ARCH_CHIP_STM32G070RB=y CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_BUILTIN=y +CONFIG_BUTTONS=y +CONFIG_BUTTONS_LOWER=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_GPIO=y CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MQUEUE=y CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_PWM=y CONFIG_EXAMPLES_TIMER=y +CONFIG_INPUT=y CONFIG_INTELHEX_BINARY=y CONFIG_MAX_TASKS=8 CONFIG_MAX_WDOGPARMS=2 diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Makefile b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Makefile index 727c63c240..4fb9909ec2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Makefile +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Makefile @@ -51,6 +51,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h index 2137cf91d1..539d4623c8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h @@ -100,6 +100,24 @@ #define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | \ GPIO_PIN13) +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +/* Input pins */ + +#define GPIO_IN1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN4) + +/* Interrupt pins */ + +#define GPIO_INT1 GPIO_BTN_USER + +/* Output pins */ + +#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_FLOAT | GPIO_PORTC | GPIO_PIN7) + /**************************************************************************** * Public Data ****************************************************************************/ @@ -108,6 +126,10 @@ * Public Function Prototypes ****************************************************************************/ +#ifdef CONFIG_DEV_GPIO +int stm32_gpio_initialize(void); +#endif + /**************************************************************************** * Name: stm32_pwm_setup * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c index 50e6210635..53c640ca90 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c @@ -46,6 +46,7 @@ #include #include +#include #include #include "nucleo-g070rb.h" @@ -101,6 +102,27 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_ADC /* Initialize ADC and register the ADC driver. */ diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c new file mode 100644 index 0000000000..fce147b3b5 --- /dev/null +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c @@ -0,0 +1,365 @@ +/**************************************************************************** + * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c + * + * Copyright (C) 2019 Fundação CERTI. All rights reserved. + * Author: Daniel Pereira Volpato + * Guillherme da Silva Amaral + * + * Based on: boards/arm/stm32f7/nucleo-144/src/stm32_gpio.c + * Author: Alan Carvalho de Assis + * Philippe Coval + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "nucleo-g070rb.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpout_write(FAR struct gpio_dev_s *dev, bool value); +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value); +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ +#if BOARD_NGPIOIN > 0 + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +#else + return ERROR; +#endif +} + +static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ +#if BOARD_NGPIOOUT > 0 + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +#else + return ERROR; +#endif +} + +static int gpout_write(FAR struct gpio_dev_s *dev, bool value) +{ +#if BOARD_NGPIOOUT > 0 + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +#else + return ERROR; +#endif +} + +static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) +{ +#if BOARD_NGPIOINT > 0 + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +#else + return ERROR; +#endif +} + +static int gpint_attach(FAR struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ +#if BOARD_NGPIOINT > 0 + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + (void)stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +#else + return ERROR; +#endif +} + +static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) +{ +#if BOARD_NGPIOINT > 0 + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + (void)stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + (void)stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +#else + return ERROR; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + (void)gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + (void)gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + (void)gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */