Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL."
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
This commit is contained in:
Mateusz Szafoni
Gregory Nutt
parent
5130f366e2
commit
4c601faf6f
@ -309,6 +309,7 @@ config ARCH_CHIP_STM32F0
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config ARCH_CHIP_STM32L0
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bool "STMicro STM32 L0"
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select ARCH_CORTEXM0
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depends on EXPERIMENTAL
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---help---
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STMicro STM32L0 architectures (ARM Cortex-M0).
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/include/stm32f0l0/chip.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Alan Carvalho de Assis <acassis@gmail.com>
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*
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@ -50,9 +50,6 @@
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
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# define STM32F051x 1 /* STM32F051x family */
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# undef STM32F072x /* Not STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# define STM32_SRAM_SIZE (8*1024) /* 8Kb */
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@ -62,7 +59,8 @@
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 2 /* Two USARTs modules */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 1 /* One DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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@ -70,9 +68,6 @@
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
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# undef STM32F051x /* Not STM32F051x family */
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# define STM32F072x 1 /* STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F072C8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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@ -90,7 +85,8 @@
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 10 /* Ten external channels */
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@ -102,9 +98,6 @@
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
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# undef STM32F051x /* Not STM32F051x family */
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# define STM32F072x 1 /* STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F072R8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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@ -122,7 +115,8 @@
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 16 /* 16 external channels */
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@ -134,9 +128,6 @@
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
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# undef STM32F051x /* Not STM32F051x family */
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# define STM32F072x 1 /* STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F072V8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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@ -154,7 +145,8 @@
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NUSBDEV 1 /* One USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 16 /* 16 external channels */
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@ -166,9 +158,6 @@
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
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# undef STM32F051x /* Not STM32F051x family */
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# undef STM32F072x /* Not STM32F072x family */
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# define STM32F091x 1 /* STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F091CB
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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@ -186,7 +175,8 @@
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 6 /* Six USARTs modules */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 0 /* No USB device controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 10 /* 10 external channels */
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@ -197,11 +187,8 @@
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# define STM32_NCAP 17 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \
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|| defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# undef STM32F051x /* Not STM32F051x family */
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# undef STM32F072x /* Not STM32F072x family */
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# define STM32F091x 1 /* STM32F091x family */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \
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defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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@ -219,7 +206,8 @@
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 8 /* Eight USARTs modules */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 0 /* No USB device controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 16 /* 16 external channels */
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@ -234,6 +222,222 @@
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# endif
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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/* STM32L EnergyLite Line ***********************************************************/
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/* STM32L03XX - With LCD
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* STM32L02XX - No LCD
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*
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* STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM
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* STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM
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* STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM
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*
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* STM32L0XXCX - 48-pins
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* STM32L0XXRX - 64-pins
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* STM32L0XXVX - 100-pins
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \
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defined(CONFIG_ARCH_CHIP_STM32L072VZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit ADC module */
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# define STM32_NADCCHAN 14 /* 14 channels */
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# define STM32_NADCINT 0 /* ? internal channels vs external? */
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# define STM32_NDAC 2 /* Two DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 14-channels */
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# define STM32_NDAC 2 /* Two DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit ADC module */
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# define STM32_NADCCHAN 14 /* 14 channels */
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# define STM32_NADCINT 0 /* ? internal channels vs external? */
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# define STM32_NDAC 2 /* Two DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit ADC module */
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# define STM32_NADCCHAN 14 /* 14 channels */
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# define STM32_NADCINT 0 /* ? internal channels vs external? */
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# define STM32_NDAC 2 /* Two DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \
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defined(CONFIG_ARCH_CHIP_STM32L073VZ)
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
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* (with DMA) and TIM21-22 without DMA */
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# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
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# define STM32_NI2S 1 /* One I2S module */
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# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 1 /* One DMA1, 7-channels */
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# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
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/* One LPUART */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NLCD 1 /* One LCD controller */
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NCEC 0 /* No HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit ADC module */
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# define STM32_NADCCHAN 14 /* 14 channels */
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# define STM32_NADCINT 0 /* ? internal channels vs external? */
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# define STM32_NDAC 2 /* Two DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ)
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# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 1 /* One LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC12 1 /* One 12-bit ADC module */
|
||||
# define STM32_NADCCHAN 14 /* 14 channels */
|
||||
# define STM32_NADCINT 0 /* ? internal channels vs external? */
|
||||
# define STM32_NDAC 2 /* Two DAC module */
|
||||
# define STM32_NDACCHAN 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ)
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3
|
||||
* (with DMA) and TIM21-22 without DMA */
|
||||
# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
|
||||
# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
|
||||
/* One LPTIMER */
|
||||
# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */
|
||||
# define STM32_NI2S 1 /* One I2S module */
|
||||
# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */
|
||||
# define STM32_NDMA 1 /* One DMA1, 7-channels */
|
||||
# define STM32_NUSART 4 /* Four USART modules, USART1-4 */
|
||||
/* One LPUART */
|
||||
# define STM32_NCAN 0 /* No CAN controllers */
|
||||
# define STM32_NLCD 1 /* One LCD controller */
|
||||
# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
|
||||
# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NCEC 0 /* No HDMI-CEC controller */
|
||||
# define STM32_NADC12 1 /* One 12-bit ADC module */
|
||||
# define STM32_NADCCHAN 14 /* 14 channels */
|
||||
# define STM32_NADCINT 0 /* ? internal channels vs external? */
|
||||
# define STM32_NDAC 2 /* Two DAC module */
|
||||
# define STM32_NDACCHAN 2 /* Two DAC channels */
|
||||
# define STM32_NCOMP 2 /* Two Analog Comparators */
|
||||
# define STM32_NCRC 1 /* One CRC module */
|
||||
# define STM32_NRNG 1 /* One Random number generator (RNG) */
|
||||
# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
|
||||
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
|
||||
|
||||
#else
|
||||
# error "Unsupported STM32F0xx chip"
|
||||
#endif
|
||||
|
||||
@ -78,9 +78,9 @@
|
||||
|
||||
/* Include MCU-specific external interrupt definitions */
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_STM32F0)
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include <arch/stm32f0l0/stm32f0_irq.h>
|
||||
#elif defined(CONFIG_STM32F0L0_STM32L0)
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include <arch/stm32f0l0/stm32l0_irq.h>
|
||||
#else
|
||||
# error Unrecognized STM32 Cortex M0 family
|
||||
|
||||
@ -45,49 +45,54 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <arch/stm32f0l0/chip.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Include STM32F0-specific external interrupt definitions */
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
|
||||
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
|
||||
* to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be found
|
||||
* in nuttx/arch/arm/include/stm32f0l0/irq.h
|
||||
*/
|
||||
|
||||
#define STM32_IRQ_WWDG (16) /* Vector 16: WWDG */
|
||||
#define STM32_IRQ_PVD_VDDIO2 (17) /* Vector 17: PVD_VDDIO2 */
|
||||
#define STM32_IRQ_RTC (18) /* Vector 18: RTC */
|
||||
#define STM32_IRQ_FLASH (19) /* Vector 19: FLASH */
|
||||
#define STM32_IRQ_RCC_CRS (20) /* Vector 20: RCC and CRS */
|
||||
#define STM32_IRQ_EXTI0_1 (21) /* Vector 21: EXTI0_1 */
|
||||
#define STM32_IRQ_EXTI2_3 (22) /* Vector 22: EXTI2_3 */
|
||||
#define STM32_IRQ_EXTI4_15 (23) /* Vector 23: EXTI4_15 */
|
||||
#define STM32_IRQ_TSC (24) /* Vector 24: TSC */
|
||||
#define STM32_IRQ_DMA_CH1 (25) /* Vector 25: DMA_CH1 */
|
||||
#define STM32_IRQ_DMA_CH23 (26) /* Vector 26: DMA_CH2_3 and DMA2_CH1_2 */
|
||||
#define STM32_IRQ_DMA_CH4567 (27) /* Vector 27: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
|
||||
#define STM32_IRQ_ADC_COMP (28) /* Vector 28: ADC_COMP */
|
||||
#define STM32_IRQ_TIM1_BRK (29) /* Vector 29: TIM1_BRK_UP_TRG_COM */
|
||||
#define STM32_IRQ_TIM1_CC (30) /* Vector 30: TIM1_CC */
|
||||
#define STM32_IRQ_TIM2 (31) /* Vector 31: TIM2 */
|
||||
#define STM32_IRQ_TIM3 (32) /* Vector 32: TIM3 */
|
||||
#define STM32_IRQ_TIM6_DAC (33) /* Vector 33: TIM6 and DAC */
|
||||
#define STM32_IRQ_TIM7 (34) /* Vector 34: TIM7 */
|
||||
#define STM32_IRQ_TIM14 (35) /* Vector 35: TIM14 */
|
||||
#define STM32_IRQ_TIM15 (36) /* Vector 36: TIM15 */
|
||||
#define STM32_IRQ_TIM16 (37) /* Vector 37: TIM16 */
|
||||
#define STM32_IRQ_TIM17 (38) /* Vector 38: TIM17 */
|
||||
#define STM32_IRQ_I2C1 (39) /* Vector 39: I2C1 */
|
||||
#define STM32_IRQ_I2C2 (40) /* Vector 40: I2C2 */
|
||||
#define STM32_IRQ_SPI1 (41) /* Vector 41: SPI1 */
|
||||
#define STM32_IRQ_SPI2 (42) /* Vector 42: SPI2 */
|
||||
#define STM32_IRQ_USART1 (43) /* Vector 43: USART1 */
|
||||
#define STM32_IRQ_USART2 (44) /* Vector 44: USART2 */
|
||||
#define STM32_IRQ_USART345678 (45) /* Vector 45: USART3_4_5_6_7_8 */
|
||||
#define STM32_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */
|
||||
#define STM32_IRQ_USB (47) /* Vector 47: USB */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */
|
||||
#define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */
|
||||
#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: FLASH */
|
||||
#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS */
|
||||
#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */
|
||||
#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */
|
||||
#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */
|
||||
#define STM32_IRQ_DMA_CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA_CH1 */
|
||||
#define STM32_IRQ_DMA_CH23 (STM32_IRQ_EXTINT + 10) /* 0: DMA_CH2_3 and DMA2_CH1_2 */
|
||||
#define STM32_IRQ_DMA_CH4567 (STM32_IRQ_EXTINT + 11) /* 1: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
|
||||
#define STM32_IRQ_ADC_COMP (STM32_IRQ_EXTINT + 12) /* 2: ADC_COMP */
|
||||
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 3: TIM1_BRK_UP_TRG_COM */
|
||||
#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 4: TIM1_CC */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 5: TIM2 */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 6: TIM3 */
|
||||
#define STM32_IRQ_TIM6_DAC (STM32_IRQ_EXTINT + 17) /* 7: TIM6 and DAC */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 8: TIM7 */
|
||||
#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 9: TIM14 */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 0: TIM15 */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 1: TIM16 */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 2: TIM17 */
|
||||
#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 3: I2C1 */
|
||||
#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 4: I2C2 */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 5: SPI1 */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 6: SPI2 */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 7: USART1 */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 8: USART2 */
|
||||
#define STM32_IRQ_USART345678 (STM32_IRQ_EXTINT + 29) /* 9: USART3_4_5_6_7_8 */
|
||||
#define STM32_IRQ_CEC_CAN (STM32_IRQ_EXTINT + 30) /* 0: HDMI CEC and CAN */
|
||||
#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 1: USB */
|
||||
|
||||
#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */
|
||||
|
||||
|
||||
136
arch/arm/include/stm32f0l0/stm32l0_irq.h
Normal file
136
arch/arm/include/stm32f0l0/stm32l0_irq.h
Normal file
@ -0,0 +1,136 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/include/stm32f0l0/stm32_irq.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <arch/stm32f0l0/chip.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
|
||||
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
|
||||
* to handle mapping tables.
|
||||
*
|
||||
* Processor Exceptions (vectors 0-15). These common definitions can be found
|
||||
* in nuttx/arch/arm/include/stm32f0l0/irq.h
|
||||
*/
|
||||
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_EXTINT + 5) /* 5: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_EXTINT + 6) /* 6: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_EXTINT + 7) /* 7: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_EXTINT + 7) /* 7: EXTI Line 5-9 interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_EXTINT + 7) /* 7: EXTI Line 10-15 interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC global interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1 channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP global interrupt */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 13) /* 13: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 14) /* 14: USART4 global interrupt */
|
||||
#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 14) /* 14: USART5 global interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC1 (STM32_IRQ_EXTINT + 17) /* 17: DAC1 global interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 global interrupt */
|
||||
#define STM32_IRQ_RESERVED18 (STM32_IRQ_EXTINT + 18) /* 19: Reserved */
|
||||
#define STM32_IRQ_TIM21 (STM32_IRQ_EXTINT + 20) /* 20: TIM21 global interrupt */
|
||||
#define STM32_IRQ_I2C3 (STM32_IRQ_EXTINT + 21) /* 21: I2C3 global interrupt */
|
||||
#define STM32_IRQ_TIM22 (STM32_IRQ_EXTINT + 22) /* 22: TIM22 global interrupt */
|
||||
#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 global interrupt */
|
||||
#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 global interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 29) /* 29: AES global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 29) /* 29: RNG gloabl interrupt */
|
||||
#define STM32_IRQ_LCD (STM32_IRQ_EXTINT + 30) /* 30: LCD global interrupt */
|
||||
#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB global interrupt */
|
||||
|
||||
#define STM32_IRQ_NEXTINT (32)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H */
|
||||
@ -57,7 +57,7 @@
|
||||
|
||||
/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L0, L1, L4
|
||||
*
|
||||
* F0, L0 and L4 have the additional CSELR register which is used to reamap
|
||||
* F0, L0 and L4 have the additional CSELR register which is used to remap
|
||||
* the DMA requests for each channel.
|
||||
*/
|
||||
|
||||
|
||||
@ -7,373 +7,527 @@ comment "STM32F0/L0 Configuration Options"
|
||||
|
||||
choice
|
||||
prompt "ST STM32F0/L0 Chip Selection"
|
||||
default ARCH_CHIP_STM32F051R8
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0
|
||||
default ARCH_CHIP_STM32L073RZ if !ARCH_CHIP_STM32F0 && ARCH_CHIP_STM32L0
|
||||
depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32F030C6
|
||||
bool "STM32F030C6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F030C8
|
||||
bool "STM32F030C8"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F030CC
|
||||
bool "STM32F030CC"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F030F4
|
||||
bool "STM32F030F4"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F030K6
|
||||
bool "STM32F030K6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F030R8
|
||||
bool "STM32F030R8"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F030RC
|
||||
bool "STM32F030RC"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031C4
|
||||
bool "STM32F031C4"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031C6
|
||||
bool "STM32F031C6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031E6
|
||||
bool "STM32F031E6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031F4
|
||||
bool "STM32F031F4"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031F6
|
||||
bool "STM32F031F6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031G4
|
||||
bool "STM32F031G4"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031G6
|
||||
bool "STM32F031G6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031K4
|
||||
bool "STM32F031K4"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F031K6
|
||||
bool "STM32F031K6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F038C6
|
||||
bool "STM32F038C6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F038E6
|
||||
bool "STM32F038E6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F038F6
|
||||
bool "STM32F038F6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F038G6
|
||||
bool "STM32F038G6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F038K6
|
||||
bool "STM32F038K6"
|
||||
select STM32F0L0_STM32F03X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042C4
|
||||
bool "STM32F042C4"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042C6
|
||||
bool "STM32F042C6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042F4
|
||||
bool "STM32F042F4"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042F6
|
||||
bool "STM32F042F6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042G4
|
||||
bool "STM32F042G4"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042G6
|
||||
bool "STM32F042G6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042K4
|
||||
bool "STM32F042K4"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042K6
|
||||
bool "STM32F042K6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F042T6
|
||||
bool "STM32F042T6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F048C6
|
||||
bool "STM32F048C6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F048G6
|
||||
bool "STM32F048G6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F048T6
|
||||
bool "STM32F048T6"
|
||||
select STM32F0L0_STM32F04X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051C4
|
||||
bool "STM32F051C4"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051C6
|
||||
bool "STM32F051C6"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051C8
|
||||
bool "STM32F051C8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051K4
|
||||
bool "STM32F051K4"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051K6
|
||||
bool "STM32F051K6"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051K8
|
||||
bool "STM32F051K8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051R4
|
||||
bool "STM32F051R4"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051R6
|
||||
bool "STM32F051R6"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051R8
|
||||
bool "STM32F051R8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F051T8
|
||||
bool "STM32F051T8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F058C8
|
||||
bool "STM32F058C8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F058R8
|
||||
bool "STM32F058R8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F058T8
|
||||
bool "STM32F058T8"
|
||||
select STM32F0L0_STM32F05X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F070C6
|
||||
bool "STM32F070C6"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F070CB
|
||||
bool "STM32F070CB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F070F6
|
||||
bool "STM32F070F6"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F070RB
|
||||
bool "STM32F070RB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_VALUELINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F071C8
|
||||
bool "STM32F071C8"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F071CB
|
||||
bool "STM32F071CB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F071RB
|
||||
bool "STM32F071RB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F071V8
|
||||
bool "STM32F071V8"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F071VB
|
||||
bool "STM32F071VB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F072C8
|
||||
bool "STM32F072C8"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F072CB
|
||||
bool "STM32F072CB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F072R8
|
||||
bool "STM32F072R8"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F072RB
|
||||
bool "STM32F072RB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F072V8
|
||||
bool "STM32F072V8"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F072VB
|
||||
bool "STM32F072VB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_USBLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F078CB
|
||||
bool "STM32F078CB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F078RB
|
||||
bool "STM32F078RB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F078VB
|
||||
bool "STM32F078VB"
|
||||
select STM32F0L0_STM32F07X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F091CB
|
||||
bool "STM32F091CB"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F091CC
|
||||
bool "STM32F091CC"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F091RB
|
||||
bool "STM32F091RB"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F091RC
|
||||
bool "STM32F091RC"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F091VB
|
||||
bool "STM32F091VB"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F091VC
|
||||
bool "STM32F091VC"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_ACCESSLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F098CC
|
||||
bool "STM32F098CC"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F098RC
|
||||
bool "STM32F098RC"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32F098VC
|
||||
bool "STM32F098VC"
|
||||
select STM32F0L0_STM32F09X
|
||||
select STM32F0L0_LOWVOLTLINE
|
||||
depends on ARCH_CHIP_STM32F0
|
||||
|
||||
config ARCH_CHIP_STM32L072V8
|
||||
bool "STM32L072V8"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072VB
|
||||
bool "STM32L072VB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072VZ
|
||||
bool "STM32L072VZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072KB
|
||||
bool "STM32L072KB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072KZ
|
||||
bool "STM32L072KZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072CB
|
||||
bool "STM32L072CB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072CZ
|
||||
bool "STM32L072CZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072RB
|
||||
bool "STM32L072RB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L072RZ
|
||||
bool "STM32L072RZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073V8
|
||||
bool "STM32L073V8"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073VB
|
||||
bool "STM32L073VB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073VZ
|
||||
bool "STM32L073VZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073CB
|
||||
bool "STM32L073CB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073CZ
|
||||
bool "STM32L073CZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073RB
|
||||
bool "STM32L073RB"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
config ARCH_CHIP_STM32L073RZ
|
||||
bool "STM32L073RZ"
|
||||
select STM32F0L0_ENERGYLITE
|
||||
depends on ARCH_CHIP_STM32L0
|
||||
|
||||
endchoice # ST STM32F0/L0 Chip Selection
|
||||
|
||||
@ -560,6 +714,10 @@ config STM32F0L0_USBLINE
|
||||
select STM32F0L0_HAVE_SPI3
|
||||
select STM32F0L0_HAVE_USBDEV
|
||||
|
||||
config STM32F0L0_ENERGYLITE
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F0L0_DFU
|
||||
bool "DFU bootloader"
|
||||
default n
|
||||
@ -568,7 +726,6 @@ config STM32F0L0_DFU
|
||||
Configure and position code for use with the STMicro DFU bootloader. Do
|
||||
not select this option if you will load code using JTAG/SWM.
|
||||
|
||||
|
||||
choice
|
||||
prompt "SysTick clock source"
|
||||
default STM32F0L0_SYSTICK_CORECLK
|
||||
|
||||
@ -65,10 +65,18 @@ CMN_CSRCS += up_dumpnvic.c
|
||||
endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = stm32_clockconfig.c stm32_gpio.c stm32_irq.c
|
||||
CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_start.c
|
||||
CHIP_CSRCS = stm32_clockconfig.c stm32_gpio.c stm32_irq.c # stm32_dma_v1.c
|
||||
CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_start.c
|
||||
|
||||
# Configuration-dependent STM32F0xx files
|
||||
# Configuration-dependent STM32F0/L0 files
|
||||
|
||||
ifdef ($(CONFIG_ARCH_CHIP_STM32L0),y
|
||||
CHIP_CSRCS += stm32l0_rcc.c
|
||||
endif
|
||||
|
||||
ifdef ($(CONFIG_STM32F0L0_PWR),y
|
||||
CHIP_CSRCS += stm32_pwr.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
||||
CHIP_CSRCS += stm32_idle.c
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/chip.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
|
||||
@ -1,456 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_dma.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* 12 Channels Total: 7 DMA1 Channels(1-7) (and 5 DMA2 channels (1-5) if STM32F09x) */
|
||||
|
||||
#define DMA1 0
|
||||
#define DMA2 1
|
||||
#define DMA3 2
|
||||
#define DMA4 3
|
||||
#define DMA5 4
|
||||
#define DMA6 5
|
||||
#define DMA7 6
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_CHAN_SHIFT(n) ((n) << 2)
|
||||
#define DMA_CHAN_MASK 0x0f
|
||||
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
|
||||
/* DMA interrupt status register */
|
||||
|
||||
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
|
||||
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
|
||||
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
|
||||
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
|
||||
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
|
||||
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA channel configuration register */
|
||||
|
||||
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
|
||||
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
|
||||
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
|
||||
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
|
||||
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
|
||||
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
|
||||
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
|
||||
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
|
||||
|
||||
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
|
||||
|
||||
/* DMA channel number of data register */
|
||||
|
||||
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to one of several
|
||||
* possible sources/sinks of data. The requests from peripherals assigned to a
|
||||
* channel are multiplexed together before entering the DMA block. This means
|
||||
* that only one request on a given channel can be enabled at once.
|
||||
*
|
||||
* Alternative DMA channel selections are provided with a numeric suffix like _1,
|
||||
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
/* REVISE IT: based on STM32L4 DMA Header */
|
||||
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
|
||||
#define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff))
|
||||
#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF
|
||||
#define DMACHAN_SETTING_CHANNEL_SHIFT (0)
|
||||
#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00
|
||||
#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
|
||||
|
||||
/* ADC */
|
||||
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0)
|
||||
|
||||
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0)
|
||||
|
||||
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0)
|
||||
|
||||
/* AES */
|
||||
|
||||
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6)
|
||||
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6)
|
||||
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6)
|
||||
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_DAC2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5)
|
||||
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
|
||||
|
||||
/* QUADSPI */
|
||||
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 0)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4)
|
||||
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1)
|
||||
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3)
|
||||
|
||||
/* TIM */
|
||||
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7)
|
||||
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4)
|
||||
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
|
||||
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6)
|
||||
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6)
|
||||
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6)
|
||||
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6)
|
||||
|
||||
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5)
|
||||
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5)
|
||||
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7)
|
||||
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7)
|
||||
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
|
||||
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
|
||||
/* USARTs */
|
||||
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2)
|
||||
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
|
||||
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2)
|
||||
|
||||
#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2)
|
||||
|
||||
#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2)
|
||||
#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMA_H */
|
||||
548
arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
Normal file
548
arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
Normal file
@ -0,0 +1,548 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* This is implementation for STM32 DMA IP version 1 - F0, F1, F3, L0, L1, L4 */
|
||||
|
||||
#define HAVE_IP_DMA_V1 1
|
||||
#undef HAVE_IP_DMA_V2
|
||||
|
||||
/* F0, L0, L4 have additional CSELR register */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# define DMA_HAVE_CSELR 1
|
||||
#endif
|
||||
|
||||
/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
|
||||
|
||||
#define DMA1 0
|
||||
#define DMA2 1
|
||||
#define DMA3 2
|
||||
#define DMA4 3
|
||||
#define DMA5 4
|
||||
#define DMA6 5
|
||||
#define DMA7 6
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
# define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
#endif
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET)
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
# define STM32_DMA_CSELR (STM32_DMA2_BASE + STM32_DMA_CSELR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_CHAN_SHIFT(n) ((n) << 2)
|
||||
#define DMA_CHAN_MASK 0x0f
|
||||
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
|
||||
/* DMA interrupt status register */
|
||||
|
||||
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
|
||||
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
|
||||
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
|
||||
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
|
||||
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
|
||||
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA channel configuration register */
|
||||
|
||||
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
|
||||
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
|
||||
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
|
||||
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
|
||||
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
|
||||
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
|
||||
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
|
||||
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
|
||||
|
||||
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
|
||||
|
||||
/* DMA channel number of data register */
|
||||
|
||||
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a channel
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given channel can be enabled at once.
|
||||
*
|
||||
* Alternative DMA channel selections are provided with a numeric suffix like _1,
|
||||
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
# define DMACHAN_SETTING(chan, sel) ((((sel) & 0xff) << 8) | ((chan) & 0xff))
|
||||
# define DMACHAN_SETTING_CHANNEL_MASK 0x00ff
|
||||
# define DMACHAN_SETTING_CHANNEL_SHIFT (0)
|
||||
# define DMACHAN_SETTING_FUNCTION_MASK 0xff00
|
||||
# define DMACHAN_SETTING_FUNCTION_SHIFT (8)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
/* REVISIT: based on STM32L4 DMA Header */
|
||||
|
||||
/* ADC */
|
||||
|
||||
# define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
# define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0)
|
||||
|
||||
# define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
# define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0)
|
||||
|
||||
# define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
# define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0)
|
||||
|
||||
/* AES */
|
||||
|
||||
# define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6)
|
||||
# define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6)
|
||||
# define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6)
|
||||
# define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6)
|
||||
|
||||
/* DAC */
|
||||
|
||||
# define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
# define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
# define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
# define DMACHAN_DAC2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
/* I2C */
|
||||
|
||||
# define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3)
|
||||
# define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5)
|
||||
# define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3)
|
||||
# define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5)
|
||||
|
||||
# define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
|
||||
# define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
|
||||
|
||||
# define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
# define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
|
||||
|
||||
/* QUADSPI */
|
||||
|
||||
# define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5)
|
||||
# define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3)
|
||||
|
||||
/* SPI */
|
||||
|
||||
# define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
|
||||
# define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4)
|
||||
# define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 0)
|
||||
# define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4)
|
||||
|
||||
# define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1)
|
||||
# define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1)
|
||||
|
||||
# define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3)
|
||||
# define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3)
|
||||
|
||||
/* TIM */
|
||||
|
||||
# define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7)
|
||||
# define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7)
|
||||
# define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
|
||||
# define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
# define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
# define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
# define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7)
|
||||
|
||||
# define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
|
||||
# define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
# define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4)
|
||||
# define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
# define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4)
|
||||
|
||||
# define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
# define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
|
||||
# define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
# define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
# define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
|
||||
# define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6)
|
||||
# define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6)
|
||||
# define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6)
|
||||
# define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6)
|
||||
|
||||
# define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5)
|
||||
# define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5)
|
||||
# define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
# define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
# define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
# define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
# define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
|
||||
# define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
# define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
# define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
# define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
# define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7)
|
||||
# define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7)
|
||||
# define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
# define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
# define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
# define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
# define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
|
||||
# define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
# define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
# define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
# define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
|
||||
# define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
# define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
# define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
# define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
|
||||
# define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
# define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
# define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
# define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
|
||||
/* USARTs */
|
||||
|
||||
# define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
|
||||
# define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2)
|
||||
# define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
|
||||
# define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2)
|
||||
|
||||
# define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
|
||||
# define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
|
||||
|
||||
# define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
|
||||
# define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2)
|
||||
|
||||
# define DMACHAN_USART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2)
|
||||
# define DMACHAN_USART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2)
|
||||
|
||||
# define DMACHAN_USART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2)
|
||||
# define DMACHAN_USART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2)
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
|
||||
/* ADC */
|
||||
|
||||
# define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
# define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA1_CHAN2, 0)
|
||||
|
||||
/* AES */
|
||||
|
||||
# define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 11)
|
||||
# define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 11)
|
||||
# define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 11)
|
||||
# define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 11)
|
||||
|
||||
/* DAC */
|
||||
|
||||
# define DMACHAN_DAC1CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 9)
|
||||
# define DMACHAN_DAC1CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 15)
|
||||
|
||||
/* I2C */
|
||||
|
||||
# define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 6)
|
||||
# define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 6)
|
||||
# define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
# define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 6)
|
||||
# define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
# define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
|
||||
# define DMACHAN_I2C3_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 14)
|
||||
# define DMACHAN_I2C3_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 14)
|
||||
# define DMACHAN_I2C3_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 14)
|
||||
# define DMACHAN_I2C3_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 14)
|
||||
|
||||
/* SPI */
|
||||
|
||||
# define DMACHAN_SPI1_RX DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
|
||||
# define DMACHAN_SPI1_TX DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
|
||||
# define DMACHAN_SPI2_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
|
||||
# define DMACHAN_SPI2_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
|
||||
# define DMACHAN_SPI2_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
|
||||
# define DMACHAN_SPI2_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
|
||||
|
||||
/* TIM */
|
||||
|
||||
# define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 8)
|
||||
# define DMACHAN_TIM2_CH2_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 8)
|
||||
# define DMACHAN_TIM2_CH2_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 8)
|
||||
# define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 8)
|
||||
# define DMACHAN_TIM2_CH4_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 8)
|
||||
# define DMACHAN_TIM2_CH4_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 8)
|
||||
# define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 8)
|
||||
# define DMACHAN_TIM6_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 9)
|
||||
# define DMACHAN_TIM7_UP DMACHAN_SETTING(STM32_DMA1_CHAN4, 15)
|
||||
|
||||
/* USART */
|
||||
|
||||
# define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
|
||||
# define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
|
||||
# define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 3)
|
||||
# define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
|
||||
# define DMACHAN_USART2_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 4)
|
||||
# define DMACHAN_USART2_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
# define DMACHAN_USART2_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
|
||||
# define DMACHAN_USART2_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
# define DMACHAN_LPUART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
|
||||
# define DMACHAN_LPUART1_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
# define DMACHAN_LPUART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
# define DMACHAN_LPUART1_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
# define DMACHAN_USART4_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 12)
|
||||
# define DMACHAN_USART4_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 12)
|
||||
# define DMACHAN_USART4_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 12)
|
||||
# define DMACHAN_USART4_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 12)
|
||||
# define DMACHAN_USART5_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 13)
|
||||
# define DMACHAN_USART5_RX_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 13)
|
||||
# define DMACHAN_USART5_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 13)
|
||||
# define DMACHAN_USART5_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 13)
|
||||
|
||||
#else
|
||||
# error "Unknown DMA channel assignments"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H */
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
@ -44,88 +44,12 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_NEXTI 31
|
||||
#define STM32_EXTI_MASK 0xffffffff
|
||||
|
||||
#define STM32_EXTI_BIT(n) (1 << (n))
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI_RTSR (STM32_EXTI_BASE + STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI_FTSR (STM32_EXTI_BASE + STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* EXTI lines > 15 are associated with internal devices: */
|
||||
|
||||
#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
|
||||
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
|
||||
#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */
|
||||
#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */
|
||||
#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */
|
||||
#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */
|
||||
#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */
|
||||
#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */
|
||||
/* EXTI line 24 is reserved (internally held low) */
|
||||
#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */
|
||||
#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */
|
||||
#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */
|
||||
#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */
|
||||
/* EXTI line 29 is reserved (internally held low) */
|
||||
/* EXTI line 30 is reserved (internally held low) */
|
||||
#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Event mask register */
|
||||
|
||||
#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Rising Trigger selection register */
|
||||
|
||||
#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Falling Trigger selection register */
|
||||
|
||||
#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Software interrupt event register */
|
||||
|
||||
#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Pending register */
|
||||
|
||||
#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR_MASK STM32_EXTI_MASK
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_exti.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_exti.h"
|
||||
#else
|
||||
# error "Unrecognized STM32F0/L0 EXTI"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_flash.h
|
||||
*
|
||||
* Copyright (C) 20017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -41,75 +41,14 @@
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_SR_OFFSET 0x000c
|
||||
#define STM32_FLASH_CR_OFFSET 0x0010
|
||||
#define STM32_FLASH_AR_OFFSET 0x0014
|
||||
#define STM32_FLASH_OBR_OFFSET 0x001c
|
||||
#define STM32_FLASH_WRPR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE + STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE + STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE + STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_AR (STM32_FLASHIF_BASE + STM32_FLASH_AR_OFFSET)
|
||||
#define STM32_FLASH_OBR (STM32_FLASHIF_BASE + STM32_FLASH_OBR_OFFSET)
|
||||
#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE + STM32_FLASH_WRPR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY_SHIFT (0)
|
||||
#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
|
||||
#define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */
|
||||
#define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH Prefetch buffer status */
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */
|
||||
#define FLASH_SR_PGERR (1 << 2) /* Bit 2: Programming Error */
|
||||
#define FLASH_SR_WRPRT_ERR (1 << 4) /* Bit 3: Write Protection Error */
|
||||
#define FLASH_SR_EOP (1 << 5) /* Bit 4: End of Operation */
|
||||
|
||||
/* Flash Control Register (CR) */
|
||||
|
||||
#define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */
|
||||
#define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */
|
||||
#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */
|
||||
#define FLASH_CR_OPTPG (1 << 4) /* Bit 4: Option Byte Programming */
|
||||
#define FLASH_CR_OPTER (1 << 5) /* Bit 5: Option Byte Erase */
|
||||
#define FLASH_CR_STRT (1 << 6) /* Bit 6: Start Erase */
|
||||
#define FLASH_CR_LOCK (1 << 7) /* Bit 7: Page Locked or Lock Page */
|
||||
#define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */
|
||||
#define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */
|
||||
#define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */
|
||||
#define FLASH_CR_OBLLAUNCH (1 << 13) /* Bit 13: Force option byte loading */
|
||||
|
||||
/* Flash Option byte register */
|
||||
#define FLASH_OBR_ /* To be provided */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_flash_lock(void);
|
||||
void stm32_flash_unlock(void);
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_flash.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_flash.h"
|
||||
#else
|
||||
# error "Unsupported STM32 FLASH"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H */
|
||||
|
||||
@ -1,9 +1,8 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -38,296 +37,20 @@
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
/* Include the appropriate GPIO definitions for this MCU GPIO version */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_gpio.h"
|
||||
#else
|
||||
# error "Unrecognized STM32F0/L0 GPIO"
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_2MHz (0) /* x0: 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_10MHz (1) /* 01: 10 MHz Medium speed */
|
||||
#define GPIO_OSPEED_50MHz (3) /* 11: 50 MHz High speed */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
@ -47,8 +47,10 @@
|
||||
#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \
|
||||
defined(CONFIG_STM32F0L0_STM32F09X)
|
||||
# include "hardware/stm32f05xf07xf09x_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_memorymap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 memory map"
|
||||
# error "Unsupported STM32F0/L0 memory map"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H */
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
|
||||
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -49,8 +49,10 @@
|
||||
# include "hardware/stm32f07x_pinmap.h"
|
||||
#elif defined(CONFIG_STM32F0L0_STM32F09X)
|
||||
# include "hardware/stm32f09x_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0 pin map"
|
||||
# error "Unsupported STM32F0/L0 pin map"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
@ -34,8 +34,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@ -44,55 +44,13 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_pwr.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_pwr.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 PWR"
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */
|
||||
|
||||
#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
|
||||
#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_PWR_CR (STM32_PWR_BASE + STM32_PWR_CR_OFFSET)
|
||||
#define STM32_PWR_CSR (STM32_PWR_BASE + STM32_PWR_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Power control register */
|
||||
|
||||
#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
|
||||
#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
|
||||
#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */
|
||||
#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
|
||||
#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
|
||||
#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
|
||||
#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT)
|
||||
# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
|
||||
# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
|
||||
# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
|
||||
# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
|
||||
# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
|
||||
# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
|
||||
# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
|
||||
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
|
||||
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
|
||||
|
||||
|
||||
/* Power control/status register */
|
||||
|
||||
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
|
||||
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
|
||||
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
|
||||
#define PWR_CSR_VREFINTRDY (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
|
||||
#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
|
||||
#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
|
||||
#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */
|
||||
#define PWR_CSR_EWUP4 (1 << 11) /* Bit 11: Enable WKUP4 pin */
|
||||
#define PWR_CSR_EWUP5 (1 << 12) /* Bit 12: Enable WKUP5 pin */
|
||||
#define PWR_CSR_EWUP6 (1 << 13) /* Bit 13: Enable WKUP6 pin */
|
||||
#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */
|
||||
#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_PWR_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
@ -44,9 +44,10 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \
|
||||
defined(CONFIG_STM32F0L0_STM32F09X)
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_rcc.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32 RCC"
|
||||
#endif
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
@ -44,348 +44,12 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_ITLINE0 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE0_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE1 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE1_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE2 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE2_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE3 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE3_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE4 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE4_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE5 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE5_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE6 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE6_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE7 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE7_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE8 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE8_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE9 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE9_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE10 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE10_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE11 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE11_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE12 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE12_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE13 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE13_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE14 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE14_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE15 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE15_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE16 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE16_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE17 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE17_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE18 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE18_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE19 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE19_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE20 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE20_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE21 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE21_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE22 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE22_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE23 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE23_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE24 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE24_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE25 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE25_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE26 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE26_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE27 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE27_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE28 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE28_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
|
||||
# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
|
||||
# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
|
||||
# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
|
||||
#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */
|
||||
#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */
|
||||
#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
|
||||
# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
|
||||
# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
|
||||
# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
|
||||
#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */
|
||||
#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
|
||||
#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
|
||||
#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_TIM16_DMARMP2 (1 << 13) /* Bit 13: TIM16 alternate DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_TIM17_DMARMP2 (1 << 14) /* Bit 14: TIM17 alternate DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */
|
||||
#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT)
|
||||
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */
|
||||
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */
|
||||
#define SYSCFG_CFGR1_I2C_PAXFMP_SHIFT (22) /* Bits 22-23: Fast Mode Plus (FM+) driving capability */
|
||||
#define SYSCFG_CFGR1_I2C_PAXFMP_MASK (3 << SYSCFG_CFGR1_I2C_PAXFMP_SHIFT)
|
||||
#define SYSCFG_CFGR1_SPI2_DMARMP (1 << 24) /* Bit 24: SPI2 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_USART2_DMARMP (1 << 25) /* Bit 25: USART2 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_USART3_DMARMP (1 << 26) /* Bit 26: USART3 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_I2C1_DMARMP (1 << 27) /* Bit 27: I2C1 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_TIM1_DMARMP (1 << 28) /* Bit 28: TIM1 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_TIM2_DMARMP (1 << 29) /* Bit 29: TIM2 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_TIM3_DMARMP (1 << 30) /* Bit 30: TIM3 DMA request remapping bit. */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* SYSCFG configuration register 2 */
|
||||
|
||||
#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M0 Hardfault output bit enable */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */
|
||||
#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */
|
||||
#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */
|
||||
|
||||
/* SYSCFG interrupt line 0 status register */
|
||||
|
||||
#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */
|
||||
|
||||
/* SYSCFG interrupt line 1 status register */
|
||||
|
||||
#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */
|
||||
#define SYSCFG_ITLINE1_VDDIO2 (1 << 0) /* Bit 1: VDDIO2 supply monitoring interrupt request pending (EXTI line 31) */
|
||||
|
||||
/* SYSCFG interrupt line 2 status register */
|
||||
|
||||
#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */
|
||||
#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */
|
||||
#define SYSCFG_ITLINE2_RTC_ALRA (1 << 2) /* Bit 2: RTC Alarm interrupt request pending (EXTI line 17) */
|
||||
|
||||
/* SYSCFG interrupt line 3 status register */
|
||||
|
||||
#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 4 status register */
|
||||
|
||||
#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */
|
||||
#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: Clock recovery system interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 5 status register */
|
||||
|
||||
#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */
|
||||
#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 6 status register */
|
||||
|
||||
#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */
|
||||
#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 7 status register */
|
||||
|
||||
#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 8 status register */
|
||||
|
||||
#define SYSCFG_ITLINE8_TCS_MCE (1 << 0) /* Bit 0: Touch sensing controller max count error interrupt request pending */
|
||||
#define SYSCFG_ITLINE8_TCS_EOA (1 << 1) /* Bit 1: Touch sensing controller end of acquisition interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 9 status register */
|
||||
|
||||
#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 10 status register */
|
||||
|
||||
#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA2_CH1 (1 << 2) /* Bit 0: DMA2 channel 1 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA2_CH2 (1 << 3) /* Bit 1: DMA2 channel 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 11 status register */
|
||||
|
||||
#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 0) /* Bit 0: DMA1 channel 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 1) /* Bit 1: DMA1 channel 5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 2) /* Bit 2: DMA1 channel 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 3) /* Bit 3: DMA1 channel 7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 4) /* Bit 4: DMA2 channel 3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 5) /* Bit 5: DMA2 channel 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 6) /* Bit 6: DMA2 channel 5 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 12 status register */
|
||||
|
||||
#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */
|
||||
#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */
|
||||
#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 13 status register */
|
||||
|
||||
#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 14 status register */
|
||||
|
||||
#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 15 status register */
|
||||
|
||||
#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 16 status register */
|
||||
|
||||
#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 17 status register */
|
||||
|
||||
#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 18 status register */
|
||||
|
||||
#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 19 status register */
|
||||
|
||||
#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 20 status register */
|
||||
|
||||
#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 21 status register */
|
||||
|
||||
#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 22 status register */
|
||||
|
||||
#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 23 status register */
|
||||
|
||||
#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */
|
||||
|
||||
/* SYSCFG interrupt line 24 status register */
|
||||
|
||||
#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 25 status register */
|
||||
|
||||
#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 26 status register */
|
||||
|
||||
#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 27 status register */
|
||||
|
||||
#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 28 status register */
|
||||
|
||||
#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 29 status register */
|
||||
|
||||
#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART5 (1 << 2) /* Bit 2: USART5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART6 (1 << 3) /* Bit 3: USART6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART7 (1 << 4) /* Bit 4: USART7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART8 (1 << 5) /* Bit 5: USART8 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 30 status register */
|
||||
|
||||
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
|
||||
#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_syscfg.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_syscfg.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 SYSCFG"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
@ -42,275 +42,14 @@
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
# include "hardware/stm32f0_uart.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
# include "hardware/stm32l0_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32F0/L0 UART"
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M0 (1 << 12) /* Bit 12: word length */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
|
||||
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
|
||||
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
|
||||
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
|
||||
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
|
||||
#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
|
||||
USART_CR1_TCIE|USART_CR1_TXEIE|USART_CR1_PEIE|USART_CR1_CMIE| \
|
||||
USART_CR1_RTOIE|USART_CR1_EOBIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
|
||||
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
|
||||
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
|
||||
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
|
||||
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
|
||||
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
|
||||
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
|
||||
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
|
||||
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
|
||||
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
|
||||
#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
|
||||
#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
|
||||
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
|
||||
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
|
||||
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
|
||||
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
|
||||
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
|
||||
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
|
||||
/* Request Register */
|
||||
|
||||
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */
|
||||
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send Break */
|
||||
#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */
|
||||
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */
|
||||
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */
|
||||
|
||||
/* Interrupt and Status register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 9: CTS Flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 10: Receiver timeout Flag */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 11: End of block Flag */
|
||||
#define USART_ISR_ABRE (1 << 13) /* Bit 12: Auto baud rate Error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 14: Auto baud rate Flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 15: Busy Flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 16: Character match Flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 17: Send break Flag */
|
||||
#define USART_ISR_RWU (1 << 19) /* Bit 18: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 19: Wakeup from Stop mode Flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */
|
||||
|
||||
/* ICR */
|
||||
|
||||
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
|
||||
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
|
||||
|
||||
/* Receive Data register */
|
||||
|
||||
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
|
||||
|
||||
/* Transmit Data register */
|
||||
|
||||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
|
||||
|
||||
@ -124,13 +124,13 @@
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H */
|
||||
|
||||
@ -144,16 +144,16 @@
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_FLOAT | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN14)
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN14)
|
||||
|
||||
/* I2S */
|
||||
|
||||
|
||||
131
arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h
Normal file
131
arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h
Normal file
@ -0,0 +1,131 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_NEXTI 31
|
||||
#define STM32_EXTI_MASK 0xffffffff
|
||||
|
||||
#define STM32_EXTI_BIT(n) (1 << (n))
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI_RTSR (STM32_EXTI_BASE + STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI_FTSR (STM32_EXTI_BASE + STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* EXTI lines > 15 are associated with internal devices: */
|
||||
|
||||
#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
|
||||
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
|
||||
#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */
|
||||
#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */
|
||||
#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */
|
||||
#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */
|
||||
#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */
|
||||
#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */
|
||||
/* EXTI line 24 is reserved (internally held low) */
|
||||
#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */
|
||||
#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */
|
||||
#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */
|
||||
#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */
|
||||
/* EXTI line 29 is reserved (internally held low) */
|
||||
/* EXTI line 30 is reserved (internally held low) */
|
||||
#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Event mask register */
|
||||
|
||||
#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Rising Trigger selection register */
|
||||
|
||||
#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Falling Trigger selection register */
|
||||
|
||||
#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Software interrupt event register */
|
||||
|
||||
#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Pending register */
|
||||
|
||||
#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR_MASK STM32_EXTI_MASK
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H */
|
||||
108
arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
Normal file
108
arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
Normal file
@ -0,0 +1,108 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_SR_OFFSET 0x000c
|
||||
#define STM32_FLASH_CR_OFFSET 0x0010
|
||||
#define STM32_FLASH_AR_OFFSET 0x0014
|
||||
#define STM32_FLASH_OBR_OFFSET 0x001c
|
||||
#define STM32_FLASH_WRPR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE + STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE + STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE + STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_AR (STM32_FLASHIF_BASE + STM32_FLASH_AR_OFFSET)
|
||||
#define STM32_FLASH_OBR (STM32_FLASHIF_BASE + STM32_FLASH_OBR_OFFSET)
|
||||
#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE + STM32_FLASH_WRPR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY_SHIFT (0)
|
||||
#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
|
||||
#define FLASH_ACR_PRTFBE (1 << 4) /* Bit 4: FLASH prefetch enable */
|
||||
#define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH Prefetch buffer status */
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */
|
||||
#define FLASH_SR_PGERR (1 << 2) /* Bit 2: Programming Error */
|
||||
#define FLASH_SR_WRPRT_ERR (1 << 4) /* Bit 3: Write Protection Error */
|
||||
#define FLASH_SR_EOP (1 << 5) /* Bit 4: End of Operation */
|
||||
|
||||
/* Flash Control Register (CR) */
|
||||
|
||||
#define FLASH_CR_PG (1 << 0) /* Bit 0: Program Page */
|
||||
#define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */
|
||||
#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */
|
||||
#define FLASH_CR_OPTPG (1 << 4) /* Bit 4: Option Byte Programming */
|
||||
#define FLASH_CR_OPTER (1 << 5) /* Bit 5: Option Byte Erase */
|
||||
#define FLASH_CR_STRT (1 << 6) /* Bit 6: Start Erase */
|
||||
#define FLASH_CR_LOCK (1 << 7) /* Bit 7: Page Locked or Lock Page */
|
||||
#define FLASH_CR_OPTWRE (1 << 9) /* Bit 8: Option Bytes Write Enable */
|
||||
#define FLASH_CR_ERRIE (1 << 10) /* Bit 10: Error Interrupt Enable */
|
||||
#define FLASH_CR_EOPIE (1 << 12) /* Bit 12: End of Program Interrupt Enable */
|
||||
#define FLASH_CR_OBLLAUNCH (1 << 13) /* Bit 13: Force option byte loading */
|
||||
|
||||
/* Flash Option byte register */
|
||||
|
||||
#define FLASH_OBR_ /* To be provided */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H */
|
||||
336
arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
Normal file
336
arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
Normal file
@ -0,0 +1,336 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#undef STM32_GPIO_VERY_LOW_SPEED /* No very low speed operation */
|
||||
#define STM32_HAVE_PORTF 1 /* If STM32_NPORTS > 5, then have GPIOF */
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_2MHz (0) /* x0: 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_10MHz (1) /* 01: 10 MHz Medium speed */
|
||||
#define GPIO_OSPEED_50MHz (3) /* 11: 50 MHz High speed */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H */
|
||||
97
arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
Normal file
97
arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
Normal file
@ -0,0 +1,97 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
|
||||
#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_PWR_CR (STM32_PWR_BASE + STM32_PWR_CR_OFFSET)
|
||||
#define STM32_PWR_CSR (STM32_PWR_BASE + STM32_PWR_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Power control register */
|
||||
|
||||
#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
|
||||
#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
|
||||
#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */
|
||||
#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
|
||||
#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
|
||||
#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
|
||||
#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT)
|
||||
# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
|
||||
# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
|
||||
# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
|
||||
# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
|
||||
# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
|
||||
# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
|
||||
# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
|
||||
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
|
||||
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
|
||||
|
||||
/* Power control/status register */
|
||||
|
||||
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
|
||||
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
|
||||
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
|
||||
#define PWR_CSR_VREFINTRDY (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
|
||||
#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
|
||||
#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
|
||||
#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */
|
||||
#define PWR_CSR_EWUP4 (1 << 11) /* Bit 11: Enable WKUP4 pin */
|
||||
#define PWR_CSR_EWUP5 (1 << 12) /* Bit 12: Enable WKUP5 pin */
|
||||
#define PWR_CSR_EWUP6 (1 << 13) /* Bit 13: Enable WKUP6 pin */
|
||||
#define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */
|
||||
#define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H */
|
||||
391
arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
Normal file
391
arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
Normal file
@ -0,0 +1,391 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_ITLINE0_OFFSET 0x0080 /* SYSCFG interrupt line 0 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE1_OFFSET 0x0084 /* SYSCFG interrupt line 1 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE2_OFFSET 0x0088 /* SYSCFG interrupt line 2 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE3_OFFSET 0x008c /* SYSCFG interrupt line 3 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE4_OFFSET 0x0090 /* SYSCFG interrupt line 4 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE5_OFFSET 0x0094 /* SYSCFG interrupt line 5 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE6_OFFSET 0x0098 /* SYSCFG interrupt line 6 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE7_OFFSET 0x009c /* SYSCFG interrupt line 7 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE8_OFFSET 0x00a0 /* SYSCFG interrupt line 8 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE9_OFFSET 0x00a4 /* SYSCFG interrupt line 9 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE10_OFFSET 0x00a8 /* SYSCFG interrupt line 10 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE11_OFFSET 0x00ac /* SYSCFG interrupt line 11 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE12_OFFSET 0x00b0 /* SYSCFG interrupt line 12 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE13_OFFSET 0x00b4 /* SYSCFG interrupt line 13 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE14_OFFSET 0x00b8 /* SYSCFG interrupt line 14 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE15_OFFSET 0x00bc /* SYSCFG interrupt line 15 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE16_OFFSET 0x00c0 /* SYSCFG interrupt line 16 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE17_OFFSET 0x00c4 /* SYSCFG interrupt line 17 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE18_OFFSET 0x00c8 /* SYSCFG interrupt line 18 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE19_OFFSET 0x00cc /* SYSCFG interrupt line 19 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE20_OFFSET 0x00d0 /* SYSCFG interrupt line 20 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE21_OFFSET 0x00d4 /* SYSCFG interrupt line 21 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE22_OFFSET 0x00d8 /* SYSCFG interrupt line 22 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE23_OFFSET 0x00dc /* SYSCFG interrupt line 23 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE24_OFFSET 0x00e0 /* SYSCFG interrupt line 24 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE25_OFFSET 0x00e4 /* SYSCFG interrupt line 25 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE26_OFFSET 0x00e8 /* SYSCFG interrupt line 26 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE27_OFFSET 0x00ec /* SYSCFG interrupt line 27 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE28_OFFSET 0x00f0 /* SYSCFG interrupt line 28 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* SYSCFG interrupt line 29 status register (STM32F09x) */
|
||||
#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* SYSCFG interrupt line 30 status register (STM32F09x) */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_ITLINE0 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE0_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE1 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE1_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE2 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE2_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE3 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE3_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE4 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE4_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE5 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE5_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE6 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE6_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE7 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE7_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE8 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE8_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE9 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE9_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE10 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE10_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE11 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE11_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE12 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE12_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE13 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE13_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE14 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE14_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE15 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE15_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE16 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE16_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE17 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE17_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE18 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE18_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE19 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE19_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE20 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE20_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE21 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE21_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE22 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE22_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE23 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE23_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE24 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE24_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE25 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE25_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE26 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE26_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE27 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE27_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE28 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE28_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET)
|
||||
#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
|
||||
# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
|
||||
# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
|
||||
# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
|
||||
#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) /* Bit 4: PA11 and PA12 remapping bit for small packages */
|
||||
#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */
|
||||
#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
|
||||
# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
|
||||
# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
|
||||
# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
|
||||
#define SYSCFG_CFGR1_ADC_DMARMP (1 << 8) /* Bit 8: ADC DMA remapping bit. Only STM32F03x/F04x/F05x/F07x */
|
||||
#define SYSCFG_CFGR1_USART1_TXDMARMP (1 << 9) /* Bit 9: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
|
||||
#define SYSCFG_CFGR1_USART1_RXDMARMP (1 << 10) /* Bit 10: USART1_TX_DMA request remapping bit. Only STM32F03x/F04x/F05x/F07x */
|
||||
#define SYSCFG_CFGR1_TIM16_DMARMP (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_TIM17_DMARMP (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_TIM16_DMARMP2 (1 << 13) /* Bit 13: TIM16 alternate DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_TIM17_DMARMP2 (1 << 14) /* Bit 14: TIM17 alternate DMA request remapping bit */
|
||||
#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT (16) /* Bits 16-19: Fast Mode Plus (FM+) driving capability */
|
||||
#define SYSCFG_CFGR1_I2C_PBXFMP_MASK (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT)
|
||||
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */
|
||||
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */
|
||||
#define SYSCFG_CFGR1_I2C_PAXFMP_SHIFT (22) /* Bits 22-23: Fast Mode Plus (FM+) driving capability */
|
||||
#define SYSCFG_CFGR1_I2C_PAXFMP_MASK (3 << SYSCFG_CFGR1_I2C_PAXFMP_SHIFT)
|
||||
#define SYSCFG_CFGR1_SPI2_DMARMP (1 << 24) /* Bit 24: SPI2 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_USART2_DMARMP (1 << 25) /* Bit 25: USART2 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_USART3_DMARMP (1 << 26) /* Bit 26: USART3 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_I2C1_DMARMP (1 << 27) /* Bit 27: I2C1 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_TIM1_DMARMP (1 << 28) /* Bit 28: TIM1 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_TIM2_DMARMP (1 << 29) /* Bit 29: TIM2 DMA request remapping bit. */
|
||||
#define SYSCFG_CFGR1_TIM3_DMARMP (1 << 30) /* Bit 30: TIM3 DMA request remapping bit. */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* SYSCFG configuration register 2 */
|
||||
|
||||
#define SYSCFG_CFGR2_LOCKUPLOCK (1 << 0) /* Bit 0: Cortex-M0 Hardfault output bit enable */
|
||||
#define SYSCFG_CFGR2_SRAM_PARITYLOCK (1 << 1) /* Bit 1: RAM parity lock */
|
||||
#define SYSCFG_CFGR2_PVDLOCK (1 << 2) /* Bit 2: PVD lock enable */
|
||||
#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /* Bit 8: SRAM parity error */
|
||||
|
||||
/* SYSCFG interrupt line 0 status register */
|
||||
|
||||
#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: Window Watchdog interrupt pending flag */
|
||||
|
||||
/* SYSCFG interrupt line 1 status register */
|
||||
|
||||
#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */
|
||||
#define SYSCFG_ITLINE1_VDDIO2 (1 << 0) /* Bit 1: VDDIO2 supply monitoring interrupt request pending (EXTI line 31) */
|
||||
|
||||
/* SYSCFG interrupt line 2 status register */
|
||||
|
||||
#define SYSCFG_ITLINE2_RTC_WAKEUP (1 << 0) /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */
|
||||
#define SYSCFG_ITLINE2_RTC_TSTAMP (1 << 1) /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */
|
||||
#define SYSCFG_ITLINE2_RTC_ALRA (1 << 2) /* Bit 2: RTC Alarm interrupt request pending (EXTI line 17) */
|
||||
|
||||
/* SYSCFG interrupt line 3 status register */
|
||||
|
||||
#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) /* Bit 0: Flash interface interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 4 status register */
|
||||
|
||||
#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: Reset and clock control interrupt request pending */
|
||||
#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: Clock recovery system interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 5 status register */
|
||||
|
||||
#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI line 0 interrupt request pending */
|
||||
#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI line 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 6 status register */
|
||||
|
||||
#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI line 2 interrupt request pending */
|
||||
#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI line 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 7 status register */
|
||||
|
||||
#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI line 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI line 5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI line 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI line 7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI line 8 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI line 9 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI line 10 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI line 11 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI line 12 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI line 13 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */
|
||||
#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 8 status register */
|
||||
|
||||
#define SYSCFG_ITLINE8_TCS_MCE (1 << 0) /* Bit 0: Touch sensing controller max count error interrupt request pending */
|
||||
#define SYSCFG_ITLINE8_TCS_EOA (1 << 1) /* Bit 1: Touch sensing controller end of acquisition interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 9 status register */
|
||||
|
||||
#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 channel 1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 10 status register */
|
||||
|
||||
#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 channel 2 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 channel 3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA2_CH1 (1 << 2) /* Bit 0: DMA2 channel 1 interrupt request pending */
|
||||
#define SYSCFG_ITLINE10_DMA2_CH2 (1 << 3) /* Bit 1: DMA2 channel 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 11 status register */
|
||||
|
||||
#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 0) /* Bit 0: DMA1 channel 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 1) /* Bit 1: DMA1 channel 5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 2) /* Bit 2: DMA1 channel 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 3) /* Bit 3: DMA1 channel 7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 4) /* Bit 4: DMA2 channel 3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 5) /* Bit 5: DMA2 channel 4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 6) /* Bit 6: DMA2 channel 5 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 12 status register */
|
||||
|
||||
#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC interrupt request pending */
|
||||
#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: Comparator 1 interrupt request pending */
|
||||
#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: Comparator 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 13 status register */
|
||||
|
||||
#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation interrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 triggerinterrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update interrupt request pending */
|
||||
#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 14 status register */
|
||||
|
||||
#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) /* Bit 0: TIM1 capture compare interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 15 status register */
|
||||
|
||||
#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: Timer 2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 16 status register */
|
||||
|
||||
#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: Timer 3 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 17 status register */
|
||||
|
||||
#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: Timer 6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 18 status register */
|
||||
|
||||
#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: Timer 7 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 19 status register */
|
||||
|
||||
#define SYSCFG_ITLINE19_TIM14 (1 << 0) /* Bit 0: Timer 14 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 20 status register */
|
||||
|
||||
#define SYSCFG_ITLINE20_TIM15 (1 << 0) /* Bit 0: Timer 15 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 21 status register */
|
||||
|
||||
#define SYSCFG_ITLINE21_TIM16 (1 << 0) /* Bit 0: Timer 16 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 22 status register */
|
||||
|
||||
#define SYSCFG_ITLINE22_TIM17 (1 << 0) /* Bit 0: Timer 17 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 23 status register */
|
||||
|
||||
#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */
|
||||
|
||||
/* SYSCFG interrupt line 24 status register */
|
||||
|
||||
#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 25 status register */
|
||||
|
||||
#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 26 status register */
|
||||
|
||||
#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 27 status register */
|
||||
|
||||
#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 28 status register */
|
||||
|
||||
#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 29 status register */
|
||||
|
||||
#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART4 (1 << 1) /* Bit 1: USART4 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART5 (1 << 2) /* Bit 2: USART5 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART6 (1 << 3) /* Bit 3: USART6 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART7 (1 << 4) /* Bit 4: USART7 interrupt request pending */
|
||||
#define SYSCFG_ITLINE29_USART8 (1 << 5) /* Bit 5: USART8 interrupt request pending */
|
||||
|
||||
/* SYSCFG interrupt line 30 status register */
|
||||
|
||||
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
|
||||
#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H */
|
||||
316
arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
Normal file
316
arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
Normal file
@ -0,0 +1,316 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
|
||||
*
|
||||
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Alan Carvalho de Assis <acassis@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
|
||||
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
|
||||
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
|
||||
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
|
||||
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
|
||||
#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | USART_CR1_RXNEIE | \
|
||||
USART_CR1_TCIE | USART_CR1_TXEIE | \
|
||||
USART_CR1_PEIE | USART_CR1_CMIE| \
|
||||
USART_CR1_RTOIE | USART_CR1_EOBIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
|
||||
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
|
||||
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
|
||||
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
|
||||
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
|
||||
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
|
||||
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
|
||||
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
|
||||
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
|
||||
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
|
||||
#define USART_CR3_SCARCNT_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
|
||||
#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT)
|
||||
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
|
||||
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
|
||||
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
|
||||
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
|
||||
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
|
||||
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
|
||||
/* Request Register */
|
||||
|
||||
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */
|
||||
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send Break */
|
||||
#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */
|
||||
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */
|
||||
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */
|
||||
|
||||
/* Interrupt and Status register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 9: CTS Flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 10: Receiver timeout Flag */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 11: End of block Flag */
|
||||
#define USART_ISR_ABRE (1 << 13) /* Bit 12: Auto baud rate Error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 14: Auto baud rate Flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 15: Busy Flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 16: Character match Flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 17: Send break Flag */
|
||||
#define USART_ISR_RWU (1 << 19) /* Bit 18: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 19: Wakeup from Stop mode Flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */
|
||||
|
||||
/* ICR */
|
||||
|
||||
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
|
||||
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
|
||||
|
||||
/* Receive Data register */
|
||||
|
||||
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
|
||||
|
||||
/* Transmit Data register */
|
||||
|
||||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
|
||||
131
arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h
Normal file
131
arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h
Normal file
@ -0,0 +1,131 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32_exti.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_NEXTI 31 /* REVISIT: Taken from the F0, probably incorrect */
|
||||
#define STM32_EXTI_MASK 0xffffffff
|
||||
|
||||
#define STM32_EXTI_BIT(n) (1 << (n))
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_EXTI_IMR (STM32_EXTI_BASE + STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI_EMR (STM32_EXTI_BASE + STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI_RTSR (STM32_EXTI_BASE + STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI_FTSR (STM32_EXTI_BASE + STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI_SWIER (STM32_EXTI_BASE + STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI_PR (STM32_EXTI_BASE + STM32_EXTI_PR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* EXTI lines > 15 are associated with internal devices: */
|
||||
/* REVISIT: Taken from the F0, probably incorrect */
|
||||
|
||||
#define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
|
||||
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
|
||||
#define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB wake up event */
|
||||
#define EXTI_RTC_TAMPER (1 << 19) /* EXTI line 19 is connected to the RTC Tamper and TimeStamp events */
|
||||
#define EXTI_RTC_WAKEUP (1 << 20) /* EXTI line 20 is connected to the RTC Wakeup event */
|
||||
#define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the COMP1 (comparator) output */
|
||||
#define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the COMP2 (comparator) output */
|
||||
#define EXTI_I2C1 (1 << 23) /* EXTI line 23 is connected to the I2C1 wakeup */
|
||||
/* EXTI line 24 is reserved (internally held low) */
|
||||
#define EXTI_USART1 (1 << 25) /* EXTI line 25 is connected to the USART1 wakeup */
|
||||
#define EXTI_USART2 (1 << 26) /* EXTI line 26 is connected to the USART2 wakeup */
|
||||
#define EXTI_CEC (1 << 27) /* EXTI line 27 is connected to the CEC wakeup */
|
||||
#define EXTI_USART3 (1 << 28) /* EXTI line 28 is connected to the USART3 wakeup */
|
||||
/* EXTI line 29 is reserved (internally held low) */
|
||||
/* EXTI line 30 is reserved (internally held low) */
|
||||
#define EXTI_VDDIO2 (1 << 31) /* EXTI line 31 is connected to the Vddio2 supply comparator */
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Event mask register */
|
||||
|
||||
#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Rising Trigger selection register */
|
||||
|
||||
#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Falling Trigger selection register */
|
||||
|
||||
#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Software interrupt event register */
|
||||
|
||||
#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Pending register */
|
||||
|
||||
#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR_MASK STM32_EXTI_MASK
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H */
|
||||
117
arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
Normal file
117
arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
Normal file
@ -0,0 +1,117 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/hardware/stm32l0_flash.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_PECR_OFFSET 0x0004
|
||||
#define STM32_FLASH_PDKEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_PEKEYR_OFFSET 0x000c
|
||||
#define STM32_FLASH_PRGKEYR_OFFSET 0x0010
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x0014
|
||||
#define STM32_FLASH_SR_OFFSET 0x0018
|
||||
#define STM32_FLASH_OBR_OFFSET 0x001c
|
||||
#define STM32_FLASH_WRPR1_OFFSET 0x0020
|
||||
#define STM32_FLASH_WRPR2_OFFSET 0x0080
|
||||
#define STM32_FLASH_WRPR3_OFFSET 0x0084
|
||||
#define STM32_FLASH_WRPR4_OFFSET 0x0088
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_PECR (STM32_FLASHIF_BASE + STM32_FLASH_PECR_OFFSET)
|
||||
#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PDKEYR_OFFSET)
|
||||
#define STM32_FLASH_PEKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PEKEYR_OFFSET)
|
||||
#define STM32_FLASH_PRGKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PRGKEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE + STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_OBR (STM32_FLASHIF_BASE + STM32_FLASH_OBR_OFFSET)
|
||||
#define STM32_FLASH_WRPR1 (STM32_FLASHIF_BASE + STM32_FLASH_WRPR1_OFFSET)
|
||||
#define STM32_FLASH_WRPR2 (STM32_FLASHIF_BASE + STM32_FLASH_WRPR2_OFFSET)
|
||||
#define STM32_FLASH_WRPR3 (STM32_FLASHIF_BASE + STM32_FLASH_WRPR3_OFFSET)
|
||||
#define STM32_FLASH_WRPR4 (STM32_FLASHIF_BASE + STM32_FLASH_WRPR4_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY (1 << 0) /* Bit 0: Latency */
|
||||
#define FLASH_ACR_PRFTEN (1 << 1) /* Bit 1: Prefetch enable */
|
||||
#define FLASH_ACR_ACC64 (1 << 2) /* Bit 2: 64-bit access */
|
||||
#define FLASH_ACR_SLEEP_PD (1 << 3) /* Bit 3: Flash mode during Sleep */
|
||||
#define FLASH_ACR_RUN_PD (1 << 4) /* Bit 4: Flash mode during Run */
|
||||
|
||||
/* Program/Erase Control Register (PECR) */
|
||||
|
||||
#define FLASH_PECR_PELOCK (1 << 0) /* Bit 0: PECR and data EEPROM lock */
|
||||
#define FLASH_PECR_PRGLOCK (1 << 1) /* Bit 1: Program memory lock */
|
||||
#define FLASH_PECR_OPTLOCK (1 << 2) /* Bit 2: Option bytes block lock */
|
||||
#define FLASH_PECR_PROG (1 << 3) /* Bit 3: Program memory selection */
|
||||
#define FLASH_PECR_DATA (1 << 4) /* Bit 4: Data EEPROM selection */
|
||||
#define FLASH_PECR_FTDW (1 << 8) /* Bit 8: Fixed time data write for Byte, Half Word and Word programming */
|
||||
#define FLASH_PECR_ERASE (1 << 9) /* Bit 9: Page or Double Word erase mode */
|
||||
#define FLASH_PECR_FPRG (1 << 10) /* Bit 10: Half Page/Double Word programming mode */
|
||||
#define FLASH_PECR_PARALLBANK (1 << 15) /* Bit 15: Parallel bank mode */
|
||||
#define FLASH_PECR_EOPIE (1 << 16) /* Bit 16: End of programming interrupt enable */
|
||||
#define FLASH_PECR_ERRIE (1 << 17) /* Bit 17: Error interrupt enable */
|
||||
#define FLASH_PECR_OBL_LAUNCH (1 << 18) /* Bit 18: Launch the option byte loading */
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */
|
||||
#define FLASH_SR_EOP (1 << 1) /* Bit 1: End of operation */
|
||||
#define FLASH_SR_ENDHV (1 << 2) /* Bit 2: End of high voltage */
|
||||
#define FLASH_SR_READY (1 << 3) /* Bit 3: Flash memory module ready after low power mode */
|
||||
#define FLASH_SR_WRPERR (1 << 8) /* Bit 8: Write protection error */
|
||||
#define FLASH_SR_PGAERR (1 << 9) /* Bit 9: Programming alignment error */
|
||||
#define FLASH_SR_SIZERR (1 << 10) /* Bit 10: Size error */
|
||||
#define FLASH_SR_OPTVERR (1 << 11) /* Bit 11: Option validity error */
|
||||
#define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */
|
||||
#define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H */
|
||||
345
arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
Normal file
345
arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
Normal file
@ -0,0 +1,345 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation (400KHz) */
|
||||
#undef STM32_HAVE_PORTF /* If STM32_NPORTS > 5, then have GPIOH */
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 6
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NPORTS > 7
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_400KHz (0) /* 400 kHz Very low speed */
|
||||
#define GPIO_OSPEED_2MHz (1) /* 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_10MHz (2) /* 10 MHz Medium speed */
|
||||
#define GPIO_OSPEED_40MHz (3) /* 40 MHz High speed */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H */
|
||||
130
arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
Normal file
130
arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
Normal file
@ -0,0 +1,130 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* STM32L0 Address Blocks ***********************************************************/
|
||||
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
/* 0x60000000-0xdfffffff: Reserved */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M0 block */
|
||||
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
|
||||
/* Code Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x07ffffff: Aliased boot memory */
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: Program FLASH memory */
|
||||
#define STM32_EEPROM_BASE 0x08080000 /* 0x08080000-0x08083fff: Data FLASH memory */
|
||||
#define STM32_SYSMEM_BASE 0x1ff00000 /* 0x1ff00000-0x1ff00fff: System memory */
|
||||
/* 0x1ff01000-0x1fff7fff: Reserved */
|
||||
#define STM32_OPTION_BASE 0x1ff80000 /* 0x1fffc000-0x1ff8001f: Option bytes */
|
||||
/* 0x1ff80020-0x1fffffff: Reserved */
|
||||
|
||||
/* Peripheral Base Addresses ********************************************************/
|
||||
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007c03: APB1 */
|
||||
/* 0x40007c04-0x4000ffff: Reserved */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40013bff: APB2 */
|
||||
/* 0x40013c00-0x4001ffff: Reserved */
|
||||
#define STM32_AHB_BASE 0x40020000 /* 0x40020000-0xa0000fff: AHB */
|
||||
/* 0xa0001000-0x4fffffff: Reserved */
|
||||
#define STM32_IOPORT_BASE 0x50000000 /* 0x50000000-0x50001fff: IOPORT */
|
||||
|
||||
/* APB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
|
||||
#define STM32_LCD_BASE 0x40002400 /* 0x40002400-0x400027ff LCD */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
|
||||
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2 */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
|
||||
#define STM32_LPUART1_BASE 0x40004800 /* 0x40004800-0x40004bff LPUART1 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
|
||||
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */
|
||||
#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
|
||||
#define STM32_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff PWR */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
|
||||
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */
|
||||
#define STM32_I2C3_BASE 0x40007800 /* 0x40007800-0x40007bff I2C3 */
|
||||
#define STM32_LPTIM1_BASE 0x40007C00 /* 0x40007c00-0x40007fff LPTIM1 */
|
||||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */
|
||||
#define STM32_TIM21_BASE 0x40010800 /* 0x40010800-0x40010bff TIM21 */
|
||||
#define STM32_TIM22_BASE 0x40014000 /* 0x40014000-0x400117ff TIM22 */
|
||||
#define STM32_FIREWALL_BASE 0x4001c000 /* 0x4001c000-0x400113ff Firewall */
|
||||
#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
|
||||
#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */
|
||||
|
||||
/* AHB Base Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff DMA */
|
||||
#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff RCC */
|
||||
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff Flash memory interface */
|
||||
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff CRC */
|
||||
#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff TSC */
|
||||
#define STM32_RNG_BASE 0x40025000 /* 0x40025000-0x400253ff RNG */
|
||||
#define STM32_AES_BASE 0x40026000 /* 0x40026000-0x400263ff AES */
|
||||
|
||||
/* IOPORT Base Addresses ************************************************************/
|
||||
|
||||
#define STM32_GPIOA_BASE 0x50000000 /* 0x50000000-0x500003ff GPIO Port A */
|
||||
#define STM32_GPIOB_BASE 0x50000400 /* 0x50000400-0x500007ff GPIO Port B */
|
||||
#define STM32_GPIOC_BASE 0x50000800 /* 0x50000800-0x50000bff GPIO Port C */
|
||||
#define STM32_GPIOD_BASE 0x50000c00 /* 0x50000c00-0x50000fff GPIO Port D */
|
||||
#define STM32_GPIOE_BASE 0x50001000 /* 0x50001000-0x500013ff GPIO Port E */
|
||||
#define STM32_GPIOH_BASE 0x50001c00 /* 0x50001c00-0x50001fff GPIO Port H */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H */
|
||||
341
arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
Normal file
341
arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
Normal file
@ -0,0 +1,341 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions.
|
||||
*
|
||||
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
|
||||
* Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file. For example, if
|
||||
* CAN1_RX connects vis PA11 on some board, then the following definitions should
|
||||
* appear in the board.h header file for that board:
|
||||
*
|
||||
* #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
*
|
||||
* The driver will then automatically configre PB6 as the I2C1 SCL pin.
|
||||
*/
|
||||
|
||||
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
||||
* Additional effort is required to select specific GPIO options such as frequency,
|
||||
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
|
||||
* pins in this file.
|
||||
*/
|
||||
|
||||
#define GPIO_BOOT1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN2)
|
||||
|
||||
/* ADC
|
||||
*
|
||||
* ADC_IN16 is internal temperature sensor
|
||||
* ADC_IN17 is internal Vrefint
|
||||
*/
|
||||
|
||||
#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
|
||||
#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
|
||||
#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
|
||||
#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
|
||||
#define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
|
||||
#define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
|
||||
#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define GPIO_DAC_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN14)
|
||||
#define GPIO_I2C2_SMBA (GPIO_ALT | GPIO_AF5 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN12)
|
||||
#define GPIO_I2C3_SCL (GPIO_ALT | GPIO_AF7 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN0)
|
||||
#define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN1)
|
||||
#define GPIO_I2C3_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN9)
|
||||
|
||||
/* LCD */
|
||||
|
||||
#define GPIO_LCD_COM0 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8)
|
||||
#define GPIO_LCD_COM1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9)
|
||||
#define GPIO_LCD_COM2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10)
|
||||
#define GPIO_LCD_COM3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_LCD_COM4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN10)
|
||||
#define GPIO_LCD_COM5 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN11)
|
||||
#define GPIO_LCD_COM6 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN12)
|
||||
#define GPIO_LCD_COM7 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN2)
|
||||
#define GPIO_LCD_SEG0 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_LCD_SEG1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_LCD_SEG2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_LCD_SEG3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6)
|
||||
#define GPIO_LCD_SEG4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_LCD_SEG5 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_LCD_SEG6 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN1)
|
||||
#define GPIO_LCD_SEG7 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_LCD_SEG8 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_LCD_SEG9 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_LCD_SEG10 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_LCD_SEG11 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_LCD_SEG12 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12)
|
||||
#define GPIO_LCD_SEG13 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_LCD_SEG14 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN14)
|
||||
#define GPIO_LCD_SEG15 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN15)
|
||||
#define GPIO_LCD_SEG16 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_LCD_SEG17 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_LCD_SEG18 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN0)
|
||||
#define GPIO_LCD_SEG19 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN1)
|
||||
#define GPIO_LCD_SEG20 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_LCD_SEG21 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
|
||||
#define GPIO_LCD_SEG22 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN4)
|
||||
#define GPIO_LCD_SEG23 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN5)
|
||||
#define GPIO_LCD_SEG24 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN6)
|
||||
#define GPIO_LCD_SEG25 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN7)
|
||||
#define GPIO_LCD_SEG26 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN8)
|
||||
#define GPIO_LCD_SEG27 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN9)
|
||||
#define GPIO_LCD_SEG28 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN10)
|
||||
#define GPIO_LCD_SEG29 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN11)
|
||||
#define GPIO_LCD_SEG30 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN12)
|
||||
#define GPIO_LCD_SEG31 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN2)
|
||||
|
||||
/* Clocking */
|
||||
|
||||
#define GPIO_MCO_1 (GPIO_ALT | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN8)
|
||||
#define GPIO_MCO_2 (GPIO_ALT | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
|
||||
#define GPIO_OSC32_IN (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN14)
|
||||
#define GPIO_OSC32_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN15)
|
||||
#define GPIO_OSC_IN (GPIO_ALT | GPIO_AF0 | GPIO_PORTH | GPIO_PIN0)
|
||||
#define GPIO_OSC_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTH | GPIO_PIN1)
|
||||
|
||||
/* Event outputs */
|
||||
|
||||
#define GPIO_PA1_EVENT_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_PA6_EVENT_OUT (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6)
|
||||
#define GPIO_PA7_EVENT_OUT (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_PA8_EVENT_OUT (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8)
|
||||
#define GPIO_PA11_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11)
|
||||
#define GPIO_PA12_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_PA15_EVENT_OUT (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_PB0_EVENT_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_PB3_EVENT_OUT (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_PB9_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_PB11_EVENT_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_PB12_EVENT_OUT (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN12)
|
||||
#define GPIO_PC0_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN0)
|
||||
#define GPIO_PC1_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN1)
|
||||
#define GPIO_PC4_EVENT_OUT (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN4)
|
||||
#define GPIO_PE0_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN0)
|
||||
#define GPIO_PE1_EVENT_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN1)
|
||||
|
||||
/* RTC */
|
||||
|
||||
#define GPIO_RTC_OUT (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14)
|
||||
#define GPIO_RTC_REFIN (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN15)
|
||||
#define GPIO_RTC_TAMP1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13)
|
||||
#define GPIO_RTC_TS (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN11)
|
||||
#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
|
||||
#define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_SPI1_MISO_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN14)
|
||||
#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_SPI1_MOSI_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN15)
|
||||
#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
|
||||
#define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN12)
|
||||
#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
|
||||
#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN13)
|
||||
#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
|
||||
#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN3)
|
||||
#define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
|
||||
#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN4)
|
||||
#define GPIO_SPI2_MOSI_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN3)
|
||||
#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
|
||||
#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN0)
|
||||
#define GPIO_SPI2_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN1)
|
||||
#define GPIO_SPI2_SCK_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN9)
|
||||
#define GPIO_TIM2_CH1_ETR_4 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN5)
|
||||
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH2OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN12)
|
||||
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_TIM2_CH4OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN12)
|
||||
|
||||
#define GPIO_TIM3_CH1IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH1IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1IN_4 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN3)
|
||||
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN6)
|
||||
#define GPIO_TIM3_CH1OUT_4 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN3)
|
||||
#define GPIO_TIM3_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH2IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2IN_4 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN7)
|
||||
#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN8)
|
||||
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN8)
|
||||
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN9)
|
||||
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN1)
|
||||
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT | GPIO_PUSHPULL | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN9)
|
||||
#define GPIO_TIM3_ETR_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTD | GPIO_PIN2)
|
||||
#define GPIO_TIM3_ETR_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PORTE | GPIO_PIN2)
|
||||
|
||||
/* TODO: TIM21, TIM22 */
|
||||
|
||||
/* USART */
|
||||
|
||||
#define GPIO_USART1_CK_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN8)
|
||||
#define GPIO_USART1_CK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_USART1_CTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11)
|
||||
#define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_USART1_RTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_USART1_RTS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6)
|
||||
|
||||
#define GPIO_USART2_CK_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN4)
|
||||
#define GPIO_USART2_CK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN7)
|
||||
#define GPIO_USART2_CTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_USART2_CTS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN3)
|
||||
#define GPIO_USART2_RTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN5)
|
||||
|
||||
#define GPIO_USART2_CK (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12)
|
||||
#define GPIO_USART2_RTS (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15)
|
||||
#define GPIO_USART2_CTS (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN11)
|
||||
#define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN9)
|
||||
#define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10)
|
||||
#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN8)
|
||||
|
||||
#define GPIO_USART5_CK_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_USART5_CK_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTE | GPIO_PIN7)
|
||||
#define GPIO_USART5_RTS_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_USART5_RTS_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTE | GPIO_PIN7)
|
||||
#define GPIO_USART5_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN2)
|
||||
#define GPIO_USART5_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN11)
|
||||
#define GPIO_USART5_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART5_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF2 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN12)
|
||||
#define GPIO_USART5_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN10)
|
||||
#define GPIO_USART5_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN4)
|
||||
|
||||
/* TODO: USB */
|
||||
|
||||
/* TODO: LPTIM */
|
||||
|
||||
/* TODO: LPUART */
|
||||
|
||||
/* TODO: LCD */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H */
|
||||
102
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
Normal file
102
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
Normal file
@ -0,0 +1,102 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32l0_pwr.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */
|
||||
#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_PWR_CR (STM32_PWR_BASE+STM32_PWR_CR_OFFSET)
|
||||
#define STM32_PWR_CSR (STM32_PWR_BASE+STM32_PWR_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Power control register */
|
||||
|
||||
#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
|
||||
#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
|
||||
#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */
|
||||
#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
|
||||
#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
|
||||
|
||||
#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
|
||||
#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT)
|
||||
# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */
|
||||
# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */
|
||||
# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */
|
||||
# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */
|
||||
# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */
|
||||
# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */
|
||||
# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */
|
||||
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
|
||||
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
|
||||
#define PWR_CR_ULP (1 << 9) /* Bit 9: Ultralow power mode */
|
||||
#define PWR_CR_FWU (1 << 10) /* Bit 10: Fast wake-up */
|
||||
#define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */
|
||||
# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */
|
||||
# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */
|
||||
# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) PLL VCO Max = 24MHz */
|
||||
#define PWR_CR_DSEEKOFF (1 << 13) /* Bit 13: Deepsleep mode with non-volatile memory kept off */
|
||||
#define PWR_CR_LPRUN (1 << 14) /* Bit 14: Low power run mode */
|
||||
|
||||
/* Power control/status register */
|
||||
|
||||
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
|
||||
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
|
||||
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
|
||||
#define PWR_CSR_VREFINTRDYF (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
|
||||
#define PWR_CSR_VOSF (1 << 4) /* Bit 4: Voltage Scaling select flag */
|
||||
#define PWR_CSR_REGLPF (1 << 5) /* Bit 5: Regulator LP flag */
|
||||
#define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
|
||||
#define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
|
||||
#define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H */
|
||||
554
arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
Normal file
554
arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
Normal file
@ -0,0 +1,554 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0008 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x000C /* Clock configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0010 /* Clock Source Interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x0014 /* Clock Source Interrupt Flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0018 /* Clock Source Interrupt Clear register */
|
||||
#define STM32_RCC_IOPRSTR_OFFSET 0x001C /* GPIO reset register */
|
||||
#define STM32_RCC_AHBRSTR_OFFSET 0x0020 /* AHB peripheral reset register */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR_OFFSET 0x0028 /* APB1 Peripheral reset register */
|
||||
#define STM32_RCC_IOPENR_OFFSET 0x002C /* GPIO clock enable register */
|
||||
#define STM32_RCC_AHBENR_OFFSET 0x0030 /* AHB Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0034 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x0038 /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_IOPSMEN_OFFSET 0x003C /* GPIO clock enable in Sleep mode register */
|
||||
#define STM32_RCC_AHBSMENR_OFFSET 0x0040 /* AHB peripheral clock enable in Sleep mode register */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0044 /* APB2 peripheral clock enable in Sleep mode register */
|
||||
#define STM32_RCC_APB1SMENR_OFFSET 0x0048 /* APB1 peripheral clock enable in Sleep mode register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x004C /* Clock configuration register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0050 /* Control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_IOPRSTR (STM32_RCC_BASE+STM32_RCC_IOPRSTR_OFFSET)
|
||||
#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
|
||||
#define STM32_RCC_IOPENR (STM32_RCC_BASE+STM32_RCC_IOPENR_OFFSET)
|
||||
#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_IOPSMEN (STM32_RCC_BASE+STM32_RCC_IOPSMEN_OFFSET)
|
||||
#define STM32_RCC_AHBSMENR (STM32_RCC_BASE+STM32_RCC_AHBSMENR_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR (STM32_RCC_BASE+STM32_RCC_APB1SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal high speed clock enable */
|
||||
#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal high speed clock enable for some IP kernels */
|
||||
#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal high speed clock ready flag */
|
||||
#define RCC_CR_HSIDIV (1 << 3) /* Bit 3: Internal high speed clock divider enable */
|
||||
#define RCC_CR_HSIDIVF (1 << 4) /* Bit 4: Internal high speed clock divider flag */
|
||||
#define RCC_CR_HSIOUTEN (1 << 5) /* Bit 5: Internal high speed clock output enable */
|
||||
/* Bits 6-7: Reserved */
|
||||
#define RCC_CR_MSION (1 << 8) /* Bit 8: MSI clock enable */
|
||||
#define RCC_CR_MSIRDY (1 << 9) /* Bit 9: MSI clock ready flag */
|
||||
/* Bits 10-15: Reserved */
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External high speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External high speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External high speed clock bypass */
|
||||
#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: Clock security system on HSE enable */
|
||||
#define RCC_CR_RTCPRE_SHIFT (20) /* Bits 20-21: RTC prescaler */
|
||||
#define RCC_CR_RTCPRE_MASK (3 << RCC_CR_RTCPRE_SHIFT)
|
||||
/* Bits 22-23: Reserved */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
/* Bits 26-27: Reserved */
|
||||
|
||||
#define RCC_CR_RSTVAL 0x00000b00
|
||||
|
||||
/* Internal clock sources calibration register */
|
||||
|
||||
#define RCC_ICSCR_HSICAL_SHIFT (0) /* Bits 0-7: Internal high speed clock calibration */
|
||||
#define RCC_ICSCR_HSICAL_MASK (0xff << RCC_ICSCR_HSICAL_SHIFT)
|
||||
#define RCC_ICSCR_HSITRIM_SHIFT (8) /* Bits 8-12: High speed internal clock trimming */
|
||||
#define RCC_ICSCR_HSITRIM_MASK (0x1f << RCC_ICSCR_HSITRIM_SHIFT)
|
||||
#define RCC_ICSCR_MSIRANGE_SHIFT (13) /* Bits 13-15: MSI clock ranges */
|
||||
#define RCC_ICSCR_MSIRANGE_MASK (7 << RCC_ICSCR_MSIRANGE_SHIFT)
|
||||
# define RCC_ICSCR_MSIRANGE_0 (0 << RCC_ICSCR_MSIRANGE_SHIFT) /* 000: Range 0 around 65.536 kHz */
|
||||
# define RCC_ICSCR_MSIRANGE_1 (1 << RCC_ICSCR_MSIRANGE_SHIFT) /* 001: Range 1 around 131.072 kHz */
|
||||
# define RCC_ICSCR_MSIRANGE_2 (2 << RCC_ICSCR_MSIRANGE_SHIFT) /* 010: Range 2 around 262.144 kHz */
|
||||
# define RCC_ICSCR_MSIRANGE_3 (3 << RCC_ICSCR_MSIRANGE_SHIFT) /* 011: Range 3 around 524.288 kHz */
|
||||
# define RCC_ICSCR_MSIRANGE_4 (4 << RCC_ICSCR_MSIRANGE_SHIFT) /* 100: Range 4 around 1.048 MHz */
|
||||
# define RCC_ICSCR_MSIRANGE_5 (5 << RCC_ICSCR_MSIRANGE_SHIFT) /* 101: Range 5 around 2.097 MHz (reset value) */
|
||||
# define RCC_ICSCR_MSIRANGE_6 (6 << RCC_ICSCR_MSIRANGE_SHIFT) /* 110: Range 6 around 4.194 MHz */
|
||||
#define RCC_ICSCR_MSICAL_SHIFT (16) /* Bits 16-23: MSI clock calibration */
|
||||
#define RCC_ICSCR_MSICAL_MASK (0xff << RCC_ICSCR_MSICAL_SHIFT)
|
||||
#define RCC_ICSCR_MSITRIM_SHIFT (24) /* Bits 24-31: MSI clock trimming */
|
||||
#define RCC_ICSCR_MSITRIM_MASK (0xff << RCC_ICSCR_MSITRIM_SHIFT)
|
||||
|
||||
#define RCC_ICSR_RSTVAL 0x0000b000
|
||||
|
||||
/* Clock recovery RC register */
|
||||
|
||||
#define RCC_CRRCR_HSI48ON (0) /* Bits 0: 48MHz HSI clock enable */
|
||||
#define RCC_CRRCR_HSI48RDY (1) /* Bits 1: 48MHz HSI clock ready */
|
||||
#define RCC_CRRCR_HSI48DIV6EN (2) /* Bits 2: 48MHz HSI clock divided by 6 output enable */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define RCC_CRRCR_HSI48CAL_SHIFT (8) /* Bits 8: 48 MHz HSI reset calibration */
|
||||
#define RCC_CRRCR_HSI48CAL_MASK (0xff << RCC_CRRCR_HSI48CAL_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_MSI (0 << RCC_CFGR_SW_SHIFT) /* 00: MSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 01: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 10: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 11: PLL selected as system clock */
|
||||
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: MSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 10: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 11: PLL used as system clock */
|
||||
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
|
||||
/* Bits 14: Reserved */
|
||||
#define RCC_CFGR_STOPWUCK (15) /* Bits 15: */
|
||||
#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */
|
||||
/* Bit 17: Reserved */
|
||||
#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 18-21: PLL Multiplication Factor */
|
||||
#define RCC_CFGR_PLLMUL_MASK (15 << RCC_CFGR_PLLMUL_SHIFT)
|
||||
# define RCC_CFGR_PLLMUL_CLKx3 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL clock entry x 3 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx4 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL clock entry x 4 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx6 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL clock entry x 6 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx8 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL clock entry x 8 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx12 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL clock entry x 12 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx16 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL clock entry x 16 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx24 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL clock entry x 24 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx32 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL clock entry x 32 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx48 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL clock entry x 48 */
|
||||
#define RCC_CFGR_PLLDIV_SHIFT (22) /* Bits 22-23: PLL output division */
|
||||
#define RCC_CFGR_PLLDIV_MASK (3 << RCC_CFGR_PLLDIV_SHIFT)
|
||||
# define RCC_CFGR_PLLDIV_2 (1 << RCC_CFGR_PLLDIV_SHIFT) /* 01: PLL clock output = PLLVCO / 2 */
|
||||
# define RCC_CFGR_PLLDIV_3 (2 << RCC_CFGR_PLLDIV_SHIFT) /* 10: PLL clock output = PLLVCO / 3 */
|
||||
# define RCC_CFGR_PLLDIV_4 (3 << RCC_CFGR_PLLDIV_SHIFT) /* 11: PLL clock output = PLLVCO / 4 */
|
||||
#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-27: Microcontroller clock output selection */
|
||||
#define RCC_CFGR_MCOSEL_MASK (7 << RCC_CFGR_MCOSEL_SHIFT)
|
||||
# define RCC_CFGR_MCOSEL_DISABLED (0 << RCC_CFGR_MCOSEL_SHIFT) /* 0000: MCO output disabled, no clock on MCO */
|
||||
# define RCC_CFGR_MCOSEL_SYSCLK (1 << RCC_CFGR_MCOSEL_SHIFT) /* 0001: SYSCLK clock selected */
|
||||
# define RCC_CFGR_MCOSEL_HSICLK (2 << RCC_CFGR_MCOSEL_SHIFT) /* 0010: HSI16 oscillator clock selected */
|
||||
# define RCC_CFGR_MCOSEL_MSICLK (3 << RCC_CFGR_MCOSEL_SHIFT) /* 0011: MSI oscillator clock selected */
|
||||
# define RCC_CFGR_MCOSEL_HSECLK (4 << RCC_CFGR_MCOSEL_SHIFT) /* 0100: HSE oscillator clock selected */
|
||||
# define RCC_CFGR_MCOSEL_PLLCLK (5 << RCC_CFGR_MCOSEL_SHIFT) /* 0101: PLL clock selected */
|
||||
# define RCC_CFGR_MCOSEL_LSICLK (6 << RCC_CFGR_MCOSEL_SHIFT) /* 0110: LSI oscillator clock selected */
|
||||
# define RCC_CFGR_MCOSEL_LSECLK (7 << RCC_CFGR_MCOSEL_SHIFT) /* 0111: LSE oscillator clock selected */
|
||||
# define RCC_CFGR_MCOSEL_HSI48CLK (8 << RCC_CFGR_MCOSEL_SHIFT) /* 1000: HSI48 oscillator clock selected */
|
||||
#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */
|
||||
#define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT)
|
||||
# define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: MCO is divided by 1 */
|
||||
# define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: MCO is divided by 2 */
|
||||
# define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: MCO is divided by 4 */
|
||||
# define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: MCO is divided by 8 */
|
||||
# define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: MCO is divided by 16 */
|
||||
/* Bit 31: Reserved */
|
||||
#define RCC_CFGR_RESET 0x00000000
|
||||
|
||||
/* Clock Source Interrupt enable register */
|
||||
|
||||
#define RCC_CIER_LSIRDYF (1 << 0) /* Bit 0: LSI ready interrupt flag */
|
||||
#define RCC_CIER_LSERDYF (1 << 1) /* Bit 1: LSE ready interrupt flag */
|
||||
#define RCC_CIER_HSIRDYF (1 << 2) /* Bit 2: HSI16 ready interrupt flag */
|
||||
#define RCC_CIER_HSERDYF (1 << 3) /* Bit 3: HSE ready interrupt flag */
|
||||
#define RCC_CIER_PLLRDYF (1 << 4) /* Bit 4: PLL ready interrupt flag */
|
||||
#define RCC_CIER_MSIRDYF (1 << 5) /* Bit 5: MSI ready interrupt flag */
|
||||
#define RCC_CIER_HSI48RDYF (1 << 6) /* Bit 6: HSI48 ready interrupt flag */
|
||||
#define RCC_CIER_CSSLSE (1 << 7) /* Bit 7: LSE CSS interrupt flag */
|
||||
|
||||
/* Clock Source Interrupt Flag register */
|
||||
|
||||
#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI ready interrupt flag */
|
||||
#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE ready interrupt flag */
|
||||
#define RCC_CIFR_HSIRDYF (1 << 2) /* Bit 2: HSI16 ready interrupt flag */
|
||||
#define RCC_CIFR_HSERDYF (1 << 3) /* Bit 3: HSE ready interrupt flag */
|
||||
#define RCC_CIFR_PLLRDYF (1 << 4) /* Bit 4: PLL ready interrupt flag */
|
||||
#define RCC_CIFR_MSIRDYF (1 << 5) /* Bit 5: MSI ready interrupt flag */
|
||||
#define RCC_CIFR_HSI48RDYF (1 << 6) /* Bit 6: HSI48 ready interrupt flag */
|
||||
#define RCC_CIFR_CSSLSE (1 << 7) /* Bit 7: LSE CSS interrupt flag */
|
||||
|
||||
/* Clock Source Interrupt Clear register */
|
||||
|
||||
#define RCC_CICR_LSIRDYF (1 << 0) /* Bit 0: LSI ready interrupt flag */
|
||||
#define RCC_CICR_LSERDYF (1 << 1) /* Bit 1: LSE ready interrupt flag */
|
||||
#define RCC_CICR_HSIRDYF (1 << 2) /* Bit 2: HSI16 ready interrupt flag */
|
||||
#define RCC_CICR_HSERDYF (1 << 3) /* Bit 3: HSE ready interrupt flag */
|
||||
#define RCC_CICR_PLLRDYF (1 << 4) /* Bit 4: PLL ready interrupt flag */
|
||||
#define RCC_CICR_MSIRDYF (1 << 5) /* Bit 5: MSI ready interrupt flag */
|
||||
#define RCC_CICR_HSI48RDYF (1 << 6) /* Bit 6: HSI48 ready interrupt flag */
|
||||
#define RCC_CICR_CSSLSE (1 << 7) /* Bit 7: LSE CSS interrupt flag */
|
||||
|
||||
/* GPIO reset register */
|
||||
|
||||
#define RCC_IOPRSTR_IOPARST (1 << 0) /* Bit 0: IO port A reset */
|
||||
#define RCC_IOPRSTR_IOPBRST (1 << 1) /* Bit 0: IO port B reset */
|
||||
#define RCC_IOPRSTR_IOPCRST (1 << 2) /* Bit 0: IO port C reset */
|
||||
#define RCC_IOPRSTR_IOPDRST (1 << 3) /* Bit 0: IO port D reset */
|
||||
#define RCC_IOPRSTR_IOPERST (1 << 4) /* Bit 0: IO port E reset */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define RCC_IOPRSTR_IOPHRST (1 << 7) /* Bit 0: IO port H reset */
|
||||
|
||||
/* AHB peripheral reset register */
|
||||
|
||||
#define RCC_AHBRSTR_DMARST (0) /* Bit 0: DMA reset */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define RCC_AHBRSTR_MIFRST (8) /* Bit 8: Memory interface reset */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBRSTR_CRCRST (12) /* Bit 12: Memory interface reset */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBRSTR_TSCRST (12) /* Bit 12: Touch sensing reset */
|
||||
/* Bits 17-19: Reserved */
|
||||
#define RCC_AHBRSTR_RNGRST (20) /* Bit 20: Random number generator module reset */
|
||||
/* Bits 21-23: Reserved */
|
||||
#define RCC_AHBRSTR_CRYPRST (24) /* Bit 24: Crypto module reset */
|
||||
/* Bits 25-31: Reserved */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: System configuration controller reset */
|
||||
/* Bit 1: Reserved */
|
||||
#define RCC_APB2RSTR_TIM21RST (1 << 2) /* Bit 2: TIM21 timer reset */
|
||||
/* Bits 3-4: Reserved */
|
||||
#define RCC_APB2RSTR_TIM22RST (1 << 5) /* Bit 5: TIM21 timer reset */
|
||||
/* Bits 6-8: Reserved */
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 interface reset */
|
||||
/* Bits 10-11: Reserved */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
|
||||
/* Bit 13: Reserved */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
|
||||
/* Bits 15-21: Reserved */
|
||||
#define RCC_APB2RSTR_DBGRST (1 << 22) /* Bit 22: DBG reset */
|
||||
/* Bits 23-31: Reserved */
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */
|
||||
/* Bits 6-8: Reserved */
|
||||
#define RCC_APB1RSTR_LCDRST (1 << 9) /* Bit 9: LCD reset */
|
||||
/* Bit 10: Reserved */
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window Watchdog reset */
|
||||
/* Bits 12-13: Reserved */
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
|
||||
/* Bits 15-16: Reserved */
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: UART 5 reset */
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
|
||||
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
|
||||
/* Bits 24-26: Reserved */
|
||||
#define RCC_APB1RSTR_CRSRST (1 << 27) /* Bit 27: Clock recovery system reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
|
||||
#define RCC_APB1RSTR_I2C3RST (1 << 30) /* Bit 30: I2C3 reset */
|
||||
#define RCC_APB1RSTR_LPTIM1RST (1 << 31) /* Bit 31: Low-power timer reset */
|
||||
|
||||
/* GPIO clock enable register */
|
||||
|
||||
#define RCC_IOPENR_IOPAEN (1 << 0) /* Bit 0: IO port A clock enable */
|
||||
#define RCC_IOPENR_IOPBEN (1 << 1) /* Bit 0: IO port B clock enable */
|
||||
#define RCC_IOPENR_IOPCEN (1 << 2) /* Bit 0: IO port C clock enable */
|
||||
#define RCC_IOPENR_IOPDEN (1 << 3) /* Bit 0: IO port D clock enable */
|
||||
#define RCC_IOPENR_IOPEEN (1 << 4) /* Bit 0: IO port E clock enable */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define RCC_IOPENR_IOPHEN (1 << 7) /* Bit 0: IO port H clock enable */
|
||||
|
||||
/* AHB Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHBENR_DMAEN (0) /* Bit 0: DMA clock enable */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define RCC_AHBENR_MIFEN (8) /* Bit 8: Memory interface clock enable */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBENR_CRCEN (12) /* Bit 12: Memory interface clock enable */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBENR_TSCEN (12) /* Bit 12: Touch sensing clock enable */
|
||||
/* Bits 17-19: Reserved */
|
||||
#define RCC_AHBENR_RNGEN (20) /* Bit 20: Random number generator module clock enable */
|
||||
/* Bits 21-23: Reserved */
|
||||
#define RCC_AHBENR_CRYPEN (24) /* Bit 24: Crypto module clock enable */
|
||||
/* Bits 25-31: Reserved */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller clock enable */
|
||||
/* Bit 1: Reserved */
|
||||
#define RCC_APB2ENR_TIM21EN (1 << 2) /* Bit 2: TIM21 timer clock enable */
|
||||
/* Bits 3-4: Reserved */
|
||||
#define RCC_APB2ENR_TIM22EN (1 << 5) /* Bit 5: TIM21 timer clock enable */
|
||||
/* Bits 6-8: Reserved */
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 9) /* Bit 9: ADC1 interface clock enable */
|
||||
/* Bits 10-11: Reserved */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */
|
||||
/* Bit 13: Reserved */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */
|
||||
/* Bits 15-21: Reserved */
|
||||
#define RCC_APB2ENR_DBGEN (1 << 22) /* Bit 22: DBG clock enable */
|
||||
/* Bits 23-31: Reserved */
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 clock enable */
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 clock enable */
|
||||
/* Bits 6-8: Reserved */
|
||||
#define RCC_APB1ENR_LCDEN (1 << 9) /* Bit 9: LCD clock enable */
|
||||
/* Bit 10: Reserved */
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window Watchdog clock enable */
|
||||
/* Bits 12-13: Reserved */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */
|
||||
/* Bits 15-16: Reserved */
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
|
||||
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
|
||||
/* Bits 24-26: Reserved */
|
||||
#define RCC_APB1ENR_CRSEN (1 << 27) /* Bit 27: Clock recovery system clock enable */
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
|
||||
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
|
||||
#define RCC_APB1ENR_I2C3EN (1 << 30) /* Bit 30: I2C3 clock enable */
|
||||
#define RCC_APB1ENR_LPTIM1EN (1 << 31) /* Bit 31: Low-power timer clock enable */
|
||||
|
||||
/* GPIO clock enable in Sleep mode register */
|
||||
|
||||
#define RCC_IOPSMENR_IOPASMEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPBSMEN (1 << 1) /* Bit 0: IO port B clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPCSMEN (1 << 2) /* Bit 0: IO port C clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPDSMEN (1 << 3) /* Bit 0: IO port D clock enable during Sleep mode */
|
||||
#define RCC_IOPSMENR_IOPESMEN (1 << 4) /* Bit 0: IO port E clock enable during Sleep mode */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define RCC_IOPSMENR_IOPHSMEN (1 << 7) /* Bit 0: IO port H clock enable during Sleep mode */
|
||||
|
||||
/* AHB peripheral clock enable in Sleep mode register */
|
||||
|
||||
#define RCC_AHBSMENR_DMASMEN (0) /* Bit 0: DMA clock enable in Sleep mode */
|
||||
/* Bits 1-7: Reserved */
|
||||
#define RCC_AHBSMENR_MIFSMEN (8) /* Bit 8: Memory interface clock enable in Sleep mode */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_AHBSMENR_CRCSMEN (12) /* Bit 12: Memory interface clock enable in Sleep mode */
|
||||
/* Bits 13-15: Reserved */
|
||||
#define RCC_AHBSMENR_TSCSMEN (12) /* Bit 12: Touch sensing clock enable in Sleep mode */
|
||||
/* Bits 17-19: Reserved */
|
||||
#define RCC_AHBSMENR_RNGSMEN (20) /* Bit 20: Random number generator module clock enable in Sleep mode */
|
||||
/* Bits 21-23: Reserved */
|
||||
#define RCC_AHBSMENR_CRYPSMEN (24) /* Bit 24: Crypto module clock enable in Sleep mode */
|
||||
/* Bits 25-31: Reserved */
|
||||
|
||||
/* APB2 peripheral clock enable in Sleep mode register */
|
||||
|
||||
#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) /* Bit 0: System configuration controller clock enable in Sleep mode */
|
||||
/* Bit 1: Reserved */
|
||||
#define RCC_APB2SMENR_TIM21SMEN (1 << 2) /* Bit 2: TIM21 timer clock enable in Sleep mode */
|
||||
/* Bits 3-4: Reserved */
|
||||
#define RCC_APB2SMENR_TIM22SMEN (1 << 5) /* Bit 5: TIM21 timer clock enable in Sleep mode */
|
||||
/* Bits 6-8: Reserved */
|
||||
#define RCC_APB2SMENR_ADC1SMEN (1 << 9) /* Bit 9: ADC1 interface clock enable in Sleep mode */
|
||||
/* Bits 10-11: Reserved */
|
||||
#define RCC_APB2SMENR_SPI1SMEN (1 << 12) /* Bit 12: SPI 1 clock enable in Sleep mode */
|
||||
/* Bit 13: Reserved */
|
||||
#define RCC_APB2SMENR_USART1SMEN (1 << 14) /* Bit 14: USART1 clock enable in Sleep mode */
|
||||
/* Bits 15-21: Reserved */
|
||||
#define RCC_APB2SMENR_DBGSMEN (1 << 22) /* Bit 22: DBG clock enable in Sleep mode */
|
||||
/* Bits 23-31: Reserved */
|
||||
|
||||
/* APB1 peripheral clock enable in Sleep mode register */
|
||||
|
||||
#define RCC_APB1SMENR_TIM2SMEN (1 << 0) /* Bit 0: Timer 2 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_TIM3SMEN (1 << 1) /* Bit 1: Timer 3 clock enable in Sleep mode */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_APB1SMENR_TIM6SMEN (1 << 4) /* Bit 4: Timer 6 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_TIM7SMEN (1 << 5) /* Bit 5: Timer 7 clock enable in Sleep mode */
|
||||
/* Bits 6-8: Reserved */
|
||||
#define RCC_APB1SMENR_LCDSMEN (1 << 9) /* Bit 9: LCD clock enable in Sleep mode */
|
||||
/* Bits 10: Reserved */
|
||||
#define RCC_APB1SMENR_WWDGSMEN (1 << 11) /* Bit 11: Window Watchdog clock enable in Sleep mode */
|
||||
/* Bits 12-13: Reserved */
|
||||
#define RCC_APB1SMENR_SPI2SMEN (1 << 14) /* Bit 14: SPI 2 clock enable in Sleep mode */
|
||||
/* Bits 15-16: Reserved */
|
||||
#define RCC_APB1SMENR_USART2SMEN (1 << 17) /* Bit 17: USART 2 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_USART3SMEN (1 << 18) /* Bit 18: USART 3 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_UART4SMEN (1 << 19) /* Bit 19: UART 4 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_UART5SMEN (1 << 20) /* Bit 20: UART 5 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_I2C1SMEN (1 << 21) /* Bit 21: I2C 1 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_I2C2SMEN (1 << 22) /* Bit 22: I2C 2 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_USBSMEN (1 << 23) /* Bit 23: USB clock enable in Sleep mode */
|
||||
/* Bits 24-26: Reserved */
|
||||
#define RCC_APB1SMENR_CRSSMEN (1 << 27) /* Bit 27: Clock recovery system clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_PWRSMEN (1 << 28) /* Bit 28: Power interface clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_DACSMEN (1 << 29) /* Bit 29: DAC interface clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_I2C3SMEN (1 << 30) /* Bit 30: I2C3 clock enable in Sleep mode */
|
||||
#define RCC_APB1SMENR_LPTIM1SMEN (1 << 31) /* Bit 31: Low-power timer clock enable in Sleep mode */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CCIPR_USART1SEL_SHIFT (0) /* Bits 0-1: USART1 clock source selection */
|
||||
#define RCC_CCIPR_USART1SEL_MASK (3 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_APB (0 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_SYSCLK (1 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_HSI16 (2 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART1SEL_LSE (3 << RCC_CCIPR_USART1SEL_SHIFT)
|
||||
#define RCC_CCIPR_USART2SEL_SHIFT (2) /* Bits 2-3: USART2 clock source selection */
|
||||
#define RCC_CCIPR_USART2SEL_MASK (3 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_APB (0 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_SYSCLK (1 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_HSI16 (2 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
# define RCC_CCIPR_USART2SEL_LSE (3 << RCC_CCIPR_USART2SEL_SHIFT)
|
||||
/* Bits 4-9: Reserved */
|
||||
#define RCC_CCIPR_LPUART1SEL_SHIFT (10) /* Bits 10-11: LPUART1 clock source selection */
|
||||
#define RCC_CCIPR_LPUART1SEL_MASK (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_APB (0 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_SYSCLK (1 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_HSI16 (2 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPUART1SEL_LSE (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
|
||||
#define RCC_CCIPR_I2C1SEL_SHIFT (12) /* Bits 12-13: I2C1 clock source selection */
|
||||
#define RCC_CCIPR_I2C1SEL_MASK (3 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C1SEL_APB (0 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C1SEL_SYSCLK (1 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C1SEL_HSI16 (2 << RCC_CCIPR_I2C1SEL_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define RCC_CCIPR_I2C3SEL_SHIFT (16) /* Bits 16-17: I2C3 clock source selection */
|
||||
#define RCC_CCIPR_I2C3SEL_MASK (3 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C3SEL_APB (0 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C3SEL_SYSCLK (1 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
# define RCC_CCIPR_I2C3SEL_HSI16 (2 << RCC_CCIPR_I2C3SEL_SHIFT)
|
||||
#define RCC_CCIPR_LPTIM1SEL_SHIFT (18) /* Bits 18-19: LPTIM1 clock source selection */
|
||||
#define RCC_CCIPR_LPTIM1SEL_MASK (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_APB (0 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_SYSCLK (1 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_HSI16 (2 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
# define RCC_CCIPR_LPTIM1SEL_LSE (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
|
||||
/* Bits 20-25: Reserved */
|
||||
#define RCC_CCIPR_HSI48SEL_SHIFT (26) /* Bit 26: HSI48 clock source selection */
|
||||
#define RCC_CCIPR_HSI48SEL_MASK (1 << RCC_CCIPR_HSI48SEL_SHIFT)
|
||||
# define RCC_CCIPR_HSI48SEL_PLL (0 << RCC_CCIPR_HSI48SEL_SHIFT)
|
||||
# define RCC_CCIPR_HSI48SEL_RC48 (1 << RCC_CCIPR_HSI48SEL_SHIFT)
|
||||
/* Bits 27-31: Reserved */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (0) /* Bit 0: LSI enable */
|
||||
#define RCC_CSR_LSIRDY (1) /* Bit 1: ready */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define RCC_CSR_LSEON (8) /* Bit 8: LSE enable */
|
||||
#define RCC_CSR_LSERDY (9) /* Bit 9: LSE ready */
|
||||
#define RCC_CSR_LSEBPY (10) /* Bit 10: LSE bypass */
|
||||
#define RCC_CSR_LSEDRV_SHIFT (11) /* Bits 11-12: LSE driving capability */
|
||||
#define RCC_CSR_LSEDRV_MASK (3 << RCC_CSR_LSEDRV_SHIFT)
|
||||
# define RCC_CSR_LSEDRV_LOW (0 << RCC_CSR_LSEDRV_SHIFT)
|
||||
# define RCC_CSR_LSEDRV_MEDLOW (1 << RCC_CSR_LSEDRV_SHIFT)
|
||||
# define RCC_CSR_LSEDRV_MEDHGIH (2 << RCC_CSR_LSEDRV_SHIFT)
|
||||
# define RCC_CSR_LSEDRV_HIGH (3 << RCC_CSR_LSEDRV_SHIFT)
|
||||
#define RCC_CSR_CSSLSEON (13) /* Bit 13: CSS on LSE enable */
|
||||
#define RCC_CSR_CSSLSED (14) /* Bit 14: CSS on LSE failure detection flag */
|
||||
/* Bit 15: Reserved */
|
||||
#define RCC_CSR_RTCSEL_SHIFT (16) /* Bits 16-17: RTC clock source selection */
|
||||
#define RCC_CSR_RTCSEL_MASK (3 << RCC_CSR_RTCSEL_SHIFT)
|
||||
# define RCC_CSR_RTCSEL_NOCLK (0 << RCC_CSR_RTCSEL_SHIFT)
|
||||
# define RCC_CSR_RTCSEL_LSE (1 << RCC_CSR_RTCSEL_SHIFT)
|
||||
# define RCC_CSR_RTCSEL_LSI (2 << RCC_CSR_RTCSEL_SHIFT)
|
||||
# define RCC_CSR_RTCSEL_HSE (3 << RCC_CSR_RTCSEL_SHIFT)
|
||||
#define RCC_CSR_RTCEN (18) /* Bit 18: RTC clock enable */
|
||||
#define RCC_CSR_RTCRST (19) /* Bit 19: RTC software reset */
|
||||
/* Bits 20-22: Reserved */
|
||||
#define RCC_CSR_RMVF (23) /* Bit 23: Remove reset flag */
|
||||
#define RCC_CSR_FWRSTF (24) /* Bit 24: Firewall reset flag */
|
||||
#define RCC_CSR_OBLRSTF (25) /* Bit 25: Options bytes loading reset flag */
|
||||
#define RCC_CSR_PINRSTF (26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_PORRSTF (27) /* Bit 27: POR/PDR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (28) /* Bit 28: software reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (29) /* Bit 29: IWDG reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (30) /* Bit 30: WWDG reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (31) /* Bit 31: Low-power reset flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H */
|
||||
132
arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
Normal file
132
arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
Normal file
@ -0,0 +1,132 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x0004 /* SYSCFG configuration register 2 */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CFGR3_OFFSET 0x0020 /* SYSCFG configuration register 3 */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CFGR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR3_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* TODO: SYSCFG configuration register 1 */
|
||||
|
||||
/* TODO: SYSCFG configuration register 2 */
|
||||
|
||||
/* TODO: SYSCFG configuration register 3 */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H */
|
||||
345
arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
Normal file
345
arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
Normal file
@ -0,0 +1,345 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H
|
||||
#define __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: Word length */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */
|
||||
#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT)
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */
|
||||
#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT)
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */
|
||||
|
||||
#define USART_CR1_ALLINTS \
|
||||
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\
|
||||
USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE)
|
||||
|
||||
/* F0 Compatibility definitions */
|
||||
|
||||
#define USART_CR1_M0 USART_CR1_M
|
||||
#define USART_CR1_M1 0
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */
|
||||
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */
|
||||
# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */
|
||||
# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */
|
||||
# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */
|
||||
#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT)
|
||||
#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */
|
||||
#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT)
|
||||
#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */
|
||||
#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT)
|
||||
|
||||
/* F0 Compatibility definitions */
|
||||
|
||||
#define USART_CR2_SWAP 0
|
||||
#define USART_CR2_ADD_MASK USART_CR2_ADD8_MASK
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
|
||||
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */
|
||||
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */
|
||||
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */
|
||||
#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */
|
||||
#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT)
|
||||
#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */
|
||||
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
|
||||
# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */
|
||||
# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */
|
||||
# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */
|
||||
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/
|
||||
#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT)
|
||||
#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */
|
||||
#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT)
|
||||
#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/
|
||||
#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
|
||||
/* Request register */
|
||||
|
||||
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */
|
||||
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */
|
||||
#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */
|
||||
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */
|
||||
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */
|
||||
|
||||
/* Interrupt & status register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */
|
||||
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */
|
||||
#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */
|
||||
|
||||
#define USART_ISR_ALLBITS (0x007fdfff)
|
||||
|
||||
/* Interrupt flag clear register */
|
||||
|
||||
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
|
||||
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
|
||||
|
||||
#define USART_ICR_ALLBITS (0x00121b5f)
|
||||
|
||||
/* Receive data register */
|
||||
|
||||
#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */
|
||||
#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
|
||||
|
||||
/* Transmit data register */
|
||||
|
||||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */
|
||||
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
|
||||
|
||||
/* Compatibility definitions ********************************************************/
|
||||
/* F1/F2/F4 Status register */
|
||||
|
||||
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
|
||||
|
||||
#define USART_SR_PE USART_ISR_PE /* Parity Error */
|
||||
#define USART_SR_FE USART_ISR_FE /* Framing error */
|
||||
#define USART_SR_NE USART_ISR_NF /* Noise detected flag */
|
||||
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
|
||||
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
|
||||
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
|
||||
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
|
||||
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
|
||||
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
|
||||
#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS USART_ISR_ALLBITS
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H */
|
||||
334
arch/arm/src/stm32f0l0/stm32_dma.h
Normal file
334
arch/arm/src/stm32f0l0/stm32_dma.h
Normal file
@ -0,0 +1,334 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_dma.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2013, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "hardware/stm32_dma_v1.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* These definitions provide the bit encoding of the 'status' parameter passed to the
|
||||
* DMA callback function (see dma_callback_t).
|
||||
*/
|
||||
|
||||
#define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
|
||||
#define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
|
||||
#define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
|
||||
|
||||
#define DMA_STATUS_ERROR (DMA_STATUS_TEIF)
|
||||
#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/* DMA_HANDLE provides an opaque are reference that can be used to represent a DMA
|
||||
* channel (F1) or a DMA stream (F4).
|
||||
*/
|
||||
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
|
||||
/* Description:
|
||||
* This is the type of the callback that is used to inform the user of the
|
||||
* completion of the DMA.
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - Refers tot he DMA channel or stream
|
||||
* status - A bit encoded value that provides the completion status. See the
|
||||
* DMASTATUS_* definitions above.
|
||||
* arg - A user-provided value that was provided when stm32_dmastart() was
|
||||
* called.
|
||||
*/
|
||||
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t isr;
|
||||
uint32_t ccr;
|
||||
uint32_t cndtr;
|
||||
uint32_t cpar;
|
||||
uint32_t cmar;
|
||||
};
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function gives the caller mutually
|
||||
* exclusive access to the DMA channel specified by the 'chan' argument.
|
||||
* DMA channels are shared on the STM32: Devices sharing the same DMA
|
||||
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
||||
* stm32_dma.h.
|
||||
*
|
||||
* If the DMA channel is not available, then stm32_dmachannel() will wait
|
||||
* until the holder of the channel relinquishes the channel by calling
|
||||
* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
|
||||
* channel and the code never releases the channel, the stm32_dmachannel
|
||||
* call for the other will hang forever in this function! Don't let your
|
||||
* design do that!
|
||||
*
|
||||
* Hmm.. I suppose this interface could be extended to make a non-blocking
|
||||
* version. Feel free to do that if that is what you need.
|
||||
*
|
||||
* Input Parameters:
|
||||
* chan - Identifies the stream/channel resource
|
||||
* For the STM32 F1, this is simply the channel number as provided by
|
||||
* the DMACHAN_* definitions in chip/stm32f10xxx_dma.h.
|
||||
* For the STM32 F4, this is a bit encoded value as provided by the
|
||||
* the DMAMAP_* definitions in chip/stm32f40xxx_dma.h
|
||||
*
|
||||
* Returned Value:
|
||||
* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
|
||||
* void* DMA channel handle. (If 'chan' is invalid, the function will
|
||||
* assert if debug is enabled or do something ignorant otherwise).
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller does not hold he DMA channel.
|
||||
* - The caller can wait for the DMA channel to be freed if it is no
|
||||
* available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE stm32_dmachannel(unsigned int chan);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. If another thread is waiting for this DMA channel
|
||||
* in a call to stm32_dmachannel, then this function will re-assign the
|
||||
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
||||
* in this argument must NEVER be used again until stm32_dmachannel() is
|
||||
* called again to re-gain access to the channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller holds the DMA channel.
|
||||
* - There is no DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmafree(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t ntransfers, uint32_t ccr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
* - No DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg,
|
||||
bool half);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
||||
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Returns the number of bytes remaining to be transferred
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t stm32_dmaresidual(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmacapable
|
||||
*
|
||||
* Description:
|
||||
* Check if the DMA controller can transfer data to/from given memory
|
||||
* address with the given configuration. This depends on the internal
|
||||
* connections in the ARM bus matrix of the processor. Note that this
|
||||
* only applies to memory addresses, it will return false for any peripheral
|
||||
* address.
|
||||
*
|
||||
* Returned Value:
|
||||
* True, if transfer is possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_DMACAPABLE
|
||||
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
|
||||
#else
|
||||
# define stm32_dmacapable(maddr, count, ccr) (true)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs);
|
||||
#else
|
||||
# define stm32_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
const char *msg);
|
||||
#else
|
||||
# define stm32_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
/* High performance, zero latency DMA interrupts need some additional
|
||||
* interfaces.
|
||||
*
|
||||
* TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2.
|
||||
* It should be unified somehow.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dma_intack
|
||||
*
|
||||
* Description:
|
||||
* Public visible interface to acknowledge interrupts on DMA channel
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(HAVE_IP_DMA_V1)
|
||||
void stm32_dma_intack(unsigned int chndx, uint32_t isr);
|
||||
#elif defined(HAVE_IP_DMA_V2)
|
||||
void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dma_intget
|
||||
*
|
||||
* Description:
|
||||
* Public visible interface to get pending interrupts from DMA channel
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(HAVE_IP_DMA_V1)
|
||||
uint32_t stm32_dma_intget(unsigned int chndx);
|
||||
#elif defined(HAVE_IP_DMA_V2)
|
||||
uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream);
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H */
|
||||
815
arch/arm/src/stm32f0l0/stm32_dma_v1.c
Normal file
815
arch/arm/src/stm32f0l0/stm32_dma_v1.c
Normal file
@ -0,0 +1,815 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_dma_v1.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2013, 2016-2018 Gregory Nutt. All rights
|
||||
* reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <semaphore.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "sched/sched.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32.h"
|
||||
|
||||
/* This file supports the STM32 DMA IP core version 1 - F0, F1, F3, L0, L1, L4
|
||||
*
|
||||
* F0, L0 and L4 have the additional CSELR register which is used to remap
|
||||
* the DMA requests for each channel.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define DMA1_NCHANNELS 7
|
||||
|
||||
#if STM32_NDMA > 1
|
||||
# define DMA2_NCHANNELS 5
|
||||
# define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS)
|
||||
#else
|
||||
# define DMA_NCHANNELS DMA1_NCHANNELS
|
||||
#endif
|
||||
|
||||
/* Convert the DMA channel base address to the DMA register block address */
|
||||
|
||||
#define DMA_BASE(ch) (ch & 0xfffffc00)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/* This structure descibes one DMA channel */
|
||||
|
||||
struct stm32_dma_s
|
||||
{
|
||||
uint8_t chan; /* DMA channel number (0-6) */
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
uint8_t function; /* DMA peripheral connected to this channel (0-7) */
|
||||
#endif
|
||||
uint8_t irq; /* DMA channel IRQ number */
|
||||
sem_t sem; /* Used to wait for DMA channel to become available */
|
||||
uint32_t base; /* DMA register channel base address */
|
||||
dma_callback_t callback; /* Callback invoked when the DMA completes */
|
||||
void *arg; /* Argument passed to callback function */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This array describes the state of each DMA */
|
||||
|
||||
static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
|
||||
{
|
||||
{
|
||||
.chan = 0,
|
||||
.irq = STM32_IRQ_DMA1CH1,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
|
||||
},
|
||||
{
|
||||
.chan = 1,
|
||||
.irq = STM32_IRQ_DMA1CH2,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
|
||||
},
|
||||
{
|
||||
.chan = 2,
|
||||
.irq = STM32_IRQ_DMA1CH3,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
|
||||
},
|
||||
{
|
||||
.chan = 3,
|
||||
.irq = STM32_IRQ_DMA1CH4,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
|
||||
},
|
||||
{
|
||||
.chan = 4,
|
||||
.irq = STM32_IRQ_DMA1CH5,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
|
||||
},
|
||||
{
|
||||
.chan = 5,
|
||||
.irq = STM32_IRQ_DMA1CH6,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
|
||||
},
|
||||
{
|
||||
.chan = 6,
|
||||
.irq = STM32_IRQ_DMA1CH7,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
|
||||
},
|
||||
#if STM32_NDMA > 1
|
||||
{
|
||||
.chan = 0,
|
||||
.irq = STM32_IRQ_DMA2CH1,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0),
|
||||
},
|
||||
{
|
||||
.chan = 1,
|
||||
.irq = STM32_IRQ_DMA2CH2,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1),
|
||||
},
|
||||
{
|
||||
.chan = 2,
|
||||
.irq = STM32_IRQ_DMA2CH3,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2),
|
||||
},
|
||||
{
|
||||
.chan = 3,
|
||||
.irq = STM32_IRQ_DMA2CH45,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
|
||||
},
|
||||
{
|
||||
.chan = 4,
|
||||
.irq = STM32_IRQ_DMA2CH45,
|
||||
.base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* DMA register access functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Get non-channel register from DMA1 or DMA2 */
|
||||
|
||||
static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach,
|
||||
uint32_t offset)
|
||||
{
|
||||
return getreg32(DMA_BASE(dmach->base) + offset);
|
||||
}
|
||||
|
||||
/* Write to non-channel register in DMA1 or DMA2 */
|
||||
|
||||
static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset,
|
||||
uint32_t value)
|
||||
{
|
||||
putreg32(value, DMA_BASE(dmach->base) + offset);
|
||||
}
|
||||
|
||||
/* Get channel register from DMA1 or DMA2 */
|
||||
|
||||
static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach,
|
||||
uint32_t offset)
|
||||
{
|
||||
return getreg32(dmach->base + offset);
|
||||
}
|
||||
|
||||
/* Write to channel register in DMA1 or DMA2 */
|
||||
|
||||
static inline void dmachan_putreg(struct stm32_dma_s *dmach,
|
||||
uint32_t offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, dmach->base + offset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmatake() and stm32_dmagive()
|
||||
*
|
||||
* Description:
|
||||
* Used to get exclusive access to a DMA channel.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_dmatake(FAR struct stm32_dma_s *dmach)
|
||||
{
|
||||
int ret;
|
||||
|
||||
do
|
||||
{
|
||||
/* Take the semaphore (perhaps waiting) */
|
||||
|
||||
ret = nxsem_wait(&dmach->sem);
|
||||
|
||||
/* The only case that an error should occur here is if the wait was
|
||||
* awakened by a signal.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(ret == OK || ret == -EINTR);
|
||||
}
|
||||
while (ret == -EINTR);
|
||||
}
|
||||
|
||||
static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach)
|
||||
{
|
||||
(void)nxsem_post(&dmach->sem);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachandisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the DMA channel
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_dmachandisable(struct stm32_dma_s *dmach)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Disable all interrupts at the DMA controller */
|
||||
|
||||
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regval &= ~DMA_CCR_ALLINTS;
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
||||
regval &= ~DMA_CCR_EN;
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
|
||||
|
||||
/* Clear pending channel interrupts */
|
||||
|
||||
dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET,
|
||||
DMA_ISR_CHAN_MASK(dmach->chan));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmainterrupt
|
||||
*
|
||||
* Description:
|
||||
* DMA interrupt handler
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_dmainterrupt(int irq, void *context, FAR void *arg)
|
||||
{
|
||||
struct stm32_dma_s *dmach;
|
||||
uint32_t isr;
|
||||
int chndx = 0;
|
||||
|
||||
/* Get the channel structure from the interrupt number */
|
||||
|
||||
if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
|
||||
{
|
||||
chndx = irq - STM32_IRQ_DMA1CH1;
|
||||
}
|
||||
else
|
||||
#if STM32_NDMA > 1
|
||||
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
|
||||
{
|
||||
chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
DEBUGPANIC();
|
||||
}
|
||||
dmach = &g_dma[chndx];
|
||||
|
||||
/* Get the interrupt status (for this channel only) */
|
||||
|
||||
isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) &
|
||||
DMA_ISR_CHAN_MASK(dmach->chan);
|
||||
|
||||
/* Clear the interrupts we are handling */
|
||||
|
||||
dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
|
||||
|
||||
/* Invoke the callback */
|
||||
|
||||
if (dmach->callback)
|
||||
{
|
||||
dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan),
|
||||
dmach->arg);
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmainitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DMA subsystem
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function up_dma_initialize(void)
|
||||
{
|
||||
struct stm32_dma_s *dmach;
|
||||
int chndx;
|
||||
|
||||
/* Initialize each DMA channel */
|
||||
|
||||
for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
|
||||
{
|
||||
dmach = &g_dma[chndx];
|
||||
nxsem_init(&dmach->sem, 0, 1);
|
||||
|
||||
/* Attach DMA interrupt vectors */
|
||||
|
||||
(void)irq_attach(dmach->irq, stm32_dmainterrupt, NULL);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
||||
stm32_dmachandisable(dmach);
|
||||
|
||||
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
|
||||
|
||||
up_enable_irq(dmach->irq);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function gives the caller mutually
|
||||
* exclusive access to the DMA channel specified by the 'chndx' argument.
|
||||
* DMA channels are shared on the STM32: Devices sharing the same DMA
|
||||
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
||||
* stm32_dma.h.
|
||||
*
|
||||
* If the DMA channel is not available, then stm32_dmachannel() will wait
|
||||
* until the holder of the channel relinquishes the channel by calling
|
||||
* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
|
||||
* channel and the code never releases the channel, the stm32_dmachannel
|
||||
* call for the other will hang forever in this function! Don't let your
|
||||
* design do that!
|
||||
*
|
||||
* Hmm.. I suppose this interface could be extended to make a non-blocking
|
||||
* version. Feel free to do that if that is what you need.
|
||||
*
|
||||
* Input Parameters:
|
||||
* chndx - Identifies the stream/channel resource. For the STM32 F1, this
|
||||
* is simply the channel number as provided by the DMACHAN_* definitions
|
||||
* in chip/stm32f10xxx_dma.h.
|
||||
*
|
||||
* Returned Value:
|
||||
* Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL,
|
||||
* void* DMA channel handle. (If 'chndx' is invalid, the function will
|
||||
* assert if debug is enabled or do something ignorant otherwise).
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller does not hold he DMA channel.
|
||||
* - The caller can wait for the DMA channel to be freed if it is no
|
||||
* available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE stm32_dmachannel(unsigned int chndef)
|
||||
{
|
||||
int chndx = 0;
|
||||
struct stm32_dma_s *dmach = NULL;
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >>
|
||||
DMACHAN_SETTING_CHANNEL_SHIFT;
|
||||
#else
|
||||
chndx = chndef;
|
||||
#endif
|
||||
|
||||
dmach = &g_dma[chndx];
|
||||
|
||||
DEBUGASSERT(chndx < DMA_NCHANNELS);
|
||||
|
||||
/* Get exclusive access to the DMA channel -- OR wait until the channel
|
||||
* is available if it is currently being used by another driver
|
||||
*/
|
||||
|
||||
stm32_dmatake(dmach);
|
||||
|
||||
/* The caller now has exclusive use of the DMA channel */
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
/* Define the peripheral that will use the channel. This is stored until
|
||||
* dmasetup is called.
|
||||
*/
|
||||
|
||||
dmach->function = (chndef & DMACHAN_SETTING_FUNCTION_MASK) >>
|
||||
DMACHAN_SETTING_FUNCTION_SHIFT;
|
||||
#endif
|
||||
|
||||
return (DMA_HANDLE)dmach;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. If another thread is waiting for this DMA channel
|
||||
* in a call to stm32_dmachannel, then this function will re-assign the
|
||||
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
||||
* in this argument must NEVER be used again until stm32_dmachannel() is
|
||||
* called again to re-gain access to the channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller holds the DMA channel.
|
||||
* - There is no DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmafree(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
/* Release the channel */
|
||||
|
||||
stm32_dmagive(dmach);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t ntransfers, uint32_t ccr)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
uint32_t regval;
|
||||
|
||||
/* Then DMA_CNDTRx register can only be modified if the DMA channel is
|
||||
* disabled.
|
||||
*/
|
||||
|
||||
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regval &= ~(DMA_CCR_EN);
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
|
||||
|
||||
/* Set the peripheral register address in the DMA_CPARx register. The data
|
||||
* will be moved from/to this address to/from the memory after the
|
||||
* peripheral event.
|
||||
*/
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr);
|
||||
|
||||
/* Set the memory address in the DMA_CMARx register. The data will be
|
||||
* written to or read from this memory after the peripheral event.
|
||||
*/
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr);
|
||||
|
||||
/* Configure the total number of data to be transferred in the DMA_CNDTRx
|
||||
* register. After each peripheral event, this value will be decremented.
|
||||
*/
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers);
|
||||
|
||||
/* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx
|
||||
* register. Configure data transfer direction, circular mode, peripheral
|
||||
* and memory incremented mode, peripheral & memory data size, and
|
||||
* interrupt after half and/or full transfer in the DMA_CCRx register.
|
||||
*/
|
||||
|
||||
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
|
||||
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC |
|
||||
DMA_CCR_CIRC | DMA_CCR_DIR);
|
||||
ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
|
||||
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC |
|
||||
DMA_CCR_CIRC | DMA_CCR_DIR);
|
||||
regval |= ccr;
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
|
||||
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
/* Define peripheral indicated in dmach->function */
|
||||
|
||||
regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET);
|
||||
regval &= ~(0x0f << (dmach->chan << 2));
|
||||
regval |= (dmach->function << (dmach->chan << 2));
|
||||
dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
* - No DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
|
||||
void *arg, bool half)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
uint32_t ccr;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
/* Save the callback info. This will be invoked whent the DMA commpletes */
|
||||
|
||||
dmach->callback = callback;
|
||||
dmach->arg = arg;
|
||||
|
||||
/* Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
|
||||
* As soon as the channel is enabled, it can serve any DMA request from the
|
||||
* peripheral connected on the channel.
|
||||
*/
|
||||
|
||||
ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
ccr |= DMA_CCR_EN;
|
||||
|
||||
/* In normal mode, interrupt at either half or full completion. In circular
|
||||
* mode, always interrupt on buffer wrap, and optionally interrupt at the
|
||||
* halfway point.
|
||||
*/
|
||||
|
||||
if ((ccr & DMA_CCR_CIRC) == 0)
|
||||
{
|
||||
/* Once half of the bytes are transferred, the half-transfer flag
|
||||
* (HTIF) is set and an interrupt is generated if the Half-Transfer
|
||||
* Interrupt Enable bit (HTIE) is set. At the end of the transfer, the
|
||||
* Transfer Complete Flag (TCIF) is set and an interrupt is generated
|
||||
* if the Transfer Complete Interrupt Enable bit (TCIE) is set.
|
||||
*/
|
||||
|
||||
ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) :
|
||||
(DMA_CCR_TCIE | DMA_CCR_TEIE));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In nonstop mode, when the transfer completes it immediately resets
|
||||
* and starts again. The transfer-complete interrupt is thus always
|
||||
* enabled, and the half-complete interrupt can be used in circular
|
||||
* mode to determine when the buffer is half-full, or in double-buffered
|
||||
* mode to determine when one of the two buffers is full.
|
||||
*/
|
||||
|
||||
ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE;
|
||||
}
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
||||
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastop(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
stm32_dmachandisable(dmach);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Returns the number of bytes remaining to be transferred
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t stm32_dmaresidual(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
|
||||
return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmacapable
|
||||
*
|
||||
* Description:
|
||||
* Check if the DMA controller can transfer data to/from given memory
|
||||
* address. This depends on the internal connections in the ARM bus matrix
|
||||
* of the processor. Note that this only applies to memory addresses, it
|
||||
* will return false for any peripheral address.
|
||||
*
|
||||
* Returned Value:
|
||||
* True, if transfer is possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_DMACAPABLE
|
||||
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
|
||||
{
|
||||
uint32_t transfer_size;
|
||||
uint32_t mend;
|
||||
|
||||
/* Verify that the address conforms to the memory transfer size.
|
||||
* Transfers to/from memory performed by the DMA controller are
|
||||
* required to be aligned to their size.
|
||||
*
|
||||
* See ST RM0090 rev4, section 9.3.11
|
||||
*
|
||||
* Compute mend inline to avoid a possible non-constant integer
|
||||
* multiply.
|
||||
*/
|
||||
|
||||
switch (ccr & DMA_CCR_MSIZE_MASK)
|
||||
{
|
||||
case DMA_CCR_MSIZE_8BITS:
|
||||
transfer_size = 1;
|
||||
mend = maddr + count - 1;
|
||||
break;
|
||||
|
||||
case DMA_CCR_MSIZE_16BITS:
|
||||
transfer_size = 2;
|
||||
mend = maddr + (count << 1) - 1;
|
||||
break;
|
||||
|
||||
case DMA_CCR_MSIZE_32BITS:
|
||||
transfer_size = 4;
|
||||
mend = maddr + (count << 2) - 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((maddr & (transfer_size - 1)) != 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Verify that the transfer is to a memory region that supports DMA. */
|
||||
|
||||
if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (maddr & STM32_REGION_MASK)
|
||||
{
|
||||
case STM32_SRAM_BASE:
|
||||
case STM32_CODE_BASE:
|
||||
/* All RAM and flash is supported */
|
||||
|
||||
return true;
|
||||
|
||||
default:
|
||||
/* Everything else is unsupported by DMA */
|
||||
|
||||
return false;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET);
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET);
|
||||
#endif
|
||||
regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
|
||||
regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET);
|
||||
regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
const char *msg)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
uint32_t dmabase = DMA_BASE(dmach->base);
|
||||
|
||||
dmainfo("DMA Registers: %s\n", msg);
|
||||
dmainfo(" ISRC[%08x]: %08x\n",
|
||||
dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
|
||||
#ifdef DMA_HAVE_CSELR
|
||||
dmainfo(" CSELR[%08x]: %08x\n",
|
||||
dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr);
|
||||
#endif
|
||||
dmainfo(" CCR[%08x]: %08x\n",
|
||||
dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
|
||||
dmainfo(" CNDTR[%08x]: %08x\n",
|
||||
dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
|
||||
dmainfo(" CPAR[%08x]: %08x\n",
|
||||
dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
|
||||
dmainfo(" CMAR[%08x]: %08x\n",
|
||||
dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dma_intack
|
||||
*
|
||||
* Description:
|
||||
* Public visible interface to acknowledge interrupts on DMA channel
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dma_intack(unsigned int chndx, uint32_t isr)
|
||||
{
|
||||
struct stm32_dma_s *dmach = &g_dma[chndx];
|
||||
|
||||
dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dma_intget
|
||||
*
|
||||
* Description:
|
||||
* Public visible interface to get pending interrupts from DMA channel
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t stm32_dma_intget(unsigned int chndx)
|
||||
{
|
||||
struct stm32_dma_s *dmach = &g_dma[chndx];
|
||||
|
||||
return dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) &
|
||||
DMA_ISR_CHAN_MASK(dmach->chan);
|
||||
}
|
||||
#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */
|
||||
@ -64,22 +64,24 @@
|
||||
const uint32_t g_gpiobase[STM32_NPORTS] =
|
||||
{
|
||||
#if STM32_NPORTS > 0
|
||||
STM32_GPIOA_BASE,
|
||||
STM32_GPIOA_BASE, /* One GPIO ports, GPIOA */
|
||||
#endif
|
||||
#if STM32_NPORTS > 1
|
||||
STM32_GPIOB_BASE,
|
||||
STM32_GPIOB_BASE, /* Two GPIO ports, GPIOA-B */
|
||||
#endif
|
||||
#if STM32_NPORTS > 2
|
||||
STM32_GPIOC_BASE,
|
||||
STM32_GPIOC_BASE, /* Three GPIO ports, GPIOA-D*/
|
||||
#endif
|
||||
#if STM32_NPORTS > 3
|
||||
STM32_GPIOD_BASE,
|
||||
STM32_GPIOD_BASE, /* Four GPIO ports, GPIOA-D */
|
||||
#endif
|
||||
#if STM32_NPORTS > 4
|
||||
STM32_GPIOE_BASE,
|
||||
STM32_GPIOE_BASE, /* Five GPIO ports, GPIOA-E */
|
||||
#endif
|
||||
#if STM32_NPORTS > 5
|
||||
STM32_GPIOF_BASE,
|
||||
#if STM32_NPORTS > 5 && defined(STM32_HAVE_PORTF)
|
||||
STM32_GPIOF_BASE, /* Six GPIO ports, GPIOA-F */
|
||||
#elif STM32_NPORTS > 5 && !defined(STM32_HAVE_PORTF)
|
||||
STM32_GPIOH_BASE, /* Six GPIO ports, GPIOA-E, H */
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -249,17 +251,35 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
switch (cfgset & GPIO_SPEED_MASK)
|
||||
{
|
||||
default:
|
||||
case GPIO_SPEED_2MHz: /* 2 MHz Low speed output */
|
||||
#if defined(STM32_GPIO_VERY_LOW_SPEED)
|
||||
case GPIO_SPPED_VERYLOW: /* 400KHz Very Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_10MHz: /* 10 MHz Medium speed output */
|
||||
case GPIO_SPEED_LOW: /* 2 MHz Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_MEDIUM: /* 10 MHz Medium speed output */
|
||||
setting = GPIO_OSPEED_10MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_50MHz: /* 50 MHz High speed output */
|
||||
case GPIO_SPEED_HIGH: /* 40 MHz High speed output */
|
||||
setting = GPIO_OSPEED_40MHz;
|
||||
break;
|
||||
#else
|
||||
case GPIO_SPEED_LOW: /* 2 MHz Low speed output */
|
||||
setting = GPIO_OSPEED_2MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_MEDIUM: /* 10 MHz Medium speed output */
|
||||
setting = GPIO_OSPEED_10MHz;
|
||||
break;
|
||||
|
||||
case GPIO_SPEED_HIGH: /* 50 MHz High speed output */
|
||||
setting = GPIO_OSPEED_50MHz;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
else
|
||||
|
||||
@ -54,6 +54,7 @@
|
||||
#include <arch/stm32f0l0/chip.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_gpio.h"
|
||||
#include "hardware/stm32_pinmap.h"
|
||||
|
||||
/************************************************************************************
|
||||
@ -142,9 +143,17 @@
|
||||
|
||||
#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
|
||||
#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
|
||||
# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_10MHz (1 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */
|
||||
# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */
|
||||
|
||||
#if defined(STM32_GPIO_VERY_LOW_SPEED)
|
||||
# define GPIO_SPPED_VERYLOW (0 << GPIO_SPEED_SHIFT) /* 400 kHz Very low speed */
|
||||
# define GPIO_SPEED_LOW (1 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_MEDIUM (2 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */
|
||||
# define GPIO_SPEED_HIGH (3 << GPIO_SPEED_SHIFT) /* 40 MHz High speed output */
|
||||
#else
|
||||
# define GPIO_SPEED_LOW (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_MEDIUM (1 << GPIO_SPEED_SHIFT) /* 10 MHz Medium speed output */
|
||||
# define GPIO_SPEED_HIGH (3 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */
|
||||
#endif
|
||||
|
||||
/* Output/Alt function type selection:
|
||||
*
|
||||
|
||||
@ -190,7 +190,7 @@
|
||||
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
|
||||
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
|
||||
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
|
||||
USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
|
||||
USART_CR3_SCARCNT_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
|
||||
|
||||
# define USART_CR3_SETBITS 0
|
||||
|
||||
|
||||
102
arch/arm/src/stm32f0l0/stm32_lse.c
Normal file
102
arch/arm/src/stm32f0l0/stm32_lse.c
Normal file
@ -0,0 +1,102 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_lse.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.orgr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32_pwr.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External Low-Speed (LSE) oscillator.
|
||||
*
|
||||
* Todo:
|
||||
* Check for LSE good timeout and return with -1,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void)
|
||||
{
|
||||
/* The LSE is in the RTC domain and write access is denied to this domain
|
||||
* after reset, you have to enable write access using DBP bit in the PWR CR
|
||||
* register before to configuring the LSE.
|
||||
*/
|
||||
|
||||
stm32_pwr_enablebkp(true);
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32L0)
|
||||
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
|
||||
* the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSEON);
|
||||
|
||||
/* Wait for the LSE clock to be ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSERDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F0)
|
||||
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
|
||||
* the RCC BDCR register.
|
||||
*/
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
|
||||
|
||||
/* Wait for the LSE clock to be ready */
|
||||
|
||||
while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* Disable backup domain access if it was disabled on entry */
|
||||
|
||||
stm32_pwr_enablebkp(false);
|
||||
}
|
||||
419
arch/arm/src/stm32f0l0/stm32_pwr.c
Normal file
419
arch/arm/src/stm32f0l0/stm32_pwr.c
Normal file
@ -0,0 +1,419 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_pwr.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_PWR)
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
/* Wakeup Pin Definitions: See chip/stm32_pwr.h */
|
||||
|
||||
#undef HAVE_PWR_WKUP2
|
||||
#undef HAVE_PWR_WKUP3
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define HAVE_PWR_WKUP2 1
|
||||
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
# define HAVE_PWR_WKUP2 1
|
||||
# define HAVE_PWR_WKUP3 1
|
||||
#endif
|
||||
|
||||
/* Thr parts only support a single Wake-up pin do not include the numeric suffix
|
||||
* in the naming.
|
||||
*/
|
||||
|
||||
#ifndef PWR_CSR_EWUP1
|
||||
# define PWR_CSR_EWUP1 PWR_CSR_EWUP
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
static uint16_t g_bkp_writable_counter = 0;
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
static inline uint32_t stm32_pwr_getreg32(uint8_t offset)
|
||||
{
|
||||
return getreg32(STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits,
|
||||
uint32_t setbits)
|
||||
{
|
||||
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_initbkp
|
||||
*
|
||||
* Description:
|
||||
* Insures the referenced count access to the backup domain (RTC registers,
|
||||
* RTC backup data registers and backup SRAM is consistent with the HW state
|
||||
* without relying on a variable.
|
||||
*
|
||||
* NOTE: This function should only be called by SoC Start up code.
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_initbkp(bool writable)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
/* Make the HW not writable */
|
||||
|
||||
regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
|
||||
regval &= ~PWR_CR_DBP;
|
||||
stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
|
||||
|
||||
/* Make the reference count agree */
|
||||
|
||||
g_bkp_writable_counter = 0;
|
||||
stm32_pwr_enablebkp(writable);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables access to the backup domain (RTC registers, RTC backup data registers
|
||||
* and backup SRAM).
|
||||
*
|
||||
* NOTE: Reference counting is used in order to supported nested calls to this
|
||||
* function. As a consequence, every call to stm32_pwr_enablebkp(true) must
|
||||
* be followed by a matching call to stm32_pwr_enablebkp(false).
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablebkp(bool writable)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint16_t regval;
|
||||
bool waswritable;
|
||||
bool wait = false;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Get the current state of the STM32 PWR control register */
|
||||
|
||||
regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
|
||||
waswritable = ((regval & PWR_CR_DBP) != 0);
|
||||
|
||||
if (writable)
|
||||
{
|
||||
DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
|
||||
g_bkp_writable_counter++;
|
||||
}
|
||||
else if (g_bkp_writable_counter > 0)
|
||||
{
|
||||
g_bkp_writable_counter--;
|
||||
}
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
||||
if (waswritable && g_bkp_writable_counter == 0)
|
||||
{
|
||||
/* Disable backup domain access */
|
||||
|
||||
regval &= ~PWR_CR_DBP;
|
||||
stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
|
||||
}
|
||||
else if (!waswritable && g_bkp_writable_counter > 0)
|
||||
{
|
||||
/* Enable backup domain access */
|
||||
|
||||
regval |= PWR_CR_DBP;
|
||||
stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
|
||||
|
||||
wait = true;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
if (wait)
|
||||
{
|
||||
/* Enable does not happen right away */
|
||||
|
||||
up_udelay(4);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablewkup
|
||||
*
|
||||
* Description:
|
||||
* Enables the WKUP pin.
|
||||
*
|
||||
* Input Parameters:
|
||||
* wupin - Selects the WKUP pin to enable/disable
|
||||
* wupon - state to set it to
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned on any
|
||||
* failure. The only cause of failure is if the selected MCU does not support
|
||||
* the requested wakeup pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon)
|
||||
{
|
||||
uint16_t pinmask;
|
||||
|
||||
/* Select the PWR_CSR bit associated with the requested wakeup pin */
|
||||
|
||||
switch (wupin)
|
||||
{
|
||||
case PWR_WUPIN_1: /* Wake-up pin 1 (all parts) */
|
||||
pinmask = PWR_CSR_EWUP1;
|
||||
break;
|
||||
|
||||
#ifdef HAVE_PWR_WKUP2
|
||||
case PWR_WUPIN_2: /* Wake-up pin 2 */
|
||||
pinmask = PWR_CSR_EWUP2;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_PWR_WKUP3
|
||||
case PWR_WUPIN_3: /* Wake-up pin 3 */
|
||||
pinmask = PWR_CSR_EWUP3;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set/clear the the wakeup pin enable bit in the CSR. This must be done
|
||||
* within a critical section because the CSR is shared with other functions
|
||||
* that may be running concurrently on another thread.
|
||||
*/
|
||||
|
||||
if (wupon)
|
||||
{
|
||||
/* Enable the wakeup pin by setting the bit in the CSR. */
|
||||
|
||||
stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the wakeup pin by clearing the bit in the CSR. */
|
||||
|
||||
stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_getsbf
|
||||
*
|
||||
* Description:
|
||||
* Return the standby flag.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool stm32_pwr_getsbf(void)
|
||||
{
|
||||
return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_SBF) != 0;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_getwuf
|
||||
*
|
||||
* Description:
|
||||
* Return the wakeup flag.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool stm32_pwr_getwuf(void)
|
||||
{
|
||||
return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_WUF) != 0;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setvos
|
||||
*
|
||||
* Description:
|
||||
* Set voltage scaling for EnergyLite devices.
|
||||
*
|
||||
* Input Parameters:
|
||||
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic. If used
|
||||
* for any other purpose that protection to assure that its operation is atomic
|
||||
* will be required.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_ENERGYLITE
|
||||
void stm32_pwr_setvos(uint16_t vos)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
/* The following sequence is required to program the voltage regulator ranges:
|
||||
* 1. Check VDD to identify which ranges are allowed...
|
||||
* 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.
|
||||
* 3. Configure the voltage scaling range by setting the VOS bits in the PWR_CR
|
||||
* register.
|
||||
* 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
|
||||
*/
|
||||
|
||||
while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
|
||||
{
|
||||
}
|
||||
|
||||
regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= (vos & PWR_CR_VOS_MASK);
|
||||
stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
|
||||
|
||||
while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setpvd
|
||||
*
|
||||
* Description:
|
||||
* Sets power voltage detector
|
||||
*
|
||||
* Input Parameters:
|
||||
* pls - PVD level
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic. If used
|
||||
* for any other purpose that protection to assure that its operation is atomic
|
||||
* will be required.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_setpvd(uint16_t pls)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
/* Set PLS */
|
||||
|
||||
regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
|
||||
regval &= ~PWR_CR_PLS_MASK;
|
||||
regval |= (pls & PWR_CR_PLS_MASK);
|
||||
|
||||
/* Write value to register */
|
||||
|
||||
stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablepvd
|
||||
*
|
||||
* Description:
|
||||
* Enable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablepvd(void)
|
||||
{
|
||||
/* Enable PVD by setting the PVDE bit in PWR_CR register. */
|
||||
|
||||
stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_disablepvd
|
||||
*
|
||||
* Description:
|
||||
* Disable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_disablepvd(void)
|
||||
{
|
||||
/* Disable PVD by clearing the PVDE bit in PWR_CR register. */
|
||||
|
||||
stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_ENERGYLITE */
|
||||
|
||||
#endif /* CONFIG_STM32F0L0_PWR */
|
||||
234
arch/arm/src/stm32f0l0/stm32_pwr.h
Normal file
234
arch/arm/src/stm32f0l0/stm32_pwr.h
Normal file
@ -0,0 +1,234 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f0l0/stm32_pwr.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_pwr.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/* Identify MCU-specific wakeup pin. Different STM32 parts support differing
|
||||
* numbers of wakeup pins.
|
||||
*/
|
||||
|
||||
enum stm32_pwr_wupin_e
|
||||
{
|
||||
PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */
|
||||
PWR_WUPIN_2, /* Wake-up pin 2 */
|
||||
PWR_WUPIN_3 /* Wake-up pin 3 */
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_initbkp
|
||||
*
|
||||
* Description:
|
||||
* Insures the referenced count access to the backup domain (RTC registers,
|
||||
* RTC backup data registers and backup SRAM is consistent with the HW state
|
||||
* without relying on a variable.
|
||||
*
|
||||
* NOTE: This function should only be called by SoC Start up code.
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - set the initial state of the enable and the
|
||||
* bkp_writable_counter
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_initbkp(bool writable);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables access to the backup domain (RTC registers, RTC backup data registers
|
||||
* and backup SRAM).
|
||||
*
|
||||
* NOTE: Reference counting is used in order to supported nested calls to this
|
||||
* function. As a consequence, every call to stm32_pwr_enablebkp(true) must
|
||||
* be followed by a matching call to stm32_pwr_enablebkp(false).
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablebkp(bool writable);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablewkup
|
||||
*
|
||||
* Description:
|
||||
* Enables the WKUP pin.
|
||||
*
|
||||
* Input Parameters:
|
||||
* wupin - Selects the WKUP pin to enable/disable
|
||||
* wupon - state to set it to
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned on any
|
||||
* failure. The only cause of failure is if the selected MCU does not support
|
||||
* the requested wakeup pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_getsbf
|
||||
*
|
||||
* Description:
|
||||
* Return the standby flag.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool stm32_pwr_getsbf(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_getwuf
|
||||
*
|
||||
* Description:
|
||||
* Return the wakeup flag.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool stm32_pwr_getwuf(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setvos
|
||||
*
|
||||
* Description:
|
||||
* Set voltage scaling for EnergyLite devices.
|
||||
*
|
||||
* Input Parameters:
|
||||
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic. If used
|
||||
* for any other purpose that protection to assure that its operation is atomic
|
||||
* will be required.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_ENERGYLITE
|
||||
void stm32_pwr_setvos(uint16_t vos);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setpvd
|
||||
*
|
||||
* Description:
|
||||
* Sets power voltage detector for EnergyLite devices.
|
||||
*
|
||||
* Input Parameters:
|
||||
* pls - PVD level
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_setpvd(uint16_t pls);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablepvd
|
||||
*
|
||||
* Description:
|
||||
* Enable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablepvd(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_disablepvd
|
||||
*
|
||||
* Description:
|
||||
* Disable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_disablepvd(void);
|
||||
|
||||
#endif /* CONFIG_STM32_ENERGYLITE */
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */
|
||||
@ -48,4 +48,24 @@
|
||||
|
||||
#include "hardware/stm32_rcc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Protoypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External Low-Speed (LSE) Oscillator.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H */
|
||||
|
||||
724
arch/arm/src/stm32f0l0/stm32l0_rcc.c
Normal file
724
arch/arm/src/stm32f0l0/stm32l0_rcc.c
Normal file
@ -0,0 +1,724 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0/stm32l0_rcc.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Allow up to 100 milliseconds for the high speed clock to become ready.
|
||||
* that is a very long delay, but if the clock does not become ready we are
|
||||
* hosed anyway. Normally this is very fast, but I have seen at least one
|
||||
* board that required this long, long timeout for the HSE to be ready.
|
||||
*/
|
||||
|
||||
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
/* HSE divisor to yield ~1MHz RTC clock (valid for HSE = 8MHz) */
|
||||
|
||||
#define HSE_DIVISOR RCC_CR_RTCPRE_HSEd8
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_reset
|
||||
*
|
||||
* Description:
|
||||
* Put all RCC registers in reset state
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_reset(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#if 1
|
||||
/* DBG clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_DBGEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableio
|
||||
*
|
||||
* Description:
|
||||
* Enable selected GPIO
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableio(void)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
/* REVISIT: */
|
||||
|
||||
regval |= (RCC_IOPENR_IOPAEN | RCC_IOPENR_IOPBEN | RCC_IOPENR_IOPCEN | \
|
||||
RCC_IOPENR_IOPDEN | RCC_IOPENR_IOPEEN | RCC_IOPENR_IOPHEN);
|
||||
|
||||
putreg32(regval, STM32_RCC_IOPENR); /* Enable GPIO */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableahb
|
||||
*
|
||||
* Description:
|
||||
* Enable selected AHB peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableahb(void)
|
||||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_DMA1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_MIF
|
||||
/* Memory interface clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_MIFEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_CRC
|
||||
/* CRC clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_CRCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TSC
|
||||
/* TSC clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_TSCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_RNG
|
||||
/* Random number generator clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_RNGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_CRYP
|
||||
/* Cryptographic modules clock enable */
|
||||
|
||||
regval |= RCC_AHBENR_CRYPEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB1ENR register to enabled the
|
||||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM2
|
||||
/* Timer 2 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM2EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM3
|
||||
/* Timer 3 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM3EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM6
|
||||
/* Timer 6 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM6EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM7
|
||||
/* Timer 7 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_TIM7EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_LCD
|
||||
/* LCD clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_LCDEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_WWDG
|
||||
/* Window Watchdog clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_WWDGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SPI2
|
||||
/* SPI 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART2
|
||||
/* USART 2 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_USART2EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART3
|
||||
/* USART 3 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_USART3EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_UART4
|
||||
/* USART 4 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_UART4EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_UART5
|
||||
/* USART 5 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_UART5EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_I2C1
|
||||
/* I2C 1 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_I2C1EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_I2C2
|
||||
/* I2C 2 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_I2C2EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USB
|
||||
/* USB clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USBEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_CRS
|
||||
/* Clock recovery system clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_CRSEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_PWR
|
||||
/* Power interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_DAC
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DACEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_I2C3
|
||||
/* I2C 3 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB1ENR_I2C4EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_LPTIM1
|
||||
/* LPTIM1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_LPTIM1EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SYSCFG
|
||||
/* SYSCFG clock */
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM21
|
||||
/* TIM21 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM21EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_TIM22
|
||||
/* TIM22 Timer clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_TIM10EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_ADC1
|
||||
/* ADC 1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_SPI1
|
||||
/* SPI 1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_USART1
|
||||
/* USART1 clock enable */
|
||||
|
||||
#ifdef CONFIG_STM32F0L0_FORCEPOWER
|
||||
regval |= RCC_APB2ENR_USART1EN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* DBG clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_DBGEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablehse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External High-Speed (HSE) Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
|
||||
static inline bool stm32_rcc_enablehse(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */
|
||||
regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */
|
||||
#else
|
||||
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
|
||||
#endif
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSERDY flag is set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then return TRUE */
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
/* In the case of a timeout starting the HSE, we really don't have a
|
||||
* strategy. This is almost always a hardware failure or misconfiguration.
|
||||
*/
|
||||
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h.
|
||||
*
|
||||
* NOTE: This logic would need to be extended if you need to select low-
|
||||
* power clocking modes or any clocking other than PLL driven by the HSE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
|
||||
static void stm32_stdclockconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
|
||||
uint16_t pwrcr;
|
||||
#endif
|
||||
uint32_t pwr_vos;
|
||||
bool flash_1ws;
|
||||
|
||||
/* Enable PWR clock from APB1 to give access to PWR_CR register */
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
/* Go to the high performance voltage range 1 if necessary. In this mode,
|
||||
* the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported.
|
||||
*
|
||||
* Range 1: PLLVCO up to 96MHz in range 1 (1.8V)
|
||||
* Range 2: PLLVCO up to 48MHz in range 2 (1.5V) (default)
|
||||
* Range 3: PLLVCO up to 24MHz in range 3 (1.2V)
|
||||
*
|
||||
* Range 1: SYSCLK up to 32Mhz
|
||||
* Range 2: SYSCLK up to 16Mhz
|
||||
* Range 3: SYSCLK up to 4.2Mhz
|
||||
*
|
||||
* Range 1: Flash 1WS if SYSCLK > 16Mhz
|
||||
* Range 2: Flash 1WS if SYSCLK > 8Mhz
|
||||
* Range 3: Flash 1WS if SYSCLK > 2.1Mhz
|
||||
*/
|
||||
|
||||
pwr_vos = PWR_CR_VOS_SCALE_2;
|
||||
flash_1ws = false;
|
||||
|
||||
#ifdef STM32_PLL_FREQUENCY
|
||||
if (STM32_PLL_FREQUENCY > 48000000)
|
||||
{
|
||||
pwr_vos = PWR_CR_VOS_SCALE_1;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (STM32_SYSCLK_FREQUENCY > 16000000)
|
||||
{
|
||||
pwr_vos = PWR_CR_VOS_SCALE_1;
|
||||
}
|
||||
|
||||
if ((pwr_vos == PWR_CR_VOS_SCALE_1 && STM32_SYSCLK_FREQUENCY > 16000000) ||
|
||||
(pwr_vos == PWR_CR_VOS_SCALE_2 && STM32_SYSCLK_FREQUENCY > 8000000))
|
||||
{
|
||||
flash_1ws = true;
|
||||
}
|
||||
|
||||
stm32_pwr_setvos(pwr_vos);
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
|
||||
/* If RTC / LCD selects HSE as clock source, the RTC prescaler
|
||||
* needs to be set before HSEON bit is set.
|
||||
*/
|
||||
|
||||
/* The RTC domain has write access denied after reset,
|
||||
* you have to enable write access using DBP bit in the PWR CR
|
||||
* register before to selecting the clock source ( and the PWR
|
||||
* peripheral must be enabled)
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
pwrcr = getreg16(STM32_PWR_CR);
|
||||
putreg16(pwrcr | PWR_CR_DBP, STM32_PWR_CR);
|
||||
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CSR);
|
||||
regval &= ~RCC_CSR_RTCSEL_MASK;
|
||||
regval |= RCC_CSR_RTCSEL_HSE;
|
||||
putreg32(regval, STM32_RCC_CSR);
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_RTCPRE_MASK;
|
||||
regval |= HSE_DIVISOR;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Restore the previous state of the DBP bit */
|
||||
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
#endif
|
||||
|
||||
/* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
|
||||
|
||||
#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
|
||||
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC))
|
||||
|
||||
/* The PLL is using the HSE, or the HSE is the system clock. In either
|
||||
* case, we need to enable HSE clocking.
|
||||
*/
|
||||
|
||||
if (!stm32_rcc_enablehse())
|
||||
{
|
||||
/* In the case of a timeout starting the HSE, we really don't have a
|
||||
* strategy. This is almost always a hardware failure or
|
||||
* misconfiguration (for example, if no crystal is fitted on the board.
|
||||
*/
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
|
||||
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
|
||||
|
||||
/* The PLL is using the HSI, or the HSI is the system clock. In either
|
||||
* case, we need to enable HSI clocking.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_CR); /* Enable the HSI */
|
||||
regval |= RCC_CR_HSION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI clock is ready. Since this is an internal clock, no
|
||||
* timeout is expected
|
||||
*/
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0);
|
||||
|
||||
#endif
|
||||
|
||||
#if (STM32_SYSCLK_SW != RCC_CFGR_SW_MSI)
|
||||
/* Increasing the CPU frequency (in the same voltage range):
|
||||
*
|
||||
* After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the
|
||||
* FLASH_ACR register. 32-bit access is enabled and prefetch is disabled.
|
||||
* ST strongly recommends to use the following software sequences to tune the
|
||||
* number of wait states needed to access the Flash memory with the CPU
|
||||
* frequency.
|
||||
*
|
||||
* - Program the 64-bit access by setting the ACC64 bit in Flash access
|
||||
* control register (FLASH_ACR)
|
||||
* - Check that 64-bit access is taken into account by reading FLASH_ACR
|
||||
* - Program 1 WS to the LATENCY bit in FLASH_ACR
|
||||
* - Check that the new number of WS is taken into account by reading FLASH_ACR
|
||||
* - Modify the CPU clock source by writing to the SW bits in the Clock
|
||||
* configuration register (RCC_CFGR)
|
||||
* - If needed, modify the CPU clock prescaler by writing to the HPRE bits in
|
||||
* RCC_CFGR
|
||||
* - Check that the new CPU clock source or/and the new CPU clock prescaler
|
||||
* value is/are taken into account by reading the clock source status (SWS
|
||||
* bits) or/and the AHB prescaler value (HPRE bits), respectively, in the
|
||||
* RCC_CFGR register
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_FLASH_ACR);
|
||||
regval |= FLASH_ACR_ACC64; /* 64-bit access mode */
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
if (flash_1ws)
|
||||
{
|
||||
regval |= FLASH_ACR_LATENCY; /* One wait state */
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~FLASH_ACR_LATENCY; /* Zero wait state */
|
||||
}
|
||||
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Enable FLASH prefetch */
|
||||
|
||||
regval |= FLASH_ACR_PRFTEN;
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
#endif /* STM32_SYSCLK_SW != RCC_CFGR_SW_MSI */
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* If we are using the PLL, configure and start it */
|
||||
|
||||
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
|
||||
|
||||
/* Set the PLL divider and multiplier. NOTE: The PLL needs to be disabled
|
||||
* to do these operation. We know this is the case here because pll_reset()
|
||||
* was previously called by stm32_clockconfig().
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK | RCC_CFGR_PLLDIV_MASK);
|
||||
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLMUL | STM32_CFGR_PLLDIV);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Enable the PLL */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
|
||||
|
||||
#endif
|
||||
|
||||
/* Select the system clock source (probably the PLL) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= STM32_SYSCLK_SW;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the selected source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_IWDG) || \
|
||||
defined(CONFIG_STM32F0L0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
|
||||
/* Low speed internal clock source LSI
|
||||
*
|
||||
* TODO: There is another case where the LSI needs to
|
||||
* be enabled: if the MCO pin selects LSI as source.
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F0L0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if the MCO pin selects LSE as source.
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if TIM9-10 Channel 1 selects LSE as input.
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if TIM10-11 selects LSE as ETR Input.
|
||||
*
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelse();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableperiphals
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableperipherals(void)
|
||||
{
|
||||
rcc_enableio();
|
||||
rcc_enableahb();
|
||||
rcc_enableapb2();
|
||||
rcc_enableapb1();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -861,6 +861,15 @@ config ARCH_BOARD_NUCLEO_144
|
||||
NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
|
||||
2048KiB Flash memory and 512KiB SRAM.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_L073RZ
|
||||
bool "STM32L073RZU6 Nucleo L073RZ"
|
||||
depends on ARCH_CHIP_STM32L073RZ
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
---help---
|
||||
STMicro Nucleo L073RZ board based on the STMicro STM32L073RZU6 MCU.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_L496ZG
|
||||
bool "STM32L496 Nucleo L496ZG"
|
||||
depends on ARCH_CHIP_STM32L496ZG
|
||||
@ -1399,6 +1408,15 @@ config ARCH_BOARD_STM32F746_WS
|
||||
---help---
|
||||
Waveshare STM32F746 development board featuring the STM32F746IG MCU.
|
||||
|
||||
config ARCH_BOARD_B_L072Z_LRWAN1
|
||||
bool "B-L072Z-LRWAN1"
|
||||
depends on ARCH_CHIP_STM32L072CZ
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
---help---
|
||||
STMicro STM32L0 Discovery kit with LoRa/SigFox based on STM32L072CZ MCU.
|
||||
|
||||
config ARCH_BOARD_B_L475E_IOT01A
|
||||
bool "STMicro IoT Discovery kit"
|
||||
depends on ARCH_CHIP_STM32L475VG
|
||||
@ -1818,6 +1836,7 @@ config ARCH_BOARD
|
||||
default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE
|
||||
default "nucleo-f410rb" if ARCH_BOARD_NUCLEO_F410RB
|
||||
default "nucleo-h743zi" if ARCH_BOARD_NUCLEO_H743ZI
|
||||
default "nucleo-l073rz" if ARCH_BOARD_NUCLEO_L073RZ
|
||||
default "nucleo-l152re" if ARCH_BOARD_NUCLEO_L152RE
|
||||
default "nucleo-l432kc" if ARCH_BOARD_NUCLEO_L432KC
|
||||
default "nucleo-l452re" if ARCH_BOARD_NUCLEO_L452RE
|
||||
@ -1881,6 +1900,7 @@ config ARCH_BOARD
|
||||
default "stm32f746g-disco" if ARCH_BOARD_STM32F746G_DISCO
|
||||
default "stm32f769i-disco" if ARCH_BOARD_STM32F769I_DISCO
|
||||
default "stm32f746-ws" if ARCH_BOARD_STM32F746_WS
|
||||
default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1
|
||||
default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A
|
||||
default "stm32l476vg-disco" if ARCH_BOARD_STM32L476VG_DISCO
|
||||
default "stm32l476-mdk" if ARCH_BOARD_STM32L476_MDK
|
||||
@ -2165,6 +2185,9 @@ endif
|
||||
if ARCH_BOARD_NUCLEO_H743ZI
|
||||
source "configs/nucleo-h743zi/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_NUCLEO_L073RZ
|
||||
source "configs/nucleo-l073rz/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_NUCLEO_L152RE
|
||||
source "configs/nucleo-l152re/Kconfig"
|
||||
endif
|
||||
@ -2342,6 +2365,9 @@ endif
|
||||
if ARCH_BOARD_STM32F769I_DISCO
|
||||
source "configs/stm32f769i-disco/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_B_L072Z_LRWAN1
|
||||
source "configs/b-l072z-lrwan1/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_B_L475E_IOT01A
|
||||
source "configs/b-l475e-iot01a/Kconfig"
|
||||
endif
|
||||
|
||||
@ -183,6 +183,9 @@ configs/avr32dev1
|
||||
Atmel website. STATUS: This port is functional but very basic. There
|
||||
are configurations for NSH and the OS test.
|
||||
|
||||
configs/b-l072z-lrwan1
|
||||
STMicro STM32L0 Discovery kit with LoRa/SigFox based on STM32L072CZ MCU.
|
||||
|
||||
configs/bambino-200e
|
||||
Micromint Bambino board. This board is based on the LPC4330FBD144.
|
||||
|
||||
@ -455,6 +458,9 @@ configs/nucleo-f410rb
|
||||
configs/nucleo-f303re
|
||||
STMicro ST Nucleo F303RE board. Contributed by Paul Alexander Patience.
|
||||
|
||||
configs/nucleo-l073rz
|
||||
STMicro STM32L0 Discovery kit with LoRa/SigFox based on STM32L072CZ MCU.
|
||||
|
||||
configs/nutiny-nuc120
|
||||
This is the port of NuttX to the NuvoTon NuTiny-SDK-NUC120 board. This
|
||||
board has the NUC120LE3AN chip with a built-in NuLink debugger.
|
||||
|
||||
8
configs/b-l072z-lrwan1/Kconfig
Normal file
8
configs/b-l072z-lrwan1/Kconfig
Normal file
@ -0,0 +1,8 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_B_L072Z_LRWAN1
|
||||
|
||||
endif
|
||||
2
configs/b-l072z-lrwan1/README.txt
Normal file
2
configs/b-l072z-lrwan1/README.txt
Normal file
@ -0,0 +1,2 @@
|
||||
B-L072Z-LRWAN1
|
||||
==============
|
||||
201
configs/b-l072z-lrwan1/include/board.h
Normal file
201
configs/b-l072z-lrwan1/include/board.h
Normal file
@ -0,0 +1,201 @@
|
||||
/****************************************************************************
|
||||
* configs/b-l072z-lrwan1/include/board.h
|
||||
* include/arch/board/board.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIG_B_L072Z_LRWAN1_INCLUDE_BOARD_H
|
||||
#define __CONFIG_B_L072Z_LRWAN1_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include <stdbool.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
/* HSI - Internal 8 MHz RC Oscillator
|
||||
* LSI - 32 KHz RC
|
||||
* HSE - 8 MHz from MCO output of ST-LINK
|
||||
* LSE - 32.768 kHz
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
#define STM32_HSEBYP_ENABLE
|
||||
#define STM32_HSI_FREQUENCY 8000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
|
||||
|
||||
/* PLL source is HSE/1, PLL multipler is 8: PLL frequency is 8MHz (XTAL) x 8 = 64MHz */
|
||||
|
||||
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
|
||||
#define STM32_CFGR_PLLXTPRE 0
|
||||
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8
|
||||
#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL)
|
||||
|
||||
/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */
|
||||
|
||||
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
|
||||
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
|
||||
#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2
|
||||
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (32MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (32MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
|
||||
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
|
||||
/* TODO: timers */
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2-1.
|
||||
* LD3 PWR: red LED indicates that the board is powered.
|
||||
*
|
||||
* And one can be controlled by software:
|
||||
*
|
||||
* User LD2: green LED is a user LED connected to the I/O PA5 of the
|
||||
* STM32LO73RZ.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
|
||||
* any way. The following definition is used to access the LED.
|
||||
*/
|
||||
|
||||
/* LED index values for use with board_userled() */
|
||||
|
||||
#define BOARD_LED1 0 /* User LD2 */
|
||||
#define BOARD_NLEDS 1
|
||||
|
||||
/* LED bits for use with board_userled_all() */
|
||||
|
||||
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
||||
|
||||
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
|
||||
* the Nucleo LO73RZ. The following definitions describe how NuttX controls
|
||||
* the LED:
|
||||
*
|
||||
* SYMBOL Meaning LED1 state
|
||||
* ------------------ ----------------------- ----------
|
||||
* LED_STARTED NuttX has been started OFF
|
||||
* LED_HEAPALLOCATE Heap has been allocated OFF
|
||||
* LED_IRQSENABLED Interrupts enabled OFF
|
||||
* LED_STACKCREATED Idle stack created ON
|
||||
* LED_INIRQ In an interrupt No change
|
||||
* LED_SIGNAL In a signal handler No change
|
||||
* LED_ASSERTION An assertion failed No change
|
||||
* LED_PANIC The system has crashed Blinking
|
||||
* LED_IDLE STM32 is is sleep mode Not used
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0
|
||||
#define LED_HEAPALLOCATE 0
|
||||
#define LED_IRQSENABLED 0
|
||||
#define LED_STACKCREATED 1
|
||||
#define LED_INIRQ 2
|
||||
#define LED_SIGNAL 2
|
||||
#define LED_ASSERTION 2
|
||||
#define LED_PANIC 1
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
/* The Nucleo LO73RZ supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ.
|
||||
* B2 RESET: push button connected to NRST is used to RESET the
|
||||
* STM32LO73RZ.
|
||||
*/
|
||||
|
||||
#define BUTTON_USER 0
|
||||
#define NUM_BUTTONS 1
|
||||
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
/* Alternate function pin selections ****************************************/
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
|
||||
/* USART */
|
||||
|
||||
/* By default the USART2 is connected to STLINK Virtual COM Port:
|
||||
* USART2_RX - PA3
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
|
||||
|
||||
/* COMP */
|
||||
|
||||
/* DMA channels *************************************************************/
|
||||
/* ADC */
|
||||
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */
|
||||
|
||||
#endif /* __CONFIG_NUCLEO_LO73RZ_INCLUDE_BOARD_H */
|
||||
52
configs/b-l072z-lrwan1/nsh/defconfig
Normal file
52
configs/b-l072z-lrwan1/nsh/defconfig
Normal file
@ -0,0 +1,52 @@
|
||||
# CONFIG_LIBC_LONG_LONG is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="b-l072z-lrwan1"
|
||||
CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y
|
||||
CONFIG_ARCH_CHIP_STM32L072CZ=y
|
||||
CONFIG_ARCH_CHIP_STM32L0=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=2796
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DISABLE_ENVIRON=y
|
||||
CONFIG_DISABLE_MOUNTPOINT=y
|
||||
CONFIG_DISABLE_MQUEUE=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_DISABLE_POSIX_TIMERS=y
|
||||
CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
|
||||
CONFIG_EXAMPLES_HELLO=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MAX_TASKS=8
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_NFILE_DESCRIPTORS=6
|
||||
CONFIG_NFILE_STREAMS=6
|
||||
CONFIG_NPTHREAD_KEYS=0
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=64
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_NUNGET_CHARS=0
|
||||
CONFIG_PREALLOC_TIMERS=0
|
||||
CONFIG_PREALLOC_WDOGS=4
|
||||
CONFIG_PTHREAD_MUTEX_UNSAFE=y
|
||||
CONFIG_PTHREAD_STACK_DEFAULT=1536
|
||||
CONFIG_RAM_SIZE=20480
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=19
|
||||
CONFIG_START_MONTH=5
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_STDIO_DISABLE_BUFFERING=y
|
||||
CONFIG_STM32F0L0_PWR=y
|
||||
CONFIG_STM32F0L0_USART2=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
|
||||
CONFIG_USART2_SERIAL_CONSOLE=y
|
||||
CONFIG_USERMAIN_STACKSIZE=1536
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=0
|
||||
114
configs/b-l072z-lrwan1/scripts/Make.defs
Normal file
114
configs/b-l072z-lrwan1/scripts/Make.defs
Normal file
@ -0,0 +1,114 @@
|
||||
############################################################################
|
||||
# configs/b-l072z-lrwan1/scripts/Make.defs
|
||||
#
|
||||
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
STRIP = $(CROSSDEV)strip --strip-unneeded
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ASMEXT = .S
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
|
||||
124
configs/b-l072z-lrwan1/scripts/ld.script
Normal file
124
configs/b-l072z-lrwan1/scripts/ld.script
Normal file
@ -0,0 +1,124 @@
|
||||
/****************************************************************************
|
||||
* configs/b-l072z-lrwan1/scripts/ld.script
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The STM32LO72CZ has 192Kb of FLASH beginning at address 0x0800:0000.
|
||||
* 20Kb of SRAM and 6Kb of EEPROM
|
||||
*
|
||||
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
|
||||
* where the code expects to begin execution by jumping to the entry point in
|
||||
* the 0x0800:0000 address range.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
EXTERN(_vectors)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
*(.init_array .init_array.*)
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
/* The RAM vector table (if present) should lie at the beginning of SRAM */
|
||||
|
||||
.ram_vectors : {
|
||||
*(.ram_vectors)
|
||||
} > sram
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
55
configs/b-l072z-lrwan1/src/Makefile
Normal file
55
configs/b-l072z-lrwan1/src/Makefile
Normal file
@ -0,0 +1,55 @@
|
||||
############################################################################
|
||||
# configs/b-l072z-lrwan1/src/Makefile
|
||||
#
|
||||
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
# Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
-include $(TOPDIR)/Make.defs
|
||||
|
||||
ASRCS =
|
||||
CSRCS = stm32_boot.c
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += stm32_autoleds.c
|
||||
else
|
||||
CSRCS += stm32_userleds.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += stm32_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinit.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
103
configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h
Normal file
103
configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h
Normal file
@ -0,0 +1,103 @@
|
||||
/****************************************************************************
|
||||
* configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_B_L072Z_LRWAN1_SRC_B_L072Z_LRWAN1_H
|
||||
#define __CONFIGS_B_L072Z_LRWAN1_SRC_B_L072Z_LRWAN1_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
/* The Nucleo L073RZ board has three LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2-1.
|
||||
* LD3 PWR: red LED indicates that the board is powered.
|
||||
*
|
||||
* And one can be controlled by software:
|
||||
*
|
||||
* User LD2: green LED is a user LED connected to the I/O PA5 of the
|
||||
* STM32L073RZT6.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
|
||||
* any way. The following definition is used to access the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH |\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTA | GPIO_PIN5)
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH | \
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_LED3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH | \
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_LED4 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH | \
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define LED_DRIVER_PATH "/dev/userleds"
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
/* The Nucleo L073RZ supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user button connected to the I/O PC13 of the STM32L073RZT6.
|
||||
* B2 RESET: push button connected to NRST is used to RESET the
|
||||
* STM32L073RZT6.
|
||||
*
|
||||
* NOTE that EXTI interrupts are configured.
|
||||
*/
|
||||
|
||||
#define MIN_IRQBUTTON BUTTON_USER
|
||||
#define MAX_IRQBUTTON BUTTON_USER
|
||||
#define NUM_IRQBUTTONS 1
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __CONFIGS_B_L072Z_LRWAN1_SRC_B_L072Z_LRWAN1_H */
|
||||
152
configs/b-l072z-lrwan1/src/stm32_appinit.c
Normal file
152
configs/b-l072z-lrwan1/src/stm32_appinit.c
Normal file
@ -0,0 +1,152 @@
|
||||
/****************************************************************************
|
||||
* configs/b-l072z-lrwan1/src/stm32_appinitialize.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/leds/userled.h>
|
||||
|
||||
#include "b-l072z-lrwan1.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#undef HAVE_LEDS
|
||||
#undef HAVE_DAC
|
||||
|
||||
#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
|
||||
# define HAVE_LEDS 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DAC)
|
||||
# define HAVE_DAC1 1
|
||||
# define HAVE_DAC2 1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_app_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform application specific initialization. This function is never
|
||||
* called directly from application code, but only indirectly via the
|
||||
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
|
||||
*
|
||||
* Input Parameters:
|
||||
* arg - The boardctl() argument is passed to the board_app_initialize()
|
||||
* implementation without modification. The argument has no
|
||||
* meaning to NuttX; the meaning of the argument is a contract
|
||||
* between the board-specific initalization logic and the
|
||||
* matching application logic. The value cold be such things as a
|
||||
* mode enumeration value, a set of DIP switch switch settings, a
|
||||
* pointer to configuration data read from a file or serial FLASH,
|
||||
* or whatever you would like to do with it. Every implementation
|
||||
* should accept zero/NULL as a default configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef HAVE_LEDS
|
||||
/* Register the LED driver */
|
||||
|
||||
ret = userled_lower_initialize(LED_DRIVER_PATH);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC driver. */
|
||||
|
||||
ret = stm32_adc_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DAC
|
||||
/* Initialize DAC and register the DAC driver. */
|
||||
|
||||
ret = stm32_dac_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_COMP
|
||||
/* Initialize COMP and register the COMP driver. */
|
||||
|
||||
ret = stm32_comp_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OPAMP
|
||||
/* Initialize OPAMP and register the OPAMP driver. */
|
||||
|
||||
ret = stm32_opamp_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
93
configs/b-l072z-lrwan1/src/stm32_autoleds.c
Normal file
93
configs/b-l072z-lrwan1/src/stm32_autoleds.c
Normal file
@ -0,0 +1,93 @@
|
||||
/****************************************************************************
|
||||
* configs/b-l072z-lrwan1/src/stm32_autoleds.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
#include "b-l072z-lrwan1.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_initialize
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_initialize(void)
|
||||
{
|
||||
/* Configure LED1 GPIO for output */
|
||||
|
||||
stm32_configgpio(GPIO_LED1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_on
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_on(int led)
|
||||
{
|
||||
if (led == BOARD_LED1)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_LED1, true);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_off
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_off(int led)
|
||||
{
|
||||
if (led == BOARD_LED1)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_LED1, false);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
87
configs/b-l072z-lrwan1/src/stm32_boot.c
Normal file
87
configs/b-l072z-lrwan1/src/stm32_boot.c
Normal file
@ -0,0 +1,87 @@
|
||||
/****************************************************************************
|
||||
* configs/b-l072z-lrwan1/src/stm32_boot.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "b-l072z-lrwan1.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following entry point. This
|
||||
* entry point is called early in the intitialization -- after all memory
|
||||
* has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_boardinitialize(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
}
|
||||
@ -74,7 +74,7 @@
|
||||
* - When the I/O is LOW, the LED is off.
|
||||
*/
|
||||
|
||||
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
@ -74,7 +74,7 @@
|
||||
* - When the I/O is LOW, the LED is off.
|
||||
*/
|
||||
|
||||
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
@ -87,7 +87,7 @@
|
||||
/* AHB clock (HCLK) is SYSCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (72MHz) */
|
||||
|
||||
@ -87,7 +87,7 @@
|
||||
/* AHB clock (HCLK) is SYSCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (72MHz) */
|
||||
@ -210,7 +210,7 @@
|
||||
|
||||
/* By default the USART2 is connected to STLINK Virtual COM Port:
|
||||
* USART2_RX - PA3
|
||||
* USART2_TX - PA4
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PA3 */
|
||||
|
||||
@ -62,12 +62,13 @@
|
||||
|
||||
/* HSI - Internal 8 MHz RC Oscillator
|
||||
* LSI - 32 KHz RC
|
||||
* HSE - On-board crystal frequency is 8MHz
|
||||
* HSE - 8 MHz from MCO output of ST-LINK
|
||||
* LSE - 32.768 kHz
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul /* X1 on board */
|
||||
|
||||
#define STM32_HSEBYP_ENABLE
|
||||
#define STM32_HSI_FREQUENCY 8000000ul
|
||||
#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
@ -89,7 +90,7 @@
|
||||
/* AHB clock (HCLK) is SYSCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (72MHz) */
|
||||
|
||||
@ -60,12 +60,13 @@
|
||||
|
||||
/* HSI - Internal 8 MHz RC Oscillator
|
||||
* LSI - 32 KHz RC
|
||||
* HSE - On-board crystal frequency is 8MHz
|
||||
* HSE - 8 MHz from MCO output of ST-LINK
|
||||
* LSE - 32.768 kHz
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul /* X1 on board */
|
||||
|
||||
#define STM32_HSEBYP_ENABLE
|
||||
#define STM32_HSI_FREQUENCY 8000000ul
|
||||
#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
@ -87,7 +88,7 @@
|
||||
/* AHB clock (HCLK) is SYSCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (72MHz) */
|
||||
|
||||
@ -87,7 +87,7 @@
|
||||
/* AHB clock (HCLK) is SYSCLK (72MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (72MHz) */
|
||||
@ -233,11 +233,11 @@
|
||||
|
||||
/* By default the USART2 is connected to STLINK Virtual COM Port:
|
||||
* USART2_RX - PA3
|
||||
* USART2_TX - PA4
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA4 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
|
||||
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
|
||||
|
||||
@ -9,7 +9,6 @@ CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP_STM32=y
|
||||
CONFIG_ARCH_CHIP_STM32F334R8=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_BUILTIN_PROXY_STACKSIZE=512
|
||||
|
||||
8
configs/nucleo-l073rz/Kconfig
Normal file
8
configs/nucleo-l073rz/Kconfig
Normal file
@ -0,0 +1,8 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_NUCLEO_L073RZ
|
||||
|
||||
endif
|
||||
26
configs/nucleo-l073rz/README.txt
Normal file
26
configs/nucleo-l073rz/README.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Nucleo-64 Boards
|
||||
================
|
||||
|
||||
The Nucleo-L073RZ is a member of the Nucleo-64 board family. The Nucleo-64
|
||||
is a standard board for use with several STM32 parts in the LQFP64 package.
|
||||
Variants include
|
||||
|
||||
Order code Targeted STM32
|
||||
------------- --------------
|
||||
NUCLEO-F030R8 STM32F030R8T6
|
||||
NUCLEO-F070RB STM32F070RBT6
|
||||
NUCLEO-F072RB STM32F072RBT6
|
||||
NUCLEO-F091RC STM32F091RCT6
|
||||
NUCLEO-F103RB STM32F103RBT6
|
||||
NUCLEO-F302R8 STM32F302R8T6
|
||||
NUCLEO-F303RE STM32F303RET6
|
||||
NUCLEO-F334R8 STM32F334R8T6
|
||||
NUCLEO-F401RE STM32F401RET6
|
||||
NUCLEO-F410RB STM32F410RBT6
|
||||
NUCLEO-F411RE STM32F411RET6
|
||||
NUCLEO-F446RE STM32F446RET6
|
||||
NUCLEO-L053R8 STM32L053R8T6
|
||||
NUCLEO-L073RZ STM32L073RZT6
|
||||
NUCLEO-L152RE STM32L152RET6
|
||||
NUCLEO-L452RE STM32L452RET6
|
||||
NUCLEO-L476RG STM32L476RGT6
|
||||
201
configs/nucleo-l073rz/include/board.h
Normal file
201
configs/nucleo-l073rz/include/board.h
Normal file
@ -0,0 +1,201 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-l073rz/include/board.h
|
||||
* include/arch/board/board.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIG_NUCLEO_L073RZ_INCLUDE_BOARD_H
|
||||
#define __CONFIG_NUCLEO_L073RZ_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include <stdbool.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
/* HSI - Internal 8 MHz RC Oscillator
|
||||
* LSI - 32 KHz RC
|
||||
* HSE - 8 MHz from MCO output of ST-LINK
|
||||
* LSE - 32.768 kHz
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
#define STM32_HSEBYP_ENABLE
|
||||
#define STM32_HSI_FREQUENCY 8000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
|
||||
|
||||
/* PLL source is HSE/1, PLL multipler is 8: PLL frequency is 8MHz (XTAL) x 8 = 64MHz */
|
||||
|
||||
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
|
||||
#define STM32_CFGR_PLLXTPRE 0
|
||||
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8
|
||||
#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL)
|
||||
|
||||
/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */
|
||||
|
||||
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
|
||||
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
|
||||
#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2
|
||||
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (32MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (32MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
|
||||
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
|
||||
/* TODO: timers */
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2-1.
|
||||
* LD3 PWR: red LED indicates that the board is powered.
|
||||
*
|
||||
* And one can be controlled by software:
|
||||
*
|
||||
* User LD2: green LED is a user LED connected to the I/O PA5 of the
|
||||
* STM32LO73RZ.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
|
||||
* any way. The following definition is used to access the LED.
|
||||
*/
|
||||
|
||||
/* LED index values for use with board_userled() */
|
||||
|
||||
#define BOARD_LED1 0 /* User LD2 */
|
||||
#define BOARD_NLEDS 1
|
||||
|
||||
/* LED bits for use with board_userled_all() */
|
||||
|
||||
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
||||
|
||||
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
|
||||
* the Nucleo LO73RZ. The following definitions describe how NuttX controls
|
||||
* the LED:
|
||||
*
|
||||
* SYMBOL Meaning LED1 state
|
||||
* ------------------ ----------------------- ----------
|
||||
* LED_STARTED NuttX has been started OFF
|
||||
* LED_HEAPALLOCATE Heap has been allocated OFF
|
||||
* LED_IRQSENABLED Interrupts enabled OFF
|
||||
* LED_STACKCREATED Idle stack created ON
|
||||
* LED_INIRQ In an interrupt No change
|
||||
* LED_SIGNAL In a signal handler No change
|
||||
* LED_ASSERTION An assertion failed No change
|
||||
* LED_PANIC The system has crashed Blinking
|
||||
* LED_IDLE STM32 is is sleep mode Not used
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0
|
||||
#define LED_HEAPALLOCATE 0
|
||||
#define LED_IRQSENABLED 0
|
||||
#define LED_STACKCREATED 1
|
||||
#define LED_INIRQ 2
|
||||
#define LED_SIGNAL 2
|
||||
#define LED_ASSERTION 2
|
||||
#define LED_PANIC 1
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
/* The Nucleo LO73RZ supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user button connected to the I/O PC13 of the STM32LO73RZ.
|
||||
* B2 RESET: push button connected to NRST is used to RESET the
|
||||
* STM32LO73RZ.
|
||||
*/
|
||||
|
||||
#define BUTTON_USER 0
|
||||
#define NUM_BUTTONS 1
|
||||
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
/* Alternate function pin selections ****************************************/
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
|
||||
/* USART */
|
||||
|
||||
/* By default the USART2 is connected to STLINK Virtual COM Port:
|
||||
* USART2_RX - PA3
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
|
||||
|
||||
/* COMP */
|
||||
|
||||
/* DMA channels *************************************************************/
|
||||
/* ADC */
|
||||
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */
|
||||
|
||||
#endif /* __CONFIG_NUCLEO_LO73RZ_INCLUDE_BOARD_H */
|
||||
52
configs/nucleo-l073rz/nsh/defconfig
Normal file
52
configs/nucleo-l073rz/nsh/defconfig
Normal file
@ -0,0 +1,52 @@
|
||||
# CONFIG_LIBC_LONG_LONG is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-l073rz"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y
|
||||
CONFIG_ARCH_CHIP_STM32L073RZ=y
|
||||
CONFIG_ARCH_CHIP_STM32L0=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=2796
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DISABLE_ENVIRON=y
|
||||
CONFIG_DISABLE_MOUNTPOINT=y
|
||||
CONFIG_DISABLE_MQUEUE=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_DISABLE_POSIX_TIMERS=y
|
||||
CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
|
||||
CONFIG_EXAMPLES_HELLO=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MAX_TASKS=8
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_NFILE_DESCRIPTORS=6
|
||||
CONFIG_NFILE_STREAMS=6
|
||||
CONFIG_NPTHREAD_KEYS=0
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=64
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_NUNGET_CHARS=0
|
||||
CONFIG_PREALLOC_TIMERS=0
|
||||
CONFIG_PREALLOC_WDOGS=4
|
||||
CONFIG_PTHREAD_MUTEX_UNSAFE=y
|
||||
CONFIG_PTHREAD_STACK_DEFAULT=1536
|
||||
CONFIG_RAM_SIZE=20480
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_START_DAY=19
|
||||
CONFIG_START_MONTH=5
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_STDIO_DISABLE_BUFFERING=y
|
||||
CONFIG_STM32F0L0_PWR=y
|
||||
CONFIG_STM32F0L0_USART2=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
|
||||
CONFIG_USART2_SERIAL_CONSOLE=y
|
||||
CONFIG_USERMAIN_STACKSIZE=1536
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=0
|
||||
114
configs/nucleo-l073rz/scripts/Make.defs
Normal file
114
configs/nucleo-l073rz/scripts/Make.defs
Normal file
@ -0,0 +1,114 @@
|
||||
############################################################################
|
||||
# configs/nucleo-l073rz/scripts/Make.defs
|
||||
#
|
||||
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
STRIP = $(CROSSDEV)strip --strip-unneeded
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ASMEXT = .S
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
|
||||
124
configs/nucleo-l073rz/scripts/ld.script
Normal file
124
configs/nucleo-l073rz/scripts/ld.script
Normal file
@ -0,0 +1,124 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-l073rz/scripts/ld.script
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The STM32LO73RZ has 192Kb of FLASH beginning at address 0x0800:0000.
|
||||
* 20Kb of SRAM and 6Kb of EEPROM
|
||||
*
|
||||
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
|
||||
* where the code expects to begin execution by jumping to the entry point in
|
||||
* the 0x0800:0000 address range.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
EXTERN(_vectors)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
*(.init_array .init_array.*)
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
/* The RAM vector table (if present) should lie at the beginning of SRAM */
|
||||
|
||||
.ram_vectors : {
|
||||
*(.ram_vectors)
|
||||
} > sram
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
55
configs/nucleo-l073rz/src/Makefile
Normal file
55
configs/nucleo-l073rz/src/Makefile
Normal file
@ -0,0 +1,55 @@
|
||||
############################################################################
|
||||
# configs/nucleo-l073rz/src/Makefile
|
||||
#
|
||||
# Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
# Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
-include $(TOPDIR)/Make.defs
|
||||
|
||||
ASRCS =
|
||||
CSRCS = stm32_boot.c
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += stm32_autoleds.c
|
||||
else
|
||||
CSRCS += stm32_userleds.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += stm32_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinit.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/configs/Board.mk
|
||||
98
configs/nucleo-l073rz/src/nucleo-l073rz.h
Normal file
98
configs/nucleo-l073rz/src/nucleo-l073rz.h
Normal file
@ -0,0 +1,98 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-l073rz/src/nucleo-l073rz.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_NUCLEO_L073RZ_SRC_NUCLEO_L073RZ_H
|
||||
#define __CONFIGS_NUCLEO_L073RZ_SRC_NUCLEO_L073RZ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
/* The Nucleo L073RZ board has three LEDs. Two of these are controlled by
|
||||
* logic on the board and are not available for software control:
|
||||
*
|
||||
* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
|
||||
* communications are in progress between the PC and the
|
||||
* ST-LINK/V2-1.
|
||||
* LD3 PWR: red LED indicates that the board is powered.
|
||||
*
|
||||
* And one can be controlled by software:
|
||||
*
|
||||
* User LD2: green LED is a user LED connected to the I/O PA5 of the
|
||||
* STM32L073RZT6.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
|
||||
* any way. The following definition is used to access the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
|
||||
|
||||
#define LED_DRIVER_PATH "/dev/userleds"
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
/* The Nucleo L073RZ supports two buttons; only one button is controllable
|
||||
* by software:
|
||||
*
|
||||
* B1 USER: user button connected to the I/O PC13 of the STM32L073RZT6.
|
||||
* B2 RESET: push button connected to NRST is used to RESET the
|
||||
* STM32L073RZT6.
|
||||
*
|
||||
* NOTE that EXTI interrupts are configured.
|
||||
*/
|
||||
|
||||
#define MIN_IRQBUTTON BUTTON_USER
|
||||
#define MAX_IRQBUTTON BUTTON_USER
|
||||
#define NUM_IRQBUTTONS 1
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | \
|
||||
GPIO_PIN13)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __CONFIGS_NUCLEO_L073RZ_SRC_NUCLEO_L073RZ_H */
|
||||
152
configs/nucleo-l073rz/src/stm32_appinit.c
Normal file
152
configs/nucleo-l073rz/src/stm32_appinit.c
Normal file
@ -0,0 +1,152 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-l073rz/src/stm32_appinitialize.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/leds/userled.h>
|
||||
|
||||
#include "nucleo-l073rz.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#undef HAVE_LEDS
|
||||
#undef HAVE_DAC
|
||||
|
||||
#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
|
||||
# define HAVE_LEDS 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DAC)
|
||||
# define HAVE_DAC1 1
|
||||
# define HAVE_DAC2 1
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_app_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform application specific initialization. This function is never
|
||||
* called directly from application code, but only indirectly via the
|
||||
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
|
||||
*
|
||||
* Input Parameters:
|
||||
* arg - The boardctl() argument is passed to the board_app_initialize()
|
||||
* implementation without modification. The argument has no
|
||||
* meaning to NuttX; the meaning of the argument is a contract
|
||||
* between the board-specific initalization logic and the
|
||||
* matching application logic. The value cold be such things as a
|
||||
* mode enumeration value, a set of DIP switch switch settings, a
|
||||
* pointer to configuration data read from a file or serial FLASH,
|
||||
* or whatever you would like to do with it. Every implementation
|
||||
* should accept zero/NULL as a default configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef HAVE_LEDS
|
||||
/* Register the LED driver */
|
||||
|
||||
ret = userled_lower_initialize(LED_DRIVER_PATH);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC driver. */
|
||||
|
||||
ret = stm32_adc_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DAC
|
||||
/* Initialize DAC and register the DAC driver. */
|
||||
|
||||
ret = stm32_dac_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_COMP
|
||||
/* Initialize COMP and register the COMP driver. */
|
||||
|
||||
ret = stm32_comp_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OPAMP
|
||||
/* Initialize OPAMP and register the OPAMP driver. */
|
||||
|
||||
ret = stm32_opamp_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
93
configs/nucleo-l073rz/src/stm32_autoleds.c
Normal file
93
configs/nucleo-l073rz/src/stm32_autoleds.c
Normal file
@ -0,0 +1,93 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-l073rz/src/stm32_autoleds.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
#include "nucleo-l073rz.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_initialize
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_initialize(void)
|
||||
{
|
||||
/* Configure LED1 GPIO for output */
|
||||
|
||||
stm32_configgpio(GPIO_LED1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_on
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_on(int led)
|
||||
{
|
||||
if (led == BOARD_LED1)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_LED1, true);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_off
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_off(int led)
|
||||
{
|
||||
if (led == BOARD_LED1)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_LED1, false);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
87
configs/nucleo-l073rz/src/stm32_boot.c
Normal file
87
configs/nucleo-l073rz/src/stm32_boot.c
Normal file
@ -0,0 +1,87 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-l073rz/src/stm32_boot.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nucleo-l073rz.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following entry point. This
|
||||
* entry point is called early in the intitialization -- after all memory
|
||||
* has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_boardinitialize(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
}
|
||||
@ -219,7 +219,7 @@
|
||||
|
||||
/* By default the USART2 is connected to STLINK Virtual COM Port:
|
||||
* USART2_RX - PA3
|
||||
* USART2_TX - PA4
|
||||
* USART2_TX - PA2
|
||||
*/
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
|
||||
|
||||
@ -81,9 +81,9 @@
|
||||
* The other side of the LED connects to ground so high value will illuminate the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN9)
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN8)
|
||||
|
||||
/* Button definitions *******************************************************************************/
|
||||
|
||||
@ -83,13 +83,13 @@
|
||||
* The other side of the LED connects to ground so high value will illuminate the LED.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN6)
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN7)
|
||||
#define GPIO_LED3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LED3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN8)
|
||||
#define GPIO_LED4 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
|
||||
#define GPIO_LED4 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_MEDIUM | \
|
||||
GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN9)
|
||||
|
||||
/* Button definitions *******************************************************************************/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user