sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge remote-tracking branch 'origin/master'

Browse Source
This commit is contained in:
Lok Tep 2016-05-24 23:23:57 +02:00
commit 4c96755219
24 changed files with 7069 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/stm32f7/Make.defs
View File

@ -114,7 +114,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
CHIP_CSRCS += stm32_start.c
CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c

52
arch/arm/src/stm32f7/chip/stm32_i2c.h Normal file
View File

@ -0,0 +1,52 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_i2c.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_i2c.h"
#else
# error "Unsupported STM32 F7 part"
#endif
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */

52
arch/arm/src/stm32f7/chip/stm32_spi.h Normal file
View File

@ -0,0 +1,52 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_spi.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include "chip/stm32f74xx75xx_spi.h"
#else
# error "Unsupported STM32 F7 part"
#endif
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */

249
arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h Normal file
View File

@ -0,0 +1,249 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
#define __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32F7_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32F7_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define STM32F7_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define STM32F7_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define STM32F7_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
#define STM32F7_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define STM32F7_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
#define STM32F7_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
#define STM32F7_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
#define STM32F7_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define STM32F7_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses ***************************************************************/
#if STM32F7_NI2C > 0
# define STM32F7_I2C1_CR1 (STM32F7_I2C1_BASE+STM32F7_I2C_CR1_OFFSET)
# define STM32F7_I2C1_CR2 (STM32F7_I2C1_BASE+STM32F7_I2C_CR2_OFFSET)
# define STM32F7_I2C1_OAR1 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR1_OFFSET)
# define STM32F7_I2C1_OAR2 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR2_OFFSET)
# define STM32F7_I2C1_TIMINGR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMINGR_OFFSET)
# define STM32F7_I2C1_TIMEOUTR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
# define STM32F7_I2C1_ISR (STM32F7_I2C1_BASE+STM32F7_I2C_ISR_OFFSET)
# define STM32F7_I2C1_ICR (STM32F7_I2C1_BASE+STM32F7_I2C_ICR_OFFSET)
# define STM32F7_I2C1_PECR (STM32F7_I2C1_BASE+STM32F7_I2C_PECR_OFFSET)
# define STM32F7_I2C1_RXDR (STM32F7_I2C1_BASE+STM32F7_I2C_RXDR_OFFSET)
# define STM32F7_I2C1_TXDR (STM32F7_I2C1_BASE+STM32F7_I2C_TXDR_OFFSET)
#endif
#if STM32F7_NI2C > 1
# define STM32F7_I2C2_CR1 (STM32F7_I2C2_BASE+STM32F7_I2C_CR1_OFFSET)
# define STM32F7_I2C2_CR2 (STM32F7_I2C2_BASE+STM32F7_I2C_CR2_OFFSET)
# define STM32F7_I2C2_OAR1 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR1_OFFSET)
# define STM32F7_I2C2_OAR2 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR2_OFFSET)
# define STM32F7_I2C2_TIMINGR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMINGR_OFFSET)
# define STM32F7_I2C2_TIMEOUTR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
# define STM32F7_I2C2_ISR (STM32F7_I2C2_BASE+STM32F7_I2C_ISR_OFFSET)
# define STM32F7_I2C2_ICR (STM32F7_I2C2_BASE+STM32F7_I2C_ICR_OFFSET)
# define STM32F7_I2C2_PECR (STM32F7_I2C2_BASE+STM32F7_I2C_PECR_OFFSET)
# define STM32F7_I2C2_RXDR (STM32F7_I2C2_BASE+STM32F7_I2C_RXDR_OFFSET)
# define STM32F7_I2C2_TXDR (STM32F7_I2C2_BASE+STM32F7_I2C_TXDR_OFFSET)
#endif
#if STM32F7_NI2C > 2
# define STM32F7_I2C3_CR1 (STM32F7_I2C3_BASE+STM32F7_I2C_CR1_OFFSET)
# define STM32F7_I2C3_CR2 (STM32F7_I2C3_BASE+STM32F7_I2C_CR2_OFFSET)
# define STM32F7_I2C3_OAR1 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR1_OFFSET)
# define STM32F7_I2C3_OAR2 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR2_OFFSET)
# define STM32F7_I2C3_TIMINGR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMINGR_OFFSET)
# define STM32F7_I2C3_TIMEOUTR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
# define STM32F7_I2C3_ISR (STM32F7_I2C3_BASE+STM32F7_I2C_ISR_OFFSET)
# define STM32F7_I2C3_ICR (STM32F7_I2C3_BASE+STM32F7_I2C_ICR_OFFSET)
# define STM32F7_I2C3_PECR (STM32F7_I2C3_BASE+STM32F7_I2C_PECR_OFFSET)
# define STM32F7_I2C3_RXDR (STM32F7_I2C3_BASE+STM32F7_I2C_RXDR_OFFSET)
# define STM32F7_I2C3_TXDR (STM32F7_I2C3_BASE+STM32F7_I2C_TXDR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* Control register 1 */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
/* Control register 2 */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
/* Own address register 1 */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
/* Own address register 2 */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
/* Timeout register */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
/* Fields unique to the Interrupt and Status register */
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
/* Packet error checking register */
#define I2C_PECR_MASK (0xff)
/* Receive data register */
#define I2C_RXDR_MASK (0xff)
/* Transmit data register */
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */

207
arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h Normal file
View File

@ -0,0 +1,207 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f7_spi.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Maximum allowed speed as per specifications for all SPIs */
#define STM32F7_SPI_CLK_MAX 27000000UL
/* Register Offsets *****************************************************************/
#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
/* Register Addresses ***************************************************************/
#if STM32F7_NSPI > 0
# define STM32F7_SPI1_CR1 (STM32_SPI1_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI1_CR2 (STM32_SPI1_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI1_SR (STM32_SPI1_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI1_DR (STM32_SPI1_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI1_CRCPR (STM32_SPI1_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI1_RXCRCR (STM32_SPI1_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI1_TXCRCR (STM32_SPI1_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 1
# define STM32F7_SPI2_CR1 (STM32_SPI2_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI2_CR2 (STM32_SPI2_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI2_SR (STM32_SPI2_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI2_DR (STM32_SPI2_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI2_CRCPR (STM32_SPI2_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI2_RXCRCR (STM32_SPI2_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI2_TXCRCR (STM32_SPI2_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 2
# define STM32F7_SPI3_CR1 (STM32_SPI3_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI3_CR2 (STM32_SPI3_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI3_SR (STM32_SPI3_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI3_DR (STM32_SPI3_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI3_CRCPR (STM32_SPI3_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI3_RXCRCR (STM32_SPI3_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI3_TXCRCR (STM32_SPI3_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 3
# define STM32F7_SPI4_CR1 (STM32_SPI4_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI4_CR2 (STM32_SPI4_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI4_SR (STM32_SPI4_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI4_DR (STM32_SPI4_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI4_CRCPR (STM32_SPI4_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI4_RXCRCR (STM32_SPI4_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI4_TXCRCR (STM32_SPI4_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 4
# define STM32F7_SPI5_CR1 (STM32_SPI5_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI5_CR2 (STM32_SPI5_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI5_SR (STM32_SPI5_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI5_DR (STM32_SPI5_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI5_CRCPR (STM32_SPI5_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI5_RXCRCR (STM32_SPI5_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI5_TXCRCR (STM32_SPI5_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
#if STM32F7_NSPI > 5
# define STM32F7_SPI6_CR1 (STM32_SPI6_BASE+STM32F7_SPI_CR1_OFFSET)
# define STM32F7_SPI6_CR2 (STM32_SPI6_BASE+STM32F7_SPI_CR2_OFFSET)
# define STM32F7_SPI6_SR (STM32_SPI6_BASE+STM32F7_SPI_SR_OFFSET)
# define STM32F7_SPI6_DR (STM32_SPI6_BASE+STM32F7_SPI_DR_OFFSET)
# define STM32F7_SPI6_CRCPR (STM32_SPI6_BASE+STM32F7_SPI_CRCPR_OFFSET)
# define STM32F7_SPI6_RXCRCR (STM32_SPI6_BASE+STM32F7_SPI_RXCRCR_OFFSET)
# define STM32F7_SPI6_TXCRCR (STM32_SPI6_BASE+STM32F7_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* SPI Control Register 1 */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
/* SPI Control Register 2 */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_VAL(bits) ( ((bits)-1) << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
/* SPI status register */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */

2058
arch/arm/src/stm32f7/stm32_i2c.c Normal file
View File

File diff suppressed because it is too large Load Diff

104
arch/arm/src/stm32f7/stm32_i2c.h Normal file
View File

@ -0,0 +1,104 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_i2c.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H
#define __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
#include "chip/stm32_i2c.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F7_I2C_DYNTIMEO
# endif
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32f7_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameter:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on succcess; a NULL on failure
*
****************************************************************************/
FAR struct i2c_master_s *stm32f7_i2cbus_initialize(int port);
/****************************************************************************
* Name: stm32f7_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the stm32f7_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int stm32f7_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_STM32F7_STM32F7_I2C_H */

1846
arch/arm/src/stm32f7/stm32_spi.c Normal file
View File

File diff suppressed because it is too large Load Diff

122
arch/arm/src/stm32f7/stm32_spi.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_spi.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32F7_STM32_SPI_H
#define __ARCH_ARM_STC_STM32F7_STM32_SPI_H
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F7_STM32_SPI_H
/************************************************************************************
* Included Files
@ -42,13 +42,11 @@
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
//#include "chip/stm32_spi.h"
#include "chip/stm32_spi.h"
/************************************************************************************
* Public Functions
* Pre-processor Definitions
************************************************************************************/
#ifndef __ASSEMBLY__
@ -62,11 +60,19 @@ extern "C"
#define EXTERN extern
#endif
struct spi_dev_s; /* Forward reference */
enum spi_dev_e; /* Forward reference */
/************************************************************************************
* Public Data
************************************************************************************/
struct spi_dev_s;
enum spi_dev_e;
/************************************************************************************
* Name: stm32_spibus_initialize
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32f7_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
@ -79,75 +85,75 @@ enum spi_dev_e; /* Forward reference */
*
************************************************************************************/
FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
FAR struct spi_dev_s *stm32f7_spibus_initialize(int bus);
/************************************************************************************
* Name: stm32_spi1/2/...select and stm32_spi1/2/...status
* Name: stm32f7_spi1/2/...select and stm32f7_spi1/2/...status
*
* Description:
* The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, and
* stm32_spi1/2/...cmddata must be provided by board-specific logic. These are
* The external functions, stm32f7_spi1/2/...select, stm32f7_spi1/2/...status, and
* stm32f7_spi1/2/...cmddata must be provided by board-specific logic. These are
* implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
* (including stm32_spibus_initialize()) are provided by common STM32 logic. To use this
* (including stm32f7_spibus_initialize()) are provided by common STM32 logic. To use this
* common SPI logic on your board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* 1. Provide logic in stm32f7_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() functions in your
* 2. Provide stm32f7_spi1/2/...select() and stm32f7_spi1/2/...status() functions in your
* board-specific logic. These functions will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then
* provide stm32_spi1/2/...cmddata() functions in your board-specific logic.
* provide stm32f7_spi1/2/...cmddata() functions in your board-specific logic.
* These functions will perform cmd/data selection operations using GPIOs in the
* way your board is configured.
* 4. Add a calls to stm32_spibus_initialize() in your low level application
* 4. Add a calls to stm32f7_spibus_initialize() in your low level application
* initialization logic
* 5. The handle returned by stm32_spibus_initialize() may then be used to bind the
* 5. The handle returned by stm32f7_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#ifdef CONFIG_STM32F7_SPI1
void stm32f7_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32f7_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32f7_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#ifdef CONFIG_STM32F7_SPI2
void stm32f7_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32f7_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32f7_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#ifdef CONFIG_STM32F7_SPI3
void stm32f7_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32f7_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32f7_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#ifdef CONFIG_STM32_SPI4
void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#ifdef CONFIG_STM32F7_SPI4
void stm32f7_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32f7_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32f7_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#ifdef CONFIG_STM32_SPI5
void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#ifdef CONFIG_STM32F7_SPI5
void stm32f7_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32f7_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32f7_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#ifdef CONFIG_STM32_SPI6
void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#ifdef CONFIG_STM32F7_SPI6
void stm32f7_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
uint8_t stm32f7_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
int stm32f7_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
/************************************************************************************
* Name: stm32_spi1/2/...register
* Name: stm32f7_spi1/2/...register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based MMC/SD
@ -167,33 +173,33 @@ int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32_SPI1
int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#ifdef CONFIG_STM32F7_SPI1
int stm32f7_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32_SPI2
int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#ifdef CONFIG_STM32F7_SPI2
int stm32f7_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32_SPI3
int stm32_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#ifdef CONFIG_STM32F7_SPI3
int stm32f7_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32_SPI4
int stm32_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#ifdef CONFIG_STM32F7_SPI4
int stm32f7_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32_SPI5
int stm32_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#ifdef CONFIG_STM32F7_SPI5
int stm32f7_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32_SPI6
int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#ifdef CONFIG_STM32F7_SPI6
int stm32f7_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#endif
@ -204,5 +210,5 @@ int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32F7_STM32_SPI_H */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_SPI_H */

8
configs/stm32f746-ws/Kconfig Normal file
View File

@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_STM32F746_WS
endif # ARCH_BOARD_STM32F746_WS

244
configs/stm32f746-ws/include/board.h Normal file
View File

@ -0,0 +1,244 @@
/************************************************************************************
* configs/stm32f746-ws/include/board.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Author: Mark Olsson <post@markolsson.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIG_STM32F746_WS_INCLUDE_BOARD_H
#define __CONFIG_STM32F746_WS_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#ifdef __KERNEL__
#include "stm32_rcc.h"
#ifdef CONFIG_STM32F7_SDMMC1
# include "stm32_sdmmc.h"
#endif
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocking *************************************************************************/
/* The STM32F7 Discovery board provides the following clock sources:
*
* X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board)
* X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY.
* X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC
*
* So we have these clock source available within the STM32
*
* HSI: 16 MHz RC factory-trimmed
* LSI: 32 KHz RC
* HSE: On-board crystal frequency is 25MHz
* LSE: 32.768 kHz
*/
#define STM32_BOARD_XTAL 8000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768
/* Main PLL Configuration.
*
* PLL source is HSE = 8,000,000
*
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* Subject to:
*
* 2 <= PLLM <= 63
* 192 <= PLLN <= 432
* 192 MHz <= PLL_VCO <= 432MHz
*
* SYSCLK = PLL_VCO / PLLP
* Subject to
*
* PLLP = {2, 4, 6, 8}
* SYSCLK <= 216 MHz
*
* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
* Subject to
* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
* and the random number generator need a frequency lower than or equal
* to 48 MHz to work correctly.
*
* 2 <= PLLQ <= 15
*/
/* Highest SYSCLK with USB OTG FS clock <= 48MHz
*
* PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz
* SYSCLK = 432 MHz / 2 = 216 MHz
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432)
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
/* Several prescalers allow the configuration of the two AHB buses, the
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
* the low-speed APB domain is 54 MHz.
*/
/* AHB clock (HCLK) is SYSCLK (216 MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB2 will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* FLASH wait states
*
* --------- ---------- -----------
* VDD MAX SYSCLK WAIT STATES
* --------- ---------- -----------
* 1.7-2.1 V 180 MHz 8
* 2.1-2.4 V 216 MHz 9
* 2.4-2.7 V 216 MHz 8
* 2.7-3.6 V 216 MHz 7
* --------- ---------- -----------
*/
#define BOARD_FLASH_WAITSTATES 7
/* Alternate function pin selections ************************************************/
/* USART6:
*
* These configurations assume that you are using a standard Arduio RS-232 shield
* with the serial interface with RX on pin D0 and TX on pin D1:
*
* -------- ---------------
* STM32F7
* ARDUIONO FUNCTION GPIO
* -- ----- --------- -----
* DO RX USART6_RX PC7
* D1 TX USART6_TX PC6
* -- ----- --------- -----
*/
#define GPIO_USART6_RX GPIO_USART6_RX_1
#define GPIO_USART6_TX GPIO_USART6_TX_1
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32_boardinitialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIG_STM32F746_WS_INCLUDE_BOARD_H */

113
configs/stm32f746-ws/nsh/Make.defs Normal file
View File

@ -0,0 +1,113 @@
############################################################################
# configs/stm32f746-ws/nsh/Make.defs
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = flash.ld
ifeq ($(WINTOOL),y)
# Windows-native toolchains
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
AR = $(ARCROSSDEV)ar rcs
NM = $(ARCROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ARCHCFLAGS = -fno-builtin
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHDEFINES =
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
ASMEXT = .S
OBJEXT = .o
LIBEXT = .a
EXEEXT =
ifneq ($(CROSSDEV),arm-nuttx-elf-)
LDFLAGS += -nostartfiles -nodefaultlibs
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

917
configs/stm32f746-ws/nsh/defconfig Normal file
View File

@ -0,0 +1,917 @@
#
# Automatically generated file; DO NOT EDIT.
# Nuttx/ Configuration
#
#
# Build Setup
#
# CONFIG_EXPERIMENTAL is not set
# CONFIG_DEFAULT_SMALL is not set
CONFIG_HOST_LINUX=y
# CONFIG_HOST_OSX is not set
# CONFIG_HOST_WINDOWS is not set
# CONFIG_HOST_OTHER is not set
#
# Build Configuration
#
CONFIG_APPS_DIR="../apps"
CONFIG_BUILD_FLAT=y
# CONFIG_BUILD_2PASS is not set
#
# Binary Output Formats
#
# CONFIG_RRLOAD_BINARY is not set
CONFIG_INTELHEX_BINARY=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
#
# Customize Header Files
#
# CONFIG_ARCH_STDINT_H is not set
# CONFIG_ARCH_STDBOOL_H is not set
# CONFIG_ARCH_MATH_H is not set
# CONFIG_ARCH_FLOAT_H is not set
CONFIG_ARCH_STDARG_H=y
# CONFIG_ARCH_DEBUG_H is not set
#
# Debug Options
#
# CONFIG_DEBUG is not set
CONFIG_ARCH_HAVE_HEAPCHECK=y
CONFIG_ARCH_HAVE_STACKCHECK=y
# CONFIG_STACK_COLORATION is not set
CONFIG_DEBUG_SYMBOLS=y
CONFIG_ARCH_HAVE_CUSTOMOPT=y
CONFIG_DEBUG_NOOPT=y
# CONFIG_DEBUG_CUSTOMOPT is not set
# CONFIG_DEBUG_FULLOPT is not set
#
# System Type
#
CONFIG_ARCH_ARM=y
# CONFIG_ARCH_AVR is not set
# CONFIG_ARCH_HC is not set
# CONFIG_ARCH_MIPS is not set
# CONFIG_ARCH_RGMP is not set
# CONFIG_ARCH_SH is not set
# CONFIG_ARCH_SIM is not set
# CONFIG_ARCH_X86 is not set
# CONFIG_ARCH_Z16 is not set
# CONFIG_ARCH_Z80 is not set
CONFIG_ARCH="arm"
#
# ARM Options
#
# CONFIG_ARCH_CHIP_A1X is not set
# CONFIG_ARCH_CHIP_C5471 is not set
# CONFIG_ARCH_CHIP_CALYPSO is not set
# CONFIG_ARCH_CHIP_DM320 is not set
# CONFIG_ARCH_CHIP_EFM32 is not set
# CONFIG_ARCH_CHIP_IMX1 is not set
# CONFIG_ARCH_CHIP_IMX6 is not set
# CONFIG_ARCH_CHIP_KINETIS is not set
# CONFIG_ARCH_CHIP_KL is not set
# CONFIG_ARCH_CHIP_LM is not set
# CONFIG_ARCH_CHIP_TIVA is not set
# CONFIG_ARCH_CHIP_LPC11XX is not set
# CONFIG_ARCH_CHIP_LPC17XX is not set
# CONFIG_ARCH_CHIP_LPC214X is not set
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
# CONFIG_ARCH_CHIP_SAML is not set
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
# CONFIG_ARCH_CHIP_STM32 is not set
CONFIG_ARCH_CHIP_STM32F7=y
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
# CONFIG_ARCH_CORTEXM0 is not set
# CONFIG_ARCH_CORTEXM3 is not set
# CONFIG_ARCH_CORTEXM4 is not set
CONFIG_ARCH_CORTEXM7=y
# CONFIG_ARCH_CORTEXA5 is not set
# CONFIG_ARCH_CORTEXA8 is not set
# CONFIG_ARCH_CORTEXA9 is not set
# CONFIG_ARCH_CORTEXR4 is not set
# CONFIG_ARCH_CORTEXR4F is not set
# CONFIG_ARCH_CORTEXR5 is not set
# CONFIG_ARCH_CORTEX5F is not set
# CONFIG_ARCH_CORTEXR7 is not set
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32f7"
# CONFIG_ARM_TOOLCHAIN_IAR is not set
CONFIG_ARM_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
# CONFIG_ARMV7M_LAZYFPU is not set
CONFIG_ARCH_HAVE_FPU=y
CONFIG_ARCH_HAVE_DPFPU=y
# CONFIG_ARCH_FPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
CONFIG_ARM_HAVE_MPU_UNIFIED=y
# CONFIG_ARM_MPU is not set
#
# ARMV7M Configuration Options
#
CONFIG_ARMV7M_HAVE_ICACHE=y
CONFIG_ARMV7M_HAVE_DCACHE=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
CONFIG_ARMV7M_HAVE_ITCM=y
CONFIG_ARMV7M_HAVE_DTCM=y
# CONFIG_ARMV7M_ITCM is not set
CONFIG_ARMV7M_DTCM=y
# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
CONFIG_ARMV7M_HAVE_STACKCHECK=y
# CONFIG_ARMV7M_STACKCHECK is not set
# CONFIG_ARMV7M_ITMSYSLOG is not set
# CONFIG_SERIAL_TERMIOS is not set
#
# STM32 F7 Configuration Options
#
# CONFIG_ARCH_CHIP_STM32F745 is not set
CONFIG_ARCH_CHIP_STM32F746=y
# CONFIG_ARCH_CHIP_STM32F756 is not set
CONFIG_STM32F7_STM32F74XX=y
# CONFIG_STM32F7_STM32F75XX is not set
# CONFIG_STM32F7_FLASH_512KB is not set
CONFIG_STM32F7_FLASH_1024KB=y
#
# STM32 Peripheral Support
#
CONFIG_STM32F7_HAVE_LTDC=y
# CONFIG_STM32F7_ADC is not set
# CONFIG_STM32F7_CAN is not set
# CONFIG_STM32F7_DAC is not set
# CONFIG_STM32F7_DMA is not set
CONFIG_STM32F7_I2C=y
# CONFIG_STM32F7_SAI is not set
CONFIG_STM32F7_SPI=y
CONFIG_STM32F7_USART=y
# CONFIG_STM32F7_ADC1 is not set
# CONFIG_STM32F7_ADC2 is not set
# CONFIG_STM32F7_ADC3 is not set
# CONFIG_STM32F7_BKPSRAM is not set
# CONFIG_STM32F7_CAN1 is not set
# CONFIG_STM32F7_CAN2 is not set
# CONFIG_STM32F7_CEC is not set
# CONFIG_STM32F7_CRC is not set
# CONFIG_STM32F7_CRYP is not set
# CONFIG_STM32F7_DMA1 is not set
# CONFIG_STM32F7_DMA2 is not set
# CONFIG_STM32F7_DAC1 is not set
# CONFIG_STM32F7_DAC2 is not set
# CONFIG_STM32F7_DCMI is not set
# CONFIG_STM32F7_ETHMAC is not set
# CONFIG_STM32F7_FSMC is not set
CONFIG_STM32F7_I2C1=y
# CONFIG_STM32F7_I2C2 is not set
# CONFIG_STM32F7_I2C3 is not set
# CONFIG_STM32F7_LPTIM1 is not set
# CONFIG_STM32F7_LTDC is not set
# CONFIG_STM32F7_DMA2D is not set
# CONFIG_STM32F7_OTGFS is not set
# CONFIG_STM32F7_OTGHS is not set
# CONFIG_STM32F7_QUADSPI is not set
# CONFIG_STM32F7_SAI1 is not set
# CONFIG_STM32F7_RNG is not set
# CONFIG_STM32F7_SAI2 is not set
# CONFIG_STM32F7_SDMMC1 is not set
# CONFIG_STM32F7_SPDIFRX is not set
CONFIG_STM32F7_SPI1=y
# CONFIG_STM32F7_SPI2 is not set
# CONFIG_STM32F7_SPI3 is not set
# CONFIG_STM32F7_SPI4 is not set
# CONFIG_STM32F7_SPI5 is not set
# CONFIG_STM32F7_SPI6 is not set
# CONFIG_STM32F7_TIM1 is not set
# CONFIG_STM32F7_TIM2 is not set
# CONFIG_STM32F7_TIM3 is not set
# CONFIG_STM32F7_TIM4 is not set
# CONFIG_STM32F7_TIM5 is not set
# CONFIG_STM32F7_TIM6 is not set
# CONFIG_STM32F7_TIM7 is not set
# CONFIG_STM32F7_TIM8 is not set
# CONFIG_STM32F7_TIM9 is not set
# CONFIG_STM32F7_TIM10 is not set
# CONFIG_STM32F7_TIM11 is not set
# CONFIG_STM32F7_TIM12 is not set
# CONFIG_STM32F7_TIM13 is not set
# CONFIG_STM32F7_TIM14 is not set
# CONFIG_STM32F7_TIM15 is not set
# CONFIG_STM32F7_USART1 is not set
# CONFIG_STM32F7_USART2 is not set
# CONFIG_STM32F7_USART3 is not set
# CONFIG_STM32F7_UART4 is not set
# CONFIG_STM32F7_UART5 is not set
CONFIG_STM32F7_USART6=y
# CONFIG_STM32F7_UART7 is not set
# CONFIG_STM32F7_UART8 is not set
# CONFIG_STM32F7_IWDG is not set
# CONFIG_STM32F7_WWDG is not set
# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
#
# Architecture Options
#
# CONFIG_ARCH_NOINTC is not set
# CONFIG_ARCH_VECNOTIRQ is not set
# CONFIG_ARCH_DMA is not set
CONFIG_ARCH_HAVE_IRQPRIO=y
# CONFIG_ARCH_L2CACHE is not set
# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
# CONFIG_ARCH_HAVE_ADDRENV is not set
# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
# CONFIG_ARCH_HAVE_MULTICPU is not set
CONFIG_ARCH_HAVE_VFORK=y
# CONFIG_ARCH_HAVE_MMU is not set
CONFIG_ARCH_HAVE_MPU=y
# CONFIG_ARCH_NAND_HWECC is not set
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_USE_MPU is not set
# CONFIG_ARCH_IRQPRIO is not set
CONFIG_ARCH_STACKDUMP=y
# CONFIG_ENDIAN_BIG is not set
# CONFIG_ARCH_IDLE_CUSTOM is not set
# CONFIG_ARCH_HAVE_RAMFUNCS is not set
CONFIG_ARCH_HAVE_RAMVECTORS=y
# CONFIG_ARCH_RAMVECTORS is not set
#
# Board Settings
#
CONFIG_BOARD_LOOPSPERMSEC=43103
# CONFIG_ARCH_CALIBRATION is not set
#
# Interrupt options
#
CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
CONFIG_ARCH_INTERRUPTSTACK=0
CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
# CONFIG_ARCH_HIPRI_INTERRUPT is not set
#
# Boot options
#
# CONFIG_BOOT_RUNFROMEXTSRAM is not set
CONFIG_BOOT_RUNFROMFLASH=y
# CONFIG_BOOT_RUNFROMISRAM is not set
# CONFIG_BOOT_RUNFROMSDRAM is not set
# CONFIG_BOOT_COPYTORAM is not set
#
# Boot Memory Configuration
#
CONFIG_RAM_START=0x20010000
CONFIG_RAM_SIZE=245760
# CONFIG_ARCH_HAVE_SDRAM is not set
#
# Board Selection
#
# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set
CONFIG_ARCH_BOARD_STM32F746_WS=y
# CONFIG_ARCH_BOARD_CUSTOM is not set
CONFIG_ARCH_BOARD="stm32f746-ws"
#
# Common Board Options
#
# CONFIG_ARCH_HAVE_LEDS is not set
# CONFIG_ARCH_LEDS is not set
# CONFIG_ARCH_HAVE_BUTTONS is not set
# CONFIG_ARCH_BUTTONS is not set
# CONFIG_ARCH_HAVE_IRQBUTTONS is not set
# CONFIG_ARCH_IRQBUTTONS is not set
CONFIG_NSH_MMCSDMINOR=0
#
# Board-Specific Options
#
# CONFIG_LIB_BOARDCTL is not set
#
# RTOS Features
#
CONFIG_DISABLE_OS_API=y
# CONFIG_DISABLE_POSIX_TIMERS is not set
# CONFIG_DISABLE_PTHREAD is not set
# CONFIG_DISABLE_SIGNALS is not set
# CONFIG_DISABLE_MQUEUE is not set
# CONFIG_DISABLE_ENVIRON is not set
#
# Clocks and Timers
#
CONFIG_USEC_PER_TICK=10000
# CONFIG_SYSTEM_TIME64 is not set
# CONFIG_CLOCK_MONOTONIC is not set
# CONFIG_JULIAN_TIME is not set
CONFIG_START_YEAR=2011
CONFIG_START_MONTH=12
CONFIG_START_DAY=6
CONFIG_MAX_WDOGPARMS=2
CONFIG_PREALLOC_WDOGS=4
CONFIG_WDOG_INTRESERVE=0
CONFIG_PREALLOC_TIMERS=4
#
# Tasks and Scheduling
#
# CONFIG_INIT_NONE is not set
CONFIG_INIT_ENTRYPOINT=y
# CONFIG_INIT_FILEPATH is not set
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_RR_INTERVAL=200
# CONFIG_SCHED_SPORADIC is not set
CONFIG_TASK_NAME_SIZE=0
CONFIG_MAX_TASKS=16
# CONFIG_SCHED_HAVE_PARENT is not set
CONFIG_SCHED_WAITPID=y
#
# Pthread Options
#
# CONFIG_MUTEX_TYPES is not set
CONFIG_NPTHREAD_KEYS=4
#
# Performance Monitoring
#
# CONFIG_SCHED_CPULOAD is not set
# CONFIG_SCHED_INSTRUMENTATION is not set
#
# Files and I/O
#
CONFIG_DEV_CONSOLE=y
# CONFIG_FDCLONE_DISABLE is not set
# CONFIG_FDCLONE_STDIO is not set
CONFIG_SDCLONE_DISABLE=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NAME_MAX=32
# CONFIG_PRIORITY_INHERITANCE is not set
#
# RTOS hooks
#
# CONFIG_BOARD_INITIALIZE is not set
# CONFIG_SCHED_STARTHOOK is not set
# CONFIG_SCHED_ATEXIT is not set
# CONFIG_SCHED_ONEXIT is not set
#
# Signal Numbers
#
CONFIG_SIG_SIGUSR1=1
CONFIG_SIG_SIGUSR2=2
CONFIG_SIG_SIGALARM=3
CONFIG_SIG_SIGCONDTIMEDOUT=16
#
# POSIX Message Queue Options
#
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_MQ_MAXMSGSIZE=32
# CONFIG_MODULE is not set
#
# Work queue support
#
# CONFIG_SCHED_WORKQUEUE is not set
# CONFIG_SCHED_HPWORK is not set
# CONFIG_SCHED_LPWORK is not set
#
# Stack and heap information
#
CONFIG_IDLETHREAD_STACKSIZE=1024
CONFIG_USERMAIN_STACKSIZE=2048
CONFIG_PTHREAD_STACK_MIN=256
CONFIG_PTHREAD_STACK_DEFAULT=2048
# CONFIG_LIB_SYSCALL is not set
#
# Device Drivers
#
CONFIG_DISABLE_POLL=y
CONFIG_DEV_NULL=y
# CONFIG_DEV_ZERO is not set
# CONFIG_DEV_LOOP is not set
#
# Buffering
#
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
# CONFIG_CAN is not set
# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
# CONFIG_PWM is not set
CONFIG_ARCH_HAVE_I2CRESET=y
CONFIG_I2C=y
CONFIG_SPI=y
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_EXCHANGE=y
# CONFIG_SPI_CMDDATA is not set
# CONFIG_SPI_CALLBACK is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_HWFEATURES is not set
# CONFIG_SPI_CRCGENERATION is not set
# CONFIG_I2S is not set
#
# Timer Driver Support
#
# CONFIG_TIMER is not set
# CONFIG_RTC is not set
# CONFIG_WATCHDOG is not set
# CONFIG_ANALOG is not set
# CONFIG_AUDIO_DEVICES is not set
# CONFIG_VIDEO_DEVICES is not set
# CONFIG_BCH is not set
# CONFIG_INPUT is not set
# CONFIG_IOEXPANDER is not set
# CONFIG_LCD is not set
#
# LED Support
#
# CONFIG_USERLED is not set
# CONFIG_RGBLED is not set
# CONFIG_PCA9635PW is not set
# CONFIG_MMCSD is not set
# CONFIG_MODEM is not set
# CONFIG_MTD is not set
# CONFIG_EEPROM is not set
# CONFIG_PIPES is not set
# CONFIG_PM is not set
# CONFIG_POWER is not set
# CONFIG_SENSORS is not set
# CONFIG_SERCOMM_CONSOLE is not set
CONFIG_SERIAL=y
# CONFIG_DEV_LOWCONSOLE is not set
# CONFIG_16550_UART is not set
# CONFIG_ARCH_HAVE_UART is not set
# CONFIG_ARCH_HAVE_UART0 is not set
# CONFIG_ARCH_HAVE_UART1 is not set
# CONFIG_ARCH_HAVE_UART2 is not set
# CONFIG_ARCH_HAVE_UART3 is not set
# CONFIG_ARCH_HAVE_UART4 is not set
# CONFIG_ARCH_HAVE_UART5 is not set
# CONFIG_ARCH_HAVE_UART6 is not set
# CONFIG_ARCH_HAVE_UART7 is not set
# CONFIG_ARCH_HAVE_UART8 is not set
# CONFIG_ARCH_HAVE_SCI0 is not set
# CONFIG_ARCH_HAVE_SCI1 is not set
# CONFIG_ARCH_HAVE_USART0 is not set
# CONFIG_ARCH_HAVE_USART1 is not set
# CONFIG_ARCH_HAVE_USART2 is not set
# CONFIG_ARCH_HAVE_USART3 is not set
# CONFIG_ARCH_HAVE_USART4 is not set
# CONFIG_ARCH_HAVE_USART5 is not set
CONFIG_ARCH_HAVE_USART6=y
# CONFIG_ARCH_HAVE_USART7 is not set
# CONFIG_ARCH_HAVE_USART8 is not set
# CONFIG_ARCH_HAVE_OTHER_UART is not set
#
# USART Configuration
#
CONFIG_USART6_ISUART=y
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
# CONFIG_SERIAL_DMA is not set
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
CONFIG_USART6_SERIAL_CONSOLE=y
# CONFIG_OTHER_SERIAL_CONSOLE is not set
# CONFIG_NO_SERIAL_CONSOLE is not set
#
# USART6 Configuration
#
CONFIG_USART6_RXBUFSIZE=256
CONFIG_USART6_TXBUFSIZE=256
CONFIG_USART6_BAUD=115200
CONFIG_USART6_BITS=8
CONFIG_USART6_PARITY=0
CONFIG_USART6_2STOP=0
# CONFIG_USART6_IFLOWCONTROL is not set
# CONFIG_USART6_OFLOWCONTROL is not set
# CONFIG_USART6_DMA is not set
# CONFIG_USBDEV is not set
# CONFIG_USBHOST is not set
# CONFIG_DRIVERS_WIRELESS is not set
#
# System Logging Device Options
#
#
# System Logging
#
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_CONSOLE is not set
#
# Networking Support
#
# CONFIG_ARCH_HAVE_NET is not set
# CONFIG_ARCH_HAVE_PHY is not set
# CONFIG_NET is not set
#
# Crypto API
#
# CONFIG_CRYPTO is not set
#
# File Systems
#
#
# File system configuration
#
# CONFIG_DISABLE_MOUNTPOINT is not set
# CONFIG_FS_AUTOMOUNTER is not set
# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
# CONFIG_FS_READABLE is not set
# CONFIG_FS_WRITABLE is not set
# CONFIG_FS_NAMED_SEMAPHORES is not set
CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
# CONFIG_FS_RAMMAP is not set
# CONFIG_FS_FAT is not set
# CONFIG_FS_NXFFS is not set
# CONFIG_FS_ROMFS is not set
# CONFIG_FS_TMPFS is not set
# CONFIG_FS_SMARTFS is not set
# CONFIG_FS_BINFS is not set
# CONFIG_FS_PROCFS is not set
# CONFIG_FS_UNIONFS is not set
#
# System Logging
#
# CONFIG_SYSLOG is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
#
# Graphics Support
#
# CONFIG_NX is not set
#
# Memory Management
#
# CONFIG_MM_SMALL is not set
CONFIG_MM_REGIONS=2
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Audio Support
#
# CONFIG_AUDIO is not set
#
# Wireless Support
#
#
# Binary Loader
#
# CONFIG_BINFMT_DISABLE is not set
# CONFIG_BINFMT_EXEPATH is not set
# CONFIG_NXFLAT is not set
# CONFIG_ELF is not set
CONFIG_BUILTIN=y
# CONFIG_PIC is not set
# CONFIG_SYMTAB_ORDEREDBYNAME is not set
#
# Library Routines
#
#
# Standard C Library Options
#
CONFIG_STDIO_BUFFER_SIZE=64
CONFIG_STDIO_LINEBUFFER=y
CONFIG_NUNGET_CHARS=2
CONFIG_LIB_HOMEDIR="/"
# CONFIG_LIBM is not set
# CONFIG_NOPRINTF_FIELDWIDTH is not set
# CONFIG_LIBC_FLOATINGPOINT is not set
CONFIG_LIBC_LONG_LONG=y
# CONFIG_LIBC_IOCTL_VARIADIC is not set
CONFIG_LIB_RAND_ORDER=1
# CONFIG_EOL_IS_CR is not set
# CONFIG_EOL_IS_LF is not set
# CONFIG_EOL_IS_BOTH_CRLF is not set
CONFIG_EOL_IS_EITHER_CRLF=y
# CONFIG_LIBC_EXECFUNCS is not set
CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
# CONFIG_LIBC_STRERROR is not set
# CONFIG_LIBC_PERROR_STDOUT is not set
CONFIG_ARCH_LOWPUTC=y
# CONFIG_LIBC_LOCALTIME is not set
# CONFIG_TIME_EXTENDED is not set
CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_ARCH_ROMGETC is not set
# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
CONFIG_ARCH_HAVE_TLS=y
# CONFIG_TLS is not set
# CONFIG_LIBC_NETDB is not set
#
# Non-standard Library Support
#
# CONFIG_LIB_KBDCODEC is not set
# CONFIG_LIB_SLCDCODEC is not set
#
# Basic CXX Support
#
# CONFIG_C99_BOOL8 is not set
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_CXX_NEWLONG is not set
#
# uClibc++ Standard C++ Library
#
# CONFIG_UCLIBCXX is not set
#
# Application Configuration
#
#
# Built-In Applications
#
CONFIG_BUILTIN_PROXY_STACKSIZE=1024
#
# CAN Utilities
#
#
# Examples
#
# CONFIG_EXAMPLES_BUTTONS is not set
# CONFIG_EXAMPLES_CHAT is not set
# CONFIG_EXAMPLES_CONFIGDATA is not set
# CONFIG_EXAMPLES_CPUHOG is not set
# CONFIG_EXAMPLES_CXXTEST is not set
# CONFIG_EXAMPLES_DHCPD is not set
# CONFIG_EXAMPLES_ELF is not set
# CONFIG_EXAMPLES_FTPC is not set
# CONFIG_EXAMPLES_FTPD is not set
# CONFIG_EXAMPLES_HELLO is not set
# CONFIG_EXAMPLES_HELLOXX is not set
# CONFIG_EXAMPLES_JSON is not set
# CONFIG_EXAMPLES_HIDKBD is not set
# CONFIG_EXAMPLES_KEYPADTEST is not set
# CONFIG_EXAMPLES_IGMP is not set
# CONFIG_EXAMPLES_MEDIA is not set
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTEXT is not set
# CONFIG_EXAMPLES_OSTEST is not set
# CONFIG_EXAMPLES_PCA9635 is not set
# CONFIG_EXAMPLES_PIPE is not set
# CONFIG_EXAMPLES_PPPD is not set
# CONFIG_EXAMPLES_POSIXSPAWN is not set
# CONFIG_EXAMPLES_RGBLED is not set
# CONFIG_EXAMPLES_RGMP is not set
# CONFIG_EXAMPLES_SENDMAIL is not set
# CONFIG_EXAMPLES_SERIALBLASTER is not set
# CONFIG_EXAMPLES_SERIALRX is not set
# CONFIG_EXAMPLES_SERLOOP is not set
# CONFIG_EXAMPLES_SLCD is not set
# CONFIG_EXAMPLES_SMART_TEST is not set
# CONFIG_EXAMPLES_SMART is not set
# CONFIG_EXAMPLES_SMP is not set
# CONFIG_EXAMPLES_TCPECHO is not set
# CONFIG_EXAMPLES_TELNETD is not set
# CONFIG_EXAMPLES_TIFF is not set
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_USBTERM is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
#
# File System Utilities
#
# CONFIG_FSUTILS_INIFILE is not set
#
# GPS Utilities
#
# CONFIG_GPSUTILS_MINMEA_LIB is not set
#
# Graphics Support
#
# CONFIG_TIFF is not set
# CONFIG_GRAPHICS_TRAVELER is not set
#
# Interpreters
#
# CONFIG_INTERPRETERS_FICL is not set
# CONFIG_INTERPRETERS_PCODE is not set
# CONFIG_INTERPRETERS_MICROPYTHON is not set
#
# FreeModBus
#
# CONFIG_MODBUS is not set
#
# Network Utilities
#
# CONFIG_NETUTILS_CODECS is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_JSON is not set
# CONFIG_NETUTILS_SMTP is not set
#
# NSH Library
#
CONFIG_NSH_LIBRARY=y
# CONFIG_NSH_MOTD is not set
#
# Command Line Configuration
#
CONFIG_NSH_READLINE=y
# CONFIG_NSH_CLE is not set
CONFIG_NSH_LINELEN=64
# CONFIG_NSH_DISABLE_SEMICOLON is not set
CONFIG_NSH_CMDPARMS=y
CONFIG_NSH_MAXARGUMENTS=6
CONFIG_NSH_ARGCAT=y
CONFIG_NSH_NESTDEPTH=3
# CONFIG_NSH_DISABLEBG is not set
CONFIG_NSH_BUILTIN_APPS=y
#
# Disable Individual commands
#
# CONFIG_NSH_DISABLE_ADDROUTE is not set
# CONFIG_NSH_DISABLE_BASENAME is not set
# CONFIG_NSH_DISABLE_CAT is not set
# CONFIG_NSH_DISABLE_CD is not set
# CONFIG_NSH_DISABLE_CP is not set
# CONFIG_NSH_DISABLE_CMP is not set
CONFIG_NSH_DISABLE_DATE=y
# CONFIG_NSH_DISABLE_DD is not set
# CONFIG_NSH_DISABLE_DF is not set
# CONFIG_NSH_DISABLE_DELROUTE is not set
# CONFIG_NSH_DISABLE_DIRNAME is not set
# CONFIG_NSH_DISABLE_ECHO is not set
# CONFIG_NSH_DISABLE_EXEC is not set
# CONFIG_NSH_DISABLE_EXIT is not set
# CONFIG_NSH_DISABLE_FREE is not set
# CONFIG_NSH_DISABLE_GET is not set
# CONFIG_NSH_DISABLE_HELP is not set
# CONFIG_NSH_DISABLE_HEXDUMP is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
CONFIG_NSH_DISABLE_IFUPDOWN=y
# CONFIG_NSH_DISABLE_KILL is not set
# CONFIG_NSH_DISABLE_LOSETUP is not set
CONFIG_NSH_DISABLE_LOSMART=y
# CONFIG_NSH_DISABLE_LS is not set
# CONFIG_NSH_DISABLE_MB is not set
# CONFIG_NSH_DISABLE_MKDIR is not set
# CONFIG_NSH_DISABLE_MKFIFO is not set
# CONFIG_NSH_DISABLE_MKRD is not set
# CONFIG_NSH_DISABLE_MH is not set
# CONFIG_NSH_DISABLE_MOUNT is not set
# CONFIG_NSH_DISABLE_MV is not set
# CONFIG_NSH_DISABLE_MW is not set
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NSH_DISABLE_PUT is not set
# CONFIG_NSH_DISABLE_PWD is not set
# CONFIG_NSH_DISABLE_RM is not set
# CONFIG_NSH_DISABLE_RMDIR is not set
# CONFIG_NSH_DISABLE_SET is not set
# CONFIG_NSH_DISABLE_SH is not set
# CONFIG_NSH_DISABLE_SLEEP is not set
# CONFIG_NSH_DISABLE_TIME is not set
# CONFIG_NSH_DISABLE_TEST is not set
# CONFIG_NSH_DISABLE_UMOUNT is not set
# CONFIG_NSH_DISABLE_UNAME is not set
# CONFIG_NSH_DISABLE_UNSET is not set
# CONFIG_NSH_DISABLE_USLEEP is not set
# CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set
#
# Configure Command Options
#
CONFIG_NSH_CMDOPT_DF_H=y
CONFIG_NSH_CODECS_BUFSIZE=128
CONFIG_NSH_CMDOPT_HEXDUMP=y
CONFIG_NSH_FILEIOSIZE=512
#
# Scripting Support
#
# CONFIG_NSH_DISABLESCRIPT is not set
# CONFIG_NSH_DISABLE_ITEF is not set
# CONFIG_NSH_DISABLE_LOOPS is not set
#
# Console Configuration
#
CONFIG_NSH_CONSOLE=y
# CONFIG_NSH_ALTCONDEV is not set
CONFIG_NSH_ARCHINIT=y
# CONFIG_NSH_LOGIN is not set
# CONFIG_NSH_CONSOLE_LOGIN is not set
#
# NxWidgets/NxWM
#
#
# Platform-specific Support
#
# CONFIG_PLATFORM_CONFIGDATA is not set
#
# System Libraries and NSH Add-Ons
#
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_RAMTEST is not set
CONFIG_READLINE_HAVE_EXTMATCH=y
CONFIG_SYSTEM_READLINE=y
CONFIG_READLINE_ECHO=y
# CONFIG_READLINE_TABCOMPLETION is not set
# CONFIG_READLINE_CMD_HISTORY is not set
# CONFIG_SYSTEM_SUDOKU is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_ZMODEM is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
CONFIG_I2CTOOL_MAXBUS=1
CONFIG_I2CTOOL_MINADDR=0x03
CONFIG_I2CTOOL_MAXADDR=0x77
CONFIG_I2CTOOL_MAXREGADDR=0xff
CONFIG_I2CTOOL_DEFFREQ=100000

77
configs/stm32f746-ws/nsh/setenv.sh Normal file
View File

@ -0,0 +1,77 @@
#!/bin/bash
# configs/stm32f746-ws/nsh/setenv.sh
#
# Copyright (C) 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
if [ "$_" = "$0" ] ; then
echo "You must source this script, not run it!" 1>&2
exit 1
fi
WD=`pwd`
if [ ! -x "setenv.sh" ]; then
echo "This script must be executed from the top-level NuttX build directory"
exit 1
fi
if [ -z "${PATH_ORIG}" ]; then
export PATH_ORIG="${PATH}"
fi
# This is the Cygwin path to the location where I installed the Atmel GCC
# toolchain under Windows. You will also have to edit this if you install
# this toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
# This is the Cygwin path to the location where I installed the CodeSourcery
# toolchain under windows. You will also have to edit this if you install
# the CodeSourcery toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
export TOOLCHAIN_BIN="/cygdrive/c/Users/Public/tools/bin"
# This is the path to the location where I installed the devkitARM toolchain
# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
# This is the Cygwin path to the location where I build the buildroot
# toolchain.
# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
# Add the path to the toolchain to the PATH varialble
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
echo "PATH : ${PATH}"

147
configs/stm32f746-ws/scripts/flash.ld Normal file
View File

@ -0,0 +1,147 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/flash.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Modified 11/4/2013 for STM32F429 support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
* be accessed from either the AXIM interface at address 0x0800:0000 or from
* the ITCM interface at address 0x0020:0000.
*
* Additional information, including the option bytes, is available at at
* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
*
* In the STM32F746NGH6, two different boot spaces can be selected through
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
* BOOT_ADD1 option bytes:
*
* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
* ST programmed value: Flash on ITCM at 0x0020:0000
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified STM32F746G
* DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
* to address 0x0020:0000 in ITCM FLASH.
*
* The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
* SRAM is split up into three blocks:
*
* 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
* 2) 240Kb of SRAM1 beginning at address 0x2001:0000
* 3) 16Kb of SRAM2 beginning at address 0x2004:c000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*/
MEMORY
{
itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K
sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : {
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram1 AT > flash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram1
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

109
configs/stm32f746-ws/scripts/kernel-space.ld Normal file
View File

@ -0,0 +1,109 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/kernel-space.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > kflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

129
configs/stm32f746-ws/scripts/memory.ld Normal file
View File

@ -0,0 +1,129 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/memory.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can
* be accessed from either the AXIM interface at address 0x0800:0000 or from
* the ITCM interface at address 0x0020:0000.
*
* Additional information, including the option bytes, is available at at
* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
*
* In the STM32F746NGH6, two different boot spaces can be selected through
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
* BOOT_ADD1 option bytes:
*
* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
* ST programmed value: Flash on ITCM at 0x0020:0000
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified STM32F746G
* DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
* to address 0x0020:0000 in ITCM FLASH.
*
* The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
* SRAM is split up into three blocks:
*
* 1) 64Kb of DTCM SRM beginning at address 0x2000:0000
* 2) 240Kb of SRAM1 beginning at address 0x2001:0000
* 3) 16Kb of SRAM2 beginning at address 0x2004:c000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*
* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
* FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
* should fit into 64KB and, of course, can be optimized as needed (See
* also configs/stm32f746g-disco/scripts/kernel-space.ld). Allowing the
* additional does permit addition debug instrumentation to be added to the
* kernel space without overflowing the partition.
*
* Alignment of the user space FLASH partition is also a critical factor:
* The user space FLASH partition will be spanned with a single region of
* size 2**n bytes. The alignment of the user-space region must be the same.
* As a consequence, as the user-space increases in size, the alignment
* requirement also increases.
*
* This alignment requirement means that the largest user space FLASH region
* you can have will be 512KB at it would have to be positioned at
* 0x08800000. If you change this address, don't forget to change the
* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
* the check in kernel/userspace.c.
*
* For the same reasons, the maximum size of the SRAM mapping is limited to
* 4KB. Both of these alignment limitations could be reduced by using
* multiple regions to map the FLASH/SDRAM range or perhaps with some
* clever use of subregions.
*
* A detailed memory map for the 112KB SRAM region is as follows:
*
* 0x20001 0000: Kernel .data region. Typical size: 0.1KB
* ------- ---- Kernel .bss region. Typical size: 1.8KB
* 0x20001 0800: Kernel IDLE thread stack (approximate). Size is
* determined by CONFIG_IDLETHREAD_STACKSIZE and
* adjustments for alignment. Typical is 1KB.
* ------- ---- Padded to 4KB
* 0x20001 1000: User .data region. Size is variable.
* ------- ---- User .bss region Size is variable.
* 0x20001 2000: Beginning of kernel heap. Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE.
* ------- ---- Beginning of user heap. Can vary with other settings.
* 0x20004 c000: End+1 of SRAM1
*/
MEMORY
{
/* ITCM boot address */
itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
/* 1024KB FLASH */
kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K
/* 240KB of contiguous SRAM1 */
ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K
usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K
xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K
/* DTCM SRAM */
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
}

111
configs/stm32f746-ws/scripts/user-space.ld Normal file
View File

@ -0,0 +1,111 @@
/****************************************************************************
* configs/stm32f746-ws/scripts/user-space.ld
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
SECTIONS
{
.userspace : {
*(.userspace)
} > uflash
.text : {
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > uflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > uflash
.ARM.extab : {
*(.ARM.extab*)
} > uflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > uflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > usram AT > uflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > usram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

2
configs/stm32f746-ws/src/.gitignore vendored Normal file
View File

@ -0,0 +1,2 @@
/.depend
/Make.dep

45
configs/stm32f746-ws/src/Makefile Normal file
View File

@ -0,0 +1,45 @@
############################################################################
# configs/stm32f746-ws/src/Makefile
#
# Copyright (C) 2015 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = stm32_boot.c stm32_spi.c
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += stm32_appinitialize.c
endif
include $(TOPDIR)/configs/Board.mk

65
configs/stm32f746-ws/src/stm32_appinitialize.c Normal file
View File

@ -0,0 +1,65 @@
/****************************************************************************
* config/stm32f746-ws/src/stm32_appinitilaize.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Author: Mark Olsson <post@markolsson.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <syslog.h>
#include "stm32f746-ws.h"
#include <nuttx/leds/userled.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
****************************************************************************/
int board_app_initialize(void)
{
return OK;
}

106
configs/stm32f746-ws/src/stm32_boot.c Normal file
View File

@ -0,0 +1,106 @@
/************************************************************************************
* configs/stm32f746-ws/src/stm32_boot.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "stm32f746-ws.h"
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_boardinitialize
*
* Description:
* All STM32 architectures must provide the following entry point. This entry point
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
*
************************************************************************************/
void stm32_boardinitialize(void)
{
#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
* stm32_spidev_initialize() has been brought into the link.
*/
if (stm32_spidev_initialize)
{
stm32_spidev_initialize();
}
#endif
}
/************************************************************************************
* Name: board_initialize
*
* Description:
* If CONFIG_BOARD_INITIALIZE is selected, then an additional initialization call
* will be performed in the boot-up sequence to a function called
* board_initialize(). board_initialize() will be called immediately after
* up_initialize() is called and just before the initial application is started.
* This additional initialization phase may be used, for example, to initialize
* board-specific device drivers.
*
************************************************************************************/
#ifdef CONFIG_BOARD_INITIALIZE
void board_initialize(void)
{
#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
/* Perform NSH initialization here instead of from the NSH. This
* alternative NSH initialization is necessary when NSH is ran in user-space
* but the initialization function must run in kernel space.
*/
(void)board_app_initialize();
#endif
}
#endif

257
configs/stm32f746-ws/src/stm32_spi.c Normal file
View File

@ -0,0 +1,257 @@
/************************************************************************************
* configs/nucleo-144/src/stm32_spi.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/spi/spi.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_spi.h"
#include "stm32f746-ws.h"
#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef SPI_VERBOSE
# define spivdbg lldbg
# else
# define spivdbg(x...)
# endif
#else
# undef SPI_VERBOSE
# define spidbg(x...)
# define spivdbg(x...)
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the stm32f746g-disco board.
*
************************************************************************************/
void weak_function stm32_spidev_initialize(void)
{
}
/****************************************************************************
* Name: stm32_spi1-6 select and stm32_spi1-6 status
*
* Description:
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
* provided by board-specific logic. They are implementations of the select
* and status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize())
* are provided by common STM32 logic. To use this common SPI logic on your
* board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
* board-specific logic. These functions will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 3. Add a calls to stm32_spibus_initialize() in your low level application
* initialization logic
* 4. The handle returned by stm32_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_STM32F7_SPI1
void stm32f7_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32f7_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI2
void stm32f7_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32f7_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI3
void stm32f7_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32f7_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI4
void stm32f7_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32f7_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI5
void stm32f7_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32f7_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32F7_SPI6
void stm32f7_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32f7_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#endif
/****************************************************************************
* Name: stm32_spi1cmddata
*
* Description:
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
* or command (false). This function must be provided by platform-specific
* logic. This is an implementation of the cmddata method of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
*
* Input Parameters:
*
* spi - SPI device that controls the bus the device that requires the CMD/
* DATA selection.
* devid - If there are multiple devices on the bus, this selects which one
* to select cmd or data. NOTE: This design restricts, for example,
* one one SPI display per SPI bus.
* cmd - true: select command; false: select data
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32F7_SPI1
int stm32f7_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI2
int stm32f7_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI3
int stm32f7_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI4
int stm32f7_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI5
int stm32f7_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32F7_SPI6
int stm32f7_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */

106
configs/stm32f746-ws/src/stm32f746-ws.h Normal file
View File

@ -0,0 +1,106 @@
/****************************************************************************************************
* configs/stm32f746-ws/src/stm32f746-ws.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Author: Mark Olsson <post@markolsson.se>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H
#define __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* procfs File System */
#ifdef CONFIG_FS_PROCFS
# ifdef CONFIG_NSH_PROC_MOUNTPOINT
# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
# else
# define STM32_PROCFS_MOUNTPOINT "/proc"
# endif
#endif
/* STM32F736G Discovery GPIOs ***********************************************************************/
/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the reset button, that
* can be controlled by software (LD2 is a power indicator, LD3-6 indicate USB status, LD7 is
* controlled by the ST-Link).
*
* LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface. One end of LD1 is
* grounded so a high output on PI1 will illuminate the LED.
*/
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN14)
#define LED_DRIVER_PATH "/dev/userleds"
/* Pushbutton B1, labelled "User", is connected to GPIO PC13. A high value will be sensed when the
* button is depressed. Note that the EXTI interrupt is configured.
*/
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
/****************************************************************************************************
* Public data
****************************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the stm32f746g-disco board.
*
****************************************************************************************************/
void weak_function stm32_spidev_initialize(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H */