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Fix a critical PIC32 GPIO configuration bug

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4867 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-06-25 15:24:52 +00:00
parent 8d06757bc4
commit 4ca2862016
2 changed files with 4 additions and 5 deletions
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8
arch/mips/src/pic32mx/pic32mx-gpio.c
View File

@ -160,7 +160,7 @@ int pic32mx_configgpio(uint16_t cfgset)
sched_lock();
if (pic32mx_output(cfgset))
{
/* It is an output; set the corresponding bit in the TRIS register */
/* It is an output; clear the corresponding bit in the TRIS register */
putreg32(1 << pin, base + PIC32MX_IOPORT_TRISCLR_OFFSET);
@ -189,11 +189,9 @@ int pic32mx_configgpio(uint16_t cfgset)
}
else
{
/* It is an input; clear the corresponding bit in the TRIS
* register.
*/
/* It is an input; set the corresponding bit in the TRIS register. */
putreg32(1 << pin, base + PIC32MX_IOPORT_TRISCLR_OFFSET);
putreg32(1 << pin, base + PIC32MX_IOPORT_TRISSET_OFFSET);
putreg32(1 << pin, base + PIC32MX_IOPORT_ODCCLR_OFFSET);
}

1
arch/mips/src/pic32mx/pic32mx-ioport.h
View File

@ -73,6 +73,7 @@
# define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0044 /* Open drain control clear register */
# define PIC32MX_IOPORT_ODCSET_OFFSET 0x0048 /* Open drain control set register */
# define PIC32MX_IOPORT_ODCINV_OFFSET 0x004c /* Open drain control invert register */
# define PIC32MX_IOPORT_CNPU_OFFSET 0x0050 /* Change Notification Pull-up register */
# define PIC32MX_IOPORT_CNPUCLR_OFFSET 0x0054 /* Change Notification Pull-up clear register */
# define PIC32MX_IOPORT_CNPUSET_OFFSET 0x0058 /* Change Notification Pull-up set register */