mmc renames
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1cbd7a0e59
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@ -274,16 +274,16 @@
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define SDMMC1_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
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#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDMMC1_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDMMC1_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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@ -291,9 +291,9 @@
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDMMC1_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDMMC1_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/************************************************************************************
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@ -312,7 +312,7 @@ CONFIG_STM32F7_OTGFS=y
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# CONFIG_STM32F7_RNG is not set
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# CONFIG_STM32F7_SAI1 is not set
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# CONFIG_STM32F7_SAI2 is not set
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##CONFIG_STM32F7_SDMMC1=y
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CONFIG_STM32F7_SDMMC1=y
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# CONFIG_STM32F7_SPDIFRX is not set
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CONFIG_STM32F7_SPI1=y
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# CONFIG_STM32F7_SPI2 is not set
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