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SAMV7 EMAC: Fix range of MCK dividers

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This commit is contained in:
Gregory Nutt 2015-03-17 11:19:46 -06:00
parent ae433eaa84
commit 4ce927168f
1 changed files with 10 additions and 2 deletions
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12
arch/arm/src/samv7/sam_emac.c
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@ -3850,15 +3850,23 @@ static int sam_phyinit(struct sam_emac_s *priv)
regval &= ~EMAC_NCFGR_CLK_MASK;
mck = BOARD_MCK_FREQUENCY;
if (mck > (160*1000*1000))
if (mck > (240*1000*1000))
{
ndbg("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (80*1000*1000))
else if (mck > (160*1000*1000))
{
regval |= EMAC_NCFGR_CLK_DIV96; /* MCK divided by 64 (MCK up to 240 MHz) */
}
else if (mck > (120*1000*1000))
{
regval |= EMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
}
else if (mck > (80*1000*1000))
{
regval |= EMAC_NCFGR_CLK_DIV48; /* MCK divided by 64 (MCK up to 120 MHz) */
}
else if (mck > (40*1000*1000))
{
regval |= EMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */