SAMA5 ADC/Touchscreen: A little more progress. Still not complete
This commit is contained in:
Gregory Nutt
parent
647aff0ded
commit
4cecf0b618
@ -289,6 +289,8 @@
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#define ADC_INT_EOC7 (1 << 9) /* Bit 9: End of Conversion 9 */
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#define ADC_INT_EOC7 (1 << 10) /* Bit 10: End of Conversion 10 */
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#define ADC_INT_EOC7 (1 << 11) /* Bit 11: End of Conversion 11 */
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#define ADC_INT_EOCALL (0x00000fff)
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#define ADC_INT_XRDY (1 << 20) /* Bit 20: TS Measure XPOS Ready Interrupt */
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#define ADC_INT_YRDY (1 << 21) /* Bit 21: TS Measure YPOS Ready Interrupt */
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#define ADC_INT_PRDY (1 << 22) /* Bit 22: TS Measure Pressure Ready Interrupt */
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@ -1,7 +1,6 @@
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/************************************************************************************
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* arch/arm/src/sama5/sam_adc.c
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*
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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@ -65,6 +64,64 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get the set of channel interrupts to enable */
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#define SAMA5_CHAN0_ENABLE 0
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#define SAMA5_CHAN1_ENABLE 0
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#define SAMA5_CHAN2_ENABLE 0
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#define SAMA5_CHAN3_ENABLE 0
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#define SAMA5_CHAN4_ENABLE 0
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#define SAMA5_CHAN5_ENABLE 0
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#define SAMA5_CHAN6_ENABLE 0
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#define SAMA5_CHAN7_ENABLE 0
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#define SAMA5_CHAN8_ENABLE 0
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#define SAMA5_CHAN9_ENABLE 0
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#define SAMA5_CHAN10_ENABLE 0
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#define SAMA5_CHAN11_ENABLE 0
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#if defined(CONFIG_SAMA5_ADC_CHAN0)
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# undef SAMA5_CHAN0_ENABLE
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# define SAMA5_CHAN0_ENABLE ADC_INT_EOC0
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#elif defined(CONFIG_SAMA5_ADC_CHAN1)
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# undef SAMA5_CHAN1_ENABLE
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# define SAMA5_CHAN1_ENABLE ADC_INT_EOC1
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#elif defined(CONFIG_SAMA5_ADC_CHAN2)
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# undef SAMA5_CHAN2_ENABLE
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# define SAMA5_CHAN2_ENABLE ADC_INT_EOC2
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#elif defined(CONFIG_SAMA5_ADC_CHAN3)
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# undef SAMA5_CHAN3_ENABLE
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# define SAMA5_CHAN3_ENABLE ADC_INT_EOC3
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#elif defined(CONFIG_SAMA5_ADC_CHAN4)
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# undef SAMA5_CHAN4_ENABLE
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# define SAMA5_CHAN4_ENABLE ADC_INT_EOC4
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#elif defined(CONFIG_SAMA5_ADC_CHAN5)
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# undef SAMA5_CHAN5_ENABLE
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# define SAMA5_CHAN5_ENABLE ADC_INT_EOC5
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#elif defined(CONFIG_SAMA5_ADC_CHAN6)
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# undef SAMA5_CHAN6_ENABLE
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# define SAMA5_CHAN6_ENABLE ADC_INT_EOC6
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#elif defined(CONFIG_SAMA5_ADC_CHAN7)
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# undef SAMA5_CHAN7_ENABLE
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# define SAMA5_CHAN7_ENABLE ADC_INT_EOC7
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#elif defined(CONFIG_SAMA5_ADC_CHAN8)
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# undef SAMA5_CHAN8_ENABLE
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# define SAMA5_CHAN8_ENABLE ADC_INT_EOC8
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#elif defined(CONFIG_SAMA5_ADC_CHAN9)
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# undef SAMA5_CHAN9_ENABLE
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# define SAMA5_CHAN9_ENABLE ADC_INT_EOC9
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#elif defined(CONFIG_SAMA5_ADC_CHAN10)
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# undef SAMA5_CHAN10_ENABLE
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# define SAMA5_CHAN10_ENABLE ADC_INT_EOC10
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#elif defined(CONFIG_SAMA5_ADC_CHAN11)
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# undef SAMA5_CHAN11_ENABLE
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# define SAMA5_CHAN11_ENABLE ADC_INT_EOC11
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#endif
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#define SAMA5_CHAN_ENABLE \
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(SAMA5_CHAN0_ENABLE || SAMA5_CHAN1_ENABLE || SAMA5_CHAN2_ENABLE || \
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SAMA5_CHAN3_ENABLE || SAMA5_CHAN4_ENABLE || SAMA5_CHAN5_ENABLE || \
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SAMA5_CHAN6_ENABLE || SAMA5_CHAN7_ENABLE || SAMA5_CHAN8_ENABLE || \
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SAMA5_CHAN9_ENABLE || SAMA5_CHAN10_ENABLE || SAMA5_CHAN11_ENABLE)
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/****************************************************************************
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* Private Types
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@ -74,13 +131,17 @@
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struct sam_adc_s
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{
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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struct adc_dev_s dev; /* The external via of the ADC device */
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#endif
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/* Debug stuff */
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#ifdef CONFIG_SAMA5_ADC_REGDEBUG
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bool wrlast; /* Last was a write */
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uintptr_t addrlast; /* Last address */
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uint32_t vallast; /* Last value */
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int ntimes; /* Number of times */
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bool wrlast; /* Last was a write */
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uintptr_t addrlast; /* Last address */
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uint32_t vallast; /* Last value */
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int ntimes; /* Number of times */
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#endif
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};
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@ -90,31 +151,32 @@ struct sam_adc_s
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/* Register operations ******************************************************/
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#if defined(CONFIG_SAMA5_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
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static bool sam_adc_checkreg(struct sam_gmac_s *priv, bool wr,
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uint32_t regval, uintptr_t address);
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static uint32_t sam_adc_getreg(struct sam_gmac_s *priv, uintptr_t addr);
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static void sam_adc_putreg(struct sam_gmac_s *priv, uintptr_t addr, uint32_t val);
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#else
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# define sam_adc_getreg(priv,addr) getreg32(addr)
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# define sam_adc_putreg(priv,addr,val) putreg32(val,addr)
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static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
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uint32_t regval, uintptr_t address);
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#endif
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/* ADC interrupt handling */
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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static void sam_adc_endconversion(struct sam_adc_s *priv, uint32_t pending);
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#endif
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static int sam_adc_interrupt(int irq, void *context);
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/* ADC methods */
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static void sam_adc_reset(FAR struct adc_dev_s *dev);
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static int sam_adc_setup(FAR struct adc_dev_s *dev);
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static void sam_adc_shutdown(FAR struct adc_dev_s *dev);
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static void sam_adc_rxint(FAR struct adc_dev_s *dev, bool enable);
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static int sam_adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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static void sam_adc_reset(struct adc_dev_s *dev);
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static int sam_adc_setup(struct adc_dev_s *dev);
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static void sam_adc_shutdown(struct adc_dev_s *dev);
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static void sam_adc_rxint(struct adc_dev_s *dev, bool enable);
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static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg);
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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/* ADC lower half device operations */
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static const struct adc_ops_s g_adcops =
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@ -125,20 +187,21 @@ static const struct adc_ops_s g_adcops =
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.ao_rxint = sam_adc_rxint,
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.ao_ioctl = sam_adc_ioctl,
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};
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#endif
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/* ADC internal state */
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static struct sam_adc_s g_adcpriv =
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{
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};
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static struct sam_adc_s g_adcpriv;
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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/* ADC device instance */
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static struct adc_dev_s g_adcdev =
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{
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.ad_ops = &g_adcops,
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.ad_priv = &g_adcpriv,
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.ad_priv = &g_adcpriv.dev,
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};
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#endif
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/****************************************************************************
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* Private Functions
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@ -161,7 +224,7 @@ static struct adc_dev_s g_adcdev =
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****************************************************************************/
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#ifdef CONFIG_SAMA5_ADC_REGDEBUG
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static bool sam_adc_checkreg(struct sam_gmac_s *priv, bool wr,
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static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
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uint32_t regval, uintptr_t address)
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{
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if (wr == priv->wrlast && /* Same kind of access? */
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@ -198,48 +261,7 @@ static bool sam_adc_checkreg(struct sam_gmac_s *priv, bool wr,
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}
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#endif
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/****************************************************************************
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* Name: sam_adc_getreg
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*
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* Description:
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* Read any 32-bit register using an absolute address.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_ADC_REGDEBUG
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static uint32_t sam_adc_getreg(struct sam_gmac_s *priv, uintptr_t address)
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{
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uint32_t regval = getreg32(address);
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if (sam_adc_checkreg(priv, false, regval, address))
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{
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lldbg("%08x->%08x\n", address, regval);
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}
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return regval;
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}
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#endif
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/****************************************************************************
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* Name: sam_adc_putreg
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*
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* Description:
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* Write to any 32-bit register using an absolute address.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_ADC_REGDEBUG
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static void sam_adc_putreg(struct sam_gmac_s *priv, uintptr_t address,
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uint32_t regval)
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{
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if (sam_adc_checkreg(priv, true, regval, address))
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{
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lldbg("%08x<-%08x\n", address, regval);
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}
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putreg32(regval, address);
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}
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#endif
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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/****************************************************************************
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* Name: sam_adc_reset
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@ -250,15 +272,20 @@ static void sam_adc_putreg(struct sam_gmac_s *priv, uintptr_t address,
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*
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****************************************************************************/
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static void sam_adc_reset(FAR struct adc_dev_s *dev)
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static void sam_adc_reset(struct adc_dev_s *dev)
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{
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FAR struct sam_adc_s *priv = (FAR struct sam_adc_s *)dev->ad_priv;
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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irqstate_t flags;
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uint32_t regval;
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flags = irqsave();
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#warning Missing logic
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/* Reset the ADC controller */
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flags = irqsave();
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sam_adc_putreg(priv, SAM_ADC_CR, ADC_CR_SWRST);
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/* Reset Mode Register */
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sam_adc_putreg(priv, SAM_ADC_MR, 0);
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irqrestore(flags);
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}
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@ -273,9 +300,9 @@ static void sam_adc_reset(FAR struct adc_dev_s *dev)
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*
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****************************************************************************/
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static int sam_adc_setup(FAR struct adc_dev_s *dev)
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static int sam_adc_setup(struct adc_dev_s *dev)
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{
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FAR struct sam_adc_s *priv = (FAR struct sam_adc_s *)dev->ad_priv;
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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int ret;
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/* Attach the ADC interrupt */
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@ -302,15 +329,15 @@ static int sam_adc_setup(FAR struct adc_dev_s *dev)
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*
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****************************************************************************/
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static void sam_adc_shutdown(FAR struct adc_dev_s *dev)
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static void sam_adc_shutdown(struct adc_dev_s *dev)
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{
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FAR struct sam_adc_s *priv = (FAR struct sam_adc_s *)dev->ad_priv;
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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/* Disable ADC interrupts, both at the level of the ADC device and at the
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* level of the NVIC.
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*/
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#warning Missing logic
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sam_adc_putreg32(priv, SAM_ADC_IDR, ADC_TSD_INTS);
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up_disable_irq(SAM_IRQ_ADC);
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/* Then detach the ADC interrupt handler. */
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@ -326,18 +353,23 @@ static void sam_adc_shutdown(FAR struct adc_dev_s *dev)
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*
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****************************************************************************/
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static void sam_adc_rxint(FAR struct adc_dev_s *dev, bool enable)
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static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
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{
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FAR struct sam_adc_s *priv = (FAR struct sam_adc_s *)dev->ad_priv;
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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/* Are we enabling or disabling? */
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if (enable)
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{
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#warning Missing logic
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/* Enable channel interrupts */
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sam_adc_putreg32(priv, SAM_ADC_IER, SAMA5_CHAN_ENABLE);
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}
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else
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{
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#warning Missing logic
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/* Disable channel interrupts */
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sam_adc_putreg32(priv, SAM_ADC_IDR, ADC_INT_EOCALL);
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}
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}
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@ -349,13 +381,44 @@ static void sam_adc_rxint(FAR struct adc_dev_s *dev, bool enable)
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*
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****************************************************************************/
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static int sam_adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
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static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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{
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/* No ioctl commands supported */
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return -ENOTTY;
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}
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/****************************************************************************
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* Name: sam_adc_endconversion
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*
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* Description:
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* End of conversion interrupt handler
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*
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****************************************************************************/
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static void sam_adc_endconversion(struct sam_adc_s *priv, uint32_t pending)
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{
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uint32_t regval;
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int chan;
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/* Check for the end of conversion event on each channel */
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for (chan = 0; chan < SAM_ADC_NCHANNELS && pending != 0; chan++)
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{
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uint32_t bit = ADC_INT_EOC(chan);
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if ((pending & bit) != 0)
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{
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/* Read the ADC sample and pass it to the upper half */
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regval = sam_adc_getreg(priv, SAM_ADC_CDR(chan));
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ret = adc_receive(&priv->dev, chan, regval & ADC_CDR_DATA_MASK);
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pending &= ~bit;
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}
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}
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}
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#endif /* SAMA5_ADC_HAVE_CHANNELS */
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/****************************************************************************
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* Name: sam_adc_interrupt
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*
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@ -366,11 +429,46 @@ static int sam_adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
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static int sam_adc_interrupt(int irq, void *context)
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{
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FAR struct sam_adc_s *priv = (FAR struct sam_adc_s *)g_adcdev.ad_priv;
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struct sam_adc_s *priv = (struct sam_adc_s *)g_adcdev.ad_priv;
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uint32_t regval;
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struct sam_adc_s *priv = &g_adcpriv;
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uint32_t isr;
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uint32_t imr;
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uint32_t pending;
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#warning Missing logic
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/* Get the set of unmasked, pending ADC interrupts */
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isr = sam_adc_getreg(priv, SAM_ADC_ISR);
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imr = sam_adc_getreg(priv, SAM_ADC_IMR);
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pending = isr & imr;
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/* Handle pending touchscreen interrupts */
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#ifdef CONFIG_SAMA5_TOUCHSCREEN
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if ((pending & ADC_TSD_INTS) != 0)
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{
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/* Let the touchscreen handle its interrupts */
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sam_tsd_interrupt(pending);
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pending &= ~ADC_TSD_INTS;
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}
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#endif
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#ifdef SAMA5_ADC_HAVE_CHANNELS
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/* Check for end-of-conversion interrupts */
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if ((pending & ADC_INT_EOCALL) != 0)
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{
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/* Let the touchscreen handle its interrupts */
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sam_adc_endconversion(pending);
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pending &= ~ADC_INT_EOCALL;
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}
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#endif
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/* Make sure that all interrupts were handled */
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DEBUGASSERT(pending == 0);
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return OK;
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}
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@ -389,12 +487,54 @@ static int sam_adc_interrupt(int irq, void *context)
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*
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****************************************************************************/
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FAR struct adc_dev_s *sam_adc_initialize(void)
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struct adc_dev_s *sam_adc_initialize(void)
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{
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/* Enable the ADC peripheral clock*/
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sam_adc_enableclk();
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/* Configure ADC pins */
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#ifdef CONFIG_SAMA5_ADC_CHAN0
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sam_configpio(PIO_ADC_AD0);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN1
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sam_configpio(PIO_ADC_AD1);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN2
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sam_configpio(PIO_ADC_AD2);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN3
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sam_configpio(PIO_ADC_AD3);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN4
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sam_configpio(PIO_ADC_AD4);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN5
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sam_configpio(PIO_ADC_AD5);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN6
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sam_configpio(PIO_ADC_AD6);
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#endif
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#ifdef CONFIG_SAMA5_ADC_CHAN7
|
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sam_configpio(PIO_ADC_AD7);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_ADC_CHAN8
|
||||
sam_configpio(PIO_ADC_AD8);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_ADC_CHAN9
|
||||
sam_configpio(PIO_ADC_AD9);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_ADC_CHAN10
|
||||
sam_configpio(PIO_ADC_AD10);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_ADC_CHAN11
|
||||
sam_configpio(PIO_ADC_AD11);
|
||||
#endif
|
||||
#if 0
|
||||
sam_configpio(PIO_ADC_TRG);
|
||||
#endif
|
||||
|
||||
/* Reset the ADC controller */
|
||||
|
||||
sam_adc_putreg(priv, SAM_ADC_CR, ADC_CR_SWRST);
|
||||
@ -408,4 +548,49 @@ FAR struct adc_dev_s *sam_adc_initialize(void)
|
||||
return &g_adcdev;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_adc_getreg
|
||||
*
|
||||
* Description:
|
||||
* Read any 32-bit register using an absolute address.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_ADC_REGDEBUG
|
||||
static uint32_t sam_adc_getreg(ADC_HANDLE handle, uintptr_t address)
|
||||
{
|
||||
struct sam_adc_s *priv = (struct sam_adc_s *)handle;
|
||||
uint32_t regval = getreg32(address);
|
||||
|
||||
if (sam_adc_checkreg(priv, false, regval, address))
|
||||
{
|
||||
lldbg("%08x->%08x\n", address, regval);
|
||||
}
|
||||
|
||||
return regval;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_adc_putreg
|
||||
*
|
||||
* Description:
|
||||
* Write to any 32-bit register using an absolute address.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_ADC_REGDEBUG
|
||||
void sam_adc_putreg(ADC_HANDLE handle, uintptr_t address, uint32_t regval)
|
||||
{
|
||||
struct sam_adc_s *priv = (struct sam_adc_s *)handle;
|
||||
|
||||
if (sam_adc_checkreg(priv, true, regval, address))
|
||||
{
|
||||
lldbg("%08x<-%08x\n", address, regval);
|
||||
}
|
||||
|
||||
putreg32(regval, address);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SAMA5_ADC */
|
||||
|
||||
@ -50,6 +50,40 @@
|
||||
****************************************************************************/
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#ifndef CONFIG_DEBUG
|
||||
# undef CONFIG_SAMA5_ADC_REGDEBUG
|
||||
#endif
|
||||
|
||||
/* ADC channels 0-3 or 0-4 are not available to the ADC driver if touchscreen
|
||||
* support is enabled.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SAMA5_TOUCHSCREEN
|
||||
# undef CONFIG_SAMA5_ADC_CHAN0
|
||||
# undef CONFIG_SAMA5_ADC_CHAN1
|
||||
# undef CONFIG_SAMA5_ADC_CHAN2
|
||||
# undef CONFIG_SAMA5_ADC_CHAN3
|
||||
# ifdef CONFIG_SAMA5_TOUCHSCREEN_5WIRE
|
||||
# undef CONFIG_SAMA5_ADC_CHAN4
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Do we have any ADC channels enabled? If not, then the ADC driver may
|
||||
* still need to exist to support the touchscreen.
|
||||
*/
|
||||
|
||||
#undef SAMA5_ADC_HAVE_CHANNELS
|
||||
#if defined(CONFIG_SAMA5_ADC_CHAN0) || defined(CONFIG_SAMA5_ADC_CHAN1) || \
|
||||
defined(CONFIG_SAMA5_ADC_CHAN2) || defined(CONFIG_SAMA5_ADC_CHAN3) || \
|
||||
defined(CONFIG_SAMA5_ADC_CHAN4) || defined(CONFIG_SAMA5_ADC_CHAN5) || \
|
||||
defined(CONFIG_SAMA5_ADC_CHAN6) || defined(CONFIG_SAMA5_ADC_CHAN7) || \
|
||||
defined(CONFIG_SAMA5_ADC_CHAN8) || defined(CONFIG_SAMA5_ADC_CHAN9) || \
|
||||
defined(CONFIG_SAMA5_ADC_CHAN10) || defined(CONFIG_SAMA5_ADC_CHAN11)
|
||||
# define SAMA5_ADC_HAVE_CHANNELS 1
|
||||
#elif !defined(CONFIG_SAMA5_TOUCHSCREEN)
|
||||
# error "No ADC channels nor touchscreen"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
@ -88,6 +122,35 @@ FAR struct adc_dev_s *sam_adcinitialize(void);
|
||||
* Interfaces exported from the ADC to the touchscreen driver
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_adc_getreg
|
||||
*
|
||||
* Description:
|
||||
* Read any 32-bit register using an absolute address.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_ADC_REGDEBUG
|
||||
uint32_t sam_adc_getreg(FAR struct adc_dev_s *, uintptr_t address)
|
||||
#else
|
||||
# define sam_adc_getreg(handle,addr) getreg32(addr)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_adc_putreg
|
||||
*
|
||||
* Description:
|
||||
* Write to any 32-bit register using an absolute address.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMA5_ADC_REGDEBUG
|
||||
void sam_adc_putreg(FAR struct adc_dev_s *dev, uintptr_t address,
|
||||
uint32_t regval)
|
||||
#else
|
||||
# define sam_adc_putreg(handle,addr,val) putreg32(val,addr)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@ -94,7 +94,7 @@ enum sam_contact_3
|
||||
CONTACT_UP, /* Contact lost */
|
||||
};
|
||||
|
||||
/* This structure describes the results of one ADS7843E sample */
|
||||
/* This structure describes the results of one touchscreen sample */
|
||||
|
||||
struct sam_sample_s
|
||||
{
|
||||
@ -105,11 +105,11 @@ struct sam_sample_s
|
||||
uint16_t y; /* Measured Y position */
|
||||
};
|
||||
|
||||
/* This structure describes the state of one ADS7843E driver instance */
|
||||
/* This structure describes the state of one touchscreen driver instance */
|
||||
|
||||
struct sam_dev_s
|
||||
{
|
||||
uint8_t nwaiters; /* Number of threads waiting for ADS7843E data */
|
||||
uint8_t nwaiters; /* Number of threads waiting for touchscreen data */
|
||||
uint8_t id; /* Current touch point ID */
|
||||
volatile bool penchange; /* An unreported event is buffered */
|
||||
uint16_t threshx; /* Thresholding X value */
|
||||
@ -117,6 +117,7 @@ struct sam_dev_s
|
||||
sem_t devsem; /* Manages exclusive access to this structure */
|
||||
sem_t waitsem; /* Used to wait for the availability of data */
|
||||
|
||||
struct adc_dev_s *dev; /* ADC device handle */
|
||||
struct work_s work; /* Supports the interrupt handling "bottom half" */
|
||||
struct sam_sample_s sample; /* Last sampled touch point data */
|
||||
WDOG_ID wdog; /* Poll the position while the pen is down */
|
||||
@ -127,7 +128,7 @@ struct sam_dev_s
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_DISABLE_POLL
|
||||
struct pollfd *fds[CONFIG_ADS7843E_NPOLLWAITERS];
|
||||
struct pollfd *fds[CONFIG_SAMA5_TSD_NPOLLWAITERS];
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -198,14 +199,14 @@ static void sam_notify(FAR struct sam_dev_s *priv)
|
||||
|
||||
if (priv->nwaiters > 0)
|
||||
{
|
||||
/* After posting this semaphore, we need to exit because the ADS7843E
|
||||
/* After posting this semaphore, we need to exit because the touchscreen
|
||||
* is no longer available.
|
||||
*/
|
||||
|
||||
sem_post(&priv->waitsem);
|
||||
}
|
||||
|
||||
/* If there are threads waiting on poll() for ADS7843E data to become available,
|
||||
/* If there are threads waiting on poll() for touchscreen data to become available,
|
||||
* then wake them up now. NOTE: we wake up all waiting threads because we
|
||||
* do not know that they are going to do. If they all try to read the data,
|
||||
* then some make end up blocking after all.
|
||||
@ -242,7 +243,7 @@ static int sam_sample(FAR struct sam_dev_s *priv,
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
/* Is there new ADS7843E sample data available? */
|
||||
/* Is there new touchscreen sample data available? */
|
||||
|
||||
if (priv->penchange)
|
||||
{
|
||||
@ -368,10 +369,11 @@ static int sam_schedule(FAR struct sam_dev_s *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Disable further interrupts. touchscreen ADC interrupts will be re-enabled
|
||||
* after the worker thread executes.
|
||||
/* Disable further touchscreen interrupts. Touchscreen interrupts will be
|
||||
* re-enabled after the worker thread executes.
|
||||
*/
|
||||
#warning "Missing logic"
|
||||
|
||||
sam_adc_putreg32(priv->dev, SAM_ADC_IDR, ADC_TSD_INTS);
|
||||
|
||||
/* Disable the watchdog timer. It will be re-enabled in the worker thread
|
||||
* while the pen remains down.
|
||||
@ -545,19 +547,16 @@ static void sam_bottomhalf(FAR void *arg)
|
||||
priv->sample.id = priv->id;
|
||||
priv->penchange = true;
|
||||
|
||||
/* Notify any waiters that new ADS7843E data is available */
|
||||
/* Notify any waiters that new touchscreen data is available */
|
||||
|
||||
sam_notify(priv);
|
||||
|
||||
/* Exit, re-enabling ADS7843E interrupts */
|
||||
/* Exit, re-enabling touchscreen interrupts */
|
||||
|
||||
ignored:
|
||||
/* Re-enable touchscreen interrupts. */
|
||||
|
||||
/* Re-enable the PENIRQ interrupts */
|
||||
#warning Missing logic
|
||||
|
||||
/* Re-enable the PENIRQ interrupt at the MCU's interrupt controller */
|
||||
#warning Missing logic
|
||||
sam_adc_putreg32(priv->dev, SAM_ADC_IER, ADC_TSD_INTS);
|
||||
|
||||
/* Release our lock on the state structure */
|
||||
|
||||
@ -658,7 +657,7 @@ static ssize_t sam_read(FAR struct file *filep, FAR char *buffer, size_t len)
|
||||
}
|
||||
}
|
||||
|
||||
/* In any event, we now have sampled ADS7843E data that we can report
|
||||
/* In any event, we now have sampled touchscreen data that we can report
|
||||
* to the caller.
|
||||
*/
|
||||
|
||||
@ -870,9 +869,9 @@ errout:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int sam_tsd_register(int minor)
|
||||
int sam_tsd_register(struct adc_dev_s *dev, int minor)
|
||||
{
|
||||
FAR struct sam_dev_s *priv = &g_tsd;
|
||||
struct sam_dev_s *priv = &g_tsd;
|
||||
char devname[DEV_NAMELEN];
|
||||
int ret;
|
||||
|
||||
@ -880,11 +879,12 @@ int sam_tsd_register(int minor)
|
||||
|
||||
/* Debug-only sanity checks */
|
||||
|
||||
DEBUGASSERT(minor >= 0 && minor < 100);
|
||||
DEBUGASSERT(dev && minor >= 0 && minor < 100);
|
||||
|
||||
/* Initialize the touchscreen device driver instance */
|
||||
|
||||
memset(priv, 0, sizeof(struct sam_dev_s));
|
||||
priv->dev = dev; /* Save the ADC device handle */
|
||||
priv->wdog = wd_create(); /* Create a watchdog timer */
|
||||
priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */
|
||||
priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */
|
||||
@ -945,20 +945,25 @@ errout_with_priv:
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_tsd_interrupt(void)
|
||||
{
|
||||
FAR struct sam_dev_s *priv = &g_tsd;
|
||||
struct sam_dev_s *priv = &g_tsd;
|
||||
int ret;
|
||||
|
||||
/* Disable further touchscreen interrupts */
|
||||
|
||||
sam_adc_putreg32(priv->dev, SAM_ADC_IDR, ADC_TSD_INTS);
|
||||
|
||||
/* Schedule sampling to occur on the worker thread */
|
||||
|
||||
ret = sam_schedule(priv);
|
||||
|
||||
/* Clear any pending interrupts and return success */
|
||||
#warning Missing logic
|
||||
if (ret < 0)
|
||||
{
|
||||
idbg("ERROR: sam_schedule failed: %d\n", ret);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@ -79,7 +79,8 @@ extern "C"
|
||||
* /dev/inputN where N is the minor device number
|
||||
*
|
||||
* Input Parameters:
|
||||
* minor - The input device minor number
|
||||
* dev - The ADC device handle received from sam_adc_initialize()
|
||||
* minor - The input device minor number
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero is returned on success. Otherwise, a negated errno value is
|
||||
@ -87,7 +88,7 @@ extern "C"
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int sam_tsd_register(int minor);
|
||||
int sam_tsd_register(FAR struct adc_dev_s *dev, int minor);
|
||||
|
||||
/****************************************************************************
|
||||
* Interfaces exported from the touchscreen to the ADC driver
|
||||
@ -99,14 +100,14 @@ int sam_tsd_register(int minor);
|
||||
* Handles ADC interrupts associated with touchscreen channels
|
||||
*
|
||||
* Input parmeters:
|
||||
* None
|
||||
* pending - Current set of pending interrupts being handled
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_tsd_interrupt(void);
|
||||
void sam_tsd_interrupt(uint32_t pending);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -129,7 +129,7 @@ struct adc_ops_s
|
||||
};
|
||||
|
||||
/* This is the device structure used by the driver. The caller of
|
||||
* can_register() must allocate and initialize this structure. The
|
||||
* adc_register() must allocate and initialize this structure. The
|
||||
* calling logic need only set all fields to zero except:
|
||||
*
|
||||
* The elements of 'ad_ops', and 'ad_priv'
|
||||
|
||||
Loading…
Reference in New Issue
Block a user