From e7bb9f714e420b38c9da95853c9693316d3d2a6f Mon Sep 17 00:00:00 2001 From: kfazz Date: Mon, 6 Jun 2016 13:50:58 -0400 Subject: [PATCH 01/18] include so OK is defined. --- configs/teensy-3.x/src/k20_appinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c index fd1b2bd5c8..a66f7a38b0 100644 --- a/configs/teensy-3.x/src/k20_appinit.c +++ b/configs/teensy-3.x/src/k20_appinit.c @@ -38,7 +38,7 @@ ****************************************************************************/ #include - +#include #include #include "teensy-3x.h" From 0a4c58e573f9de6461250e3785c76f7c43afca45 Mon Sep 17 00:00:00 2001 From: kfazz Date: Mon, 6 Jun 2016 13:58:07 -0400 Subject: [PATCH 02/18] First attempt at a usb device controller driver for kinetis. derived from pic32mx usb driver, which uses the same usb controller. --- arch/arm/src/kinetis/kinetis_usbdev.c | 4688 +++++++++++++++++++++++++ arch/arm/src/kinetis/kinetis_usbotg.h | 55 +- 2 files changed, 4741 insertions(+), 2 deletions(-) create mode 100644 arch/arm/src/kinetis/kinetis_usbdev.c diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c new file mode 100644 index 0000000000..75fcdb2cc7 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -0,0 +1,4688 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_usbdev.c + * + * Copyright (C) 2011-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * This file derives from the STM32 USB device driver with modifications + * based on additional information from: + * + * - "USB On-The-Go (OTG)", DS61126E, Microchip Technology Inc., 2009 + * - Sample code provided with the Sure Electronics PIC32 board + * (which seems to have derived from Microchip PICDEM PIC18 code). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +//#include "pic32mx.h" +//#include "pic32mx-usbotg.h" +#include "kinetis.h" +#include "kinetis_usbotg.h" +#include "kinetis_sim.h" +#include "kinetis_fmc.h" + +#if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USBOTG) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +//#define CONFIG_USBOTG + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +/* Extremely detailed register/BDT debug that you would normally never want + * enabled. + */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_KHCI_USBDEV_REGDEBUG +# undef CONFIG_KHCI_USBDEV_BDTDEBUG +#endif + +//#define CONFIG_KHCI_USBDEV_REGDEBUG +//#define CONFIG_KHCI_USBDEV_BDTDEBUG + +/* Disable this logic because it is buggy. It works most of the time but + * has some lurking issues that keep this higher performance solution from + * being usable. + */ + +#undef CONFIG_USBDEV_NOREADAHEAD /* Makes no difference */ + +#undef CONFIG_USBDEV_NOWRITEAHEAD +#define CONFIG_USBDEV_NOWRITEAHEAD 1 /* Fixes some problems with IN transfers */ + +/* Interrupts ***************************************************************/ +/* Initial interrupt sets */ + +//#define CONFIG_USB_SOFINTS + +#ifdef CONFIG_USB_SOFINTS +# define USB_SOF_INTERRUPT USB_INT_SOFTOK +#else +# define USB_SOF_INTERRUPT 0 +#endif + +#define ERROR_INTERRUPTS (USB_ERRSTAT_PIDERR | USB_ERRSTAT_CRC5EOF | \ + USB_ERRSTAT_CRC16 | USB_ERRSTAT_DFN8 | USB_ERRSTAT_BTOERR | \ + USB_ERRSTAT_BTSERR) + +#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \ + USB_INT_TOKDNE | USB_INT_SLEEP | USB_INT_STALL) + +/* Endpoints ****************************************************************/ + +#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */ + +#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */ +#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */ + +#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */ +#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */ + +#define KHCI_NENDPOINTS (16) +#define EP0 (0) + +#define KHCI_ENDP_BIT(ep) (1 << (ep)) +#define KHCI_ENDP_ALLSET 0xffff + +/* BDT Table Indexing. The BDT is addressed in the hardware as follows: + * + * Bits 9-31: These come the BDT address bits written into the BDTP3, + * BDTP2, and BDTP1 registers + * Bits 5-8: The endpoint number + * Bit 4: Direction: + * 1 = Transmit: SETUP/OUT for host, IN for function + * 0 = Receive: IN for host, SETUP/OUT for function + * Bit 3: PPBI, the ping point buffer index bit (0=EVEN, 1=ODD) + * Bits 0-2: Supports 8-byte BDT entries + */ + +#define EP0_OUT_EVEN (0) +#define EP0_OUT_ODD (1) +#define EP0_IN_EVEN (2) +#define EP0_IN_ODD (3) +#define EP_OUT_EVEN(ep) ((int)(ep) << 2) +#define EP_OUT_ODD(ep) (((int)(ep) << 2) + 1) +#define EP_IN_EVEN(ep) (((int)(ep) << 2) + 2) +#define EP_IN_ODD(ep) (((int)(ep) << 2) + 3) + +#define EP(ep,dir,pp) (((int)(ep) << 2) + ((int)(dir) << 1) + (int)(pp)) +#define EP_DIR_OUT 0 +#define EP_DIR_IN 1 +#define EP_PP_EVEN 0 +#define EP_PP_ODD 1 + +/* Packet sizes. We use a fixed 64 max packet size for all endpoint types */ + +#define KHCI_MAXPACKET_SHIFT (6) +#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT)) + +#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE + +/* Endpoint register initialization parameters */ + +#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK|USB_ENDPT_EPTXEN|USB_ENDPT_EPRXEN) +#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) +#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) +#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) +#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) +#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS) +#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS) + +/* USB-related masks */ + +#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK) + +/* Request queue operations *************************************************/ + +#define khci_rqempty(q) ((q)->head == NULL) +#define khci_rqhead(q) ((q)->head) +#define khci_rqtail(q) ((q)->tail) + +#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000) + +/* USB trace ****************************************************************/ +/* Trace error codes */ + +#define KHCI_TRACEERR_ALLOCFAIL 0x0001 +#define KHCI_TRACEERR_BADCLEARFEATURE 0x0002 +#define KHCI_TRACEERR_BADDEVGETSTATUS 0x0003 +#define KHCI_TRACEERR_BADEPGETSTATUS 0x0004 +#define KHCI_TRACEERR_BADEPNO 0x0005 +#define KHCI_TRACEERR_BADEPTYPE 0x0006 +#define KHCI_TRACEERR_BADGETCONFIG 0x0007 +#define KHCI_TRACEERR_BADGETSETDESC 0x0008 +#define KHCI_TRACEERR_BADGETSTATUS 0x0009 +#define KHCI_TRACEERR_BADSETADDRESS 0x000a +#define KHCI_TRACEERR_BADSETCONFIG 0x000b +#define KHCI_TRACEERR_BADSETFEATURE 0x000c +#define KHCI_TRACEERR_BINDFAILED 0x000d +#define KHCI_TRACEERR_DISPATCHSTALL 0x000e +#define KHCI_TRACEERR_DRIVER 0x000f +#define KHCI_TRACEERR_DRIVERREGISTERED 0x0010 +#define KHCI_TRACEERR_EP0SETUPSTALLED 0x0011 +#define KHCI_TRACEERR_EPDISABLED 0x0012 +#define KHCI_TRACEERR_EPOUTNULLPACKET 0x0013 +#define KHCI_TRACEERR_EPRESERVE 0x0014 +#define KHCI_TRACEERR_INVALIDCTRLREQ 0x0015 +#define KHCI_TRACEERR_INVALIDPARMS 0x0016 +#define KHCI_TRACEERR_IRQREGISTRATION 0x0017 +#define KHCI_TRACEERR_NOTCONFIGURED 0x0018 +#define KHCI_TRACEERR_REQABORTED 0x0019 +#define KHCI_TRACEERR_INVALIDSTATE 0x001a + +/* Trace interrupt codes */ + +#define KHCI_TRACEINTID_CLEARFEATURE 0x0001 +#define KHCI_TRACEINTID_DEVGETSTATUS 0x0002 +#define KHCI_TRACEINTID_DISPATCH 0x0003 +#define KHCI_TRACEINTID_EP0IN 0x0004 +#define KHCI_TRACEINTID_EP0INDONE 0x0005 +#define KHCI_TRACEINTID_EP0OUTDONE 0x0006 +#define KHCI_TRACEINTID_EP0SETUPDONE 0x0007 +#define KHCI_TRACEINTID_EP0SETUPSETADDRESS 0x0008 +#define KHCI_TRACEINTID_EP0ADDRESSSET 0x0009 +#define KHCI_TRACEINTID_EPGETSTATUS 0x000a +#define KHCI_TRACEINTID_EPINDONE 0x000b +#define KHCI_TRACEINTID_EPINQEMPTY 0x000c +#define KHCI_TRACEINTID_EPOUTDONE 0x000d +#define KHCI_TRACEINTID_EPOUTQEMPTY 0x000e +#define KHCI_TRACEINTID_SOF 0x000f +#define KHCI_TRACEINTID_GETCONFIG 0x0010 +#define KHCI_TRACEINTID_GETSETDESC 0x0011 +#define KHCI_TRACEINTID_GETSETIF 0x0012 +#define KHCI_TRACEINTID_GETSTATUS 0x0013 +#define KHCI_TRACEINTID_IFGETSTATUS 0x0014 +#define KHCI_TRACEINTID_TRNC 0x0015 +#define KHCI_TRACEINTID_TRNCS 0x0016 +#define KHCI_TRACEINTID_INTERRUPT 0x0017 +#define KHCI_TRACEINTID_NOSTDREQ 0x0018 +#define KHCI_TRACEINTID_RESET 0x0019 +#define KHCI_TRACEINTID_SETCONFIG 0x001a +#define KHCI_TRACEINTID_SETFEATURE 0x001b +#define KHCI_TRACEINTID_IDLE 0x001c +#define KHCI_TRACEINTID_SYNCHFRAME 0x001d +#define KHCI_TRACEINTID_WKUP 0x001e +#define KHCI_TRACEINTID_T1MSEC 0x001f +#define KHCI_TRACEINTID_OTGID 0x0020 +#define KHCI_TRACEINTID_STALL 0x0021 +#define KHCI_TRACEINTID_UERR 0x0022 +#define KHCI_TRACEINTID_SUSPENDED 0x0023 +#define KHCI_TRACEINTID_WAITRESET 0x0024 + + + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), //0001 + TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), //0002 + TRACE_STR(KHCI_TRACEINTID_DISPATCH ), //0003 + TRACE_STR(KHCI_TRACEINTID_EP0IN ), //0004 + TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), //0005 + TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), //0006 + TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), //0007 + TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), //0008 + TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), //0009 + TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), //000a + TRACE_STR(KHCI_TRACEINTID_EPINDONE ), //000b + TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), //000c + TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), //000d + TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), //000e + TRACE_STR(KHCI_TRACEINTID_SOF ), //000f + TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), //0010 + TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), //0011 + TRACE_STR(KHCI_TRACEINTID_GETSETIF ), //0012 + TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), //0013 + TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), //0014 + TRACE_STR(KHCI_TRACEINTID_TRNC ), //0015 + TRACE_STR(KHCI_TRACEINTID_TRNCS ), //0016 + TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), //0017 + TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), //0018 + TRACE_STR(KHCI_TRACEINTID_RESET ), //0019 + TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), //001a + TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), //001b + TRACE_STR(KHCI_TRACEINTID_IDLE ), //001c + TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), //001d + TRACE_STR(KHCI_TRACEINTID_WKUP ), //001e + TRACE_STR(KHCI_TRACEINTID_T1MSEC ), //001f + TRACE_STR(KHCI_TRACEINTID_OTGID ), //0020 + TRACE_STR(KHCI_TRACEINTID_STALL ), //0021 + TRACE_STR(KHCI_TRACEINTID_UERR ), //0022 + TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), //0023 + TRACE_STR(KHCI_TRACEINTID_WAITRESET ), //0024 + TRACE_STR_END +}; +#endif + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), //0001 + TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), //0002 + TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), //0003 + TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), //0004 + TRACE_STR(KHCI_TRACEERR_BADEPNO ), //0005 + TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), //0006 + TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), //0007 + TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), //0008 + TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), //0009 + TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), //000a + TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), //000b + TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), //000c + TRACE_STR(KHCI_TRACEERR_BINDFAILED ), //000d + TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), //000e + TRACE_STR(KHCI_TRACEERR_DRIVER ), //000f + TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), //0010 + TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), //0011 + TRACE_STR(KHCI_TRACEERR_EPDISABLED ), //0012 + TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), //0013 + TRACE_STR(KHCI_TRACEERR_EPRESERVE ), //0014 + TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), //0015 + TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), //0016 + TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), //0017 + TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), //0018 + TRACE_STR(KHCI_TRACEERR_REQABORTED ), //0019 + TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), //001a + TRACE_STR_END +}; +#endif + +/* Misc Helper Macros *******************************************************/ + +/* Ever-present MIN and MAX macros */ + +#ifndef MIN +# define MIN(a,b) (a < b ? a : b) +#endif + +#ifndef MAX +# define MAX(a,b) (a > b ? a : b) +#endif + +/* Byte ordering in host-based values */ + +#ifdef CONFIG_ENDIAN_BIG +# define LSB 1 +# define MSB 0 +#else +# define LSB 0 +# define MSB 1 +#endif + +/* Debug ********************************************************************/ +/* CONFIG_KHCI_USBDEV_REGDEBUG enables dumping of all low-level register + * access and BDT accesses. Normally, this generates so much debug output + * that USB may not even be functional. + */ + +#ifdef CONFIG_KHCI_USBDEV_REGDEBUG + +# undef CONFIG_KHCI_USBDEV_BDTDEBUG +# define CONFIG_KHCI_USBDEV_BDTDEBUG 1 + +# define regdbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define regvdbg lldbg +# else +# define regvdbg(x...) +# endif + +#else + +# define khci_getreg(addr) getreg8(addr) +# define khci_putreg(val,addr) putreg8(val,addr) +# define regdbg(x...) +# define regvdbg(x...) + +#endif + +/* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */ + +#ifdef CONFIG_KHCI_USBDEV_BDTDEBUG + +# define bdtdbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define bdtvdbg lldbg +# else +# define bdtvdbg(x...) +# endif + +#else + +# define bdtdbg(x...) +# define bdtvdbg(x...) + +#endif + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + +/* Overvall device state */ + +enum khci_devstate_e +{ + DEVSTATE_DETACHED = 0, /* Not connected to a host */ + DEVSTATE_ATTACHED, /* Connected to a host */ + DEVSTATE_POWERED, /* Powered */ + DEVSTATE_DEFAULT, /* Default state */ + DEVSTATE_ADDRPENDING, /* Waiting for an address */ + DEVSTATE_ADDRESS, /* Address received */ + DEVSTATE_CONFIGURED, /* Configuration received */ +}; + +/* The various states of the control pipe */ + +enum khci_ctrlstate_e +{ + CTRLSTATE_WAITSETUP = 0, /* No request in progress, waiting for setup */ + CTRLSTATE_RDREQUEST, /* Read request (OUT) in progress */ + CTRLSTATE_WRREQUEST, /* Write request (IN) in progress */ + CTRLSTATE_STALL, /* EP0 stall requested */ + CTRLSTATE_STALLED /* EP0 is stalled */ +}; + +union wb_u +{ + uint16_t w; + uint8_t b[2]; +}; + +/* A container for a request so that the request make be retained in a + * singly-linked list. + */ + +struct khci_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ +#ifdef CONFIG_USBDEV_NOWRITEAHEAD + uint16_t inflight[1]; /* The number of bytes "in-flight" */ +#else + uint16_t inflight[2]; /* The number of bytes "in-flight" */ +#endif + struct khci_req_s *flink; /* Supports a singly linked list */ +}; + +/* This structure represents the 'head' of a singly linked list of requests */ + +struct khci_queue_s +{ + struct khci_req_s *head; /* Head of the request queue */ + struct khci_req_s *tail; /* Tail of the request queue */ +}; + +/* This is the internal representation of an endpoint */ + +struct khci_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct khci_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* KHCI-specific fields */ + + struct khci_usbdev_s *dev; /* Reference to private driver data */ + struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */ + struct khci_queue_s active; /* List of active requests for this endpoint */ + uint8_t stalled:1; /* true: Endpoint is stalled */ + uint8_t halted:1; /* true: Endpoint feature halted */ + uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */ + uint8_t txdata1:1; /* Data0/1 of next TX transfer */ + uint8_t rxdata1:1; /* Data0/1 of next RX transfer */ + volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction */ + volatile struct usbotg_bdtentry_s *bdtout; /* BDT entry for the OUT transaction */ +}; + +struct khci_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to structkhci_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* KHCI-specific fields */ + + struct usb_ctrlreq_s ctrl; /* Last EP0 request */ + uint8_t devstate; /* Driver state (see enum khci_devstate_e) */ + uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t rwakeup:1; /* 1: Device supports remote wakeup */ + uint8_t attached:1; /* Device is attached to the host */ + uint8_t ep0done:1; /* EP0 OUT already prepared */ + uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */ + uint16_t epavail; /* Bitset of available endpoints */ + uint16_t epstalled; /* Bitset of stalled endpoints */ + WDOG_ID wdog; /* Supports the restart delay */ + + /* The endpoint list */ + + struct khci_ep_s eplist[KHCI_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_KHCI_USBDEV_REGDEBUG +static uint16_t khci_getreg(uint32_t addr); +static void khci_putreg(uint32_t val, uint32_t addr); +#endif + +/* Suspend/Resume Helpers ***************************************************/ + +static void khci_suspend(struct khci_usbdev_s *priv); +static void khci_resume(struct khci_usbdev_s *priv); + +/* Request Queue Management *************************************************/ + +static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue); +static struct khci_req_s *khci_remlast(struct khci_queue_s *queue); +static void khci_addlast(struct khci_queue_s *queue, + struct khci_req_s *req); +static void khci_addfirst(struct khci_queue_s *queue, + struct khci_req_s *req); + +/* Request Helpers **********************************************************/ + +static void khci_reqreturn(struct khci_ep_s *privep, + struct khci_req_s *privreq, int16_t result); +static void khci_reqcomplete(struct khci_ep_s *privep, + int16_t result); +static void khci_epwrite(struct khci_ep_s *privep, + volatile struct usbotg_bdtentry_s *bdt, + const uint8_t *src, uint32_t nbytes); +static void khci_wrcomplete(struct khci_usbdev_s *priv, + struct khci_ep_s *privep); +static void khci_rqrestart(int argc, uint32_t arg1, ...); +static void khci_delayedrestart(struct khci_usbdev_s *priv, + uint8_t epno); +static void khci_rqstop(struct khci_ep_s *privep); +static int khci_wrstart(struct khci_usbdev_s *priv, + struct khci_ep_s *privep); +static int khci_wrrequest(struct khci_usbdev_s *priv, + struct khci_ep_s *privep); +static int khci_rdcomplete(struct khci_usbdev_s *priv, + struct khci_ep_s *privep); +static int khci_ep0rdsetup(struct khci_usbdev_s *priv, + uint8_t *dest, int readlen); +static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, + int readlen); +static int khci_rdrequest(struct khci_usbdev_s *priv, + struct khci_ep_s *privep); +static void khci_cancelrequests(struct khci_ep_s *privep, + int16_t result); + +/* Interrupt level processing ***********************************************/ + +static void khci_dispatchrequest(struct khci_usbdev_s *priv); +static void khci_ep0stall(struct khci_usbdev_s *priv); +static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno, + uint16_t ustat); +static void khci_ep0nextsetup(struct khci_usbdev_s *priv); +static void khci_ep0rdcomplete(struct khci_usbdev_s *priv); +static void khci_ep0setup(struct khci_usbdev_s *priv); +static void khci_ep0outcomplete(struct khci_usbdev_s *priv); +static void khci_ep0incomplete(struct khci_usbdev_s *priv); +static void khci_ep0transfer(struct khci_usbdev_s *priv, + uint16_t ustat); +static int khci_interrupt(int irq, void *context); + +/* Endpoint helpers *********************************************************/ + +static inline struct khci_ep_s * + khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset); +static inline void + khci_epunreserve(struct khci_usbdev_s *priv, + struct khci_ep_s *privep); +static inline bool + khci_epreserved(struct khci_usbdev_s *priv, int epno); +static void khci_ep0configure(struct khci_usbdev_s *priv); + +/* Endpoint operations ******************************************************/ + +static int khci_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static int khci_epdisable(struct usbdev_ep_s *ep); +static struct usbdev_req_s * + khci_epallocreq(struct usbdev_ep_s *ep); +static void khci_epfreereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); +static int khci_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int khci_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, + bool epin); +static int khci_epstall(struct usbdev_ep_s *ep, bool resume); + +/* USB device controller operations *****************************************/ + +static struct usbdev_ep_s * + khci_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + uint8_t eptype); +static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int khci_getframe(struct usbdev_s *dev); +static int khci_wakeup(struct usbdev_s *dev); +static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered); + +/* Initialization/Reset *****************************************************/ + +static void khci_reset(struct khci_usbdev_s *priv); +static void khci_attach(struct khci_usbdev_s *priv); +static void khci_detach(struct khci_usbdev_s *priv); +static void khci_swreset(struct khci_usbdev_s *priv); +static void khci_hwreset(struct khci_usbdev_s *priv); +static void khci_stateinit(struct khci_usbdev_s *priv); +static void khci_hwshutdown(struct khci_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct khci_usbdev_s g_usbdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = khci_epconfigure, + .disable = khci_epdisable, + .allocreq = khci_epallocreq, + .freereq = khci_epfreereq, + .submit = khci_epsubmit, + .cancel = khci_epcancel, + .stall = khci_epstall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = khci_allocep, + .freeep = khci_freeep, + .getframe = khci_getframe, + .wakeup = khci_wakeup, + .selfpowered = khci_selfpowered, + .pullup = kinetis_usbpullup, +}; + +/* Buffer Descriptor Table. Four BDT entries per endpoint + * + * The BDT is addressed in the hardware as follows: + * + * Bits 9-31: These come the BDT address bits written into the BDTP3, BDTP2 + * and BDTP1 registers + * Bits 5-8: The endpoint number + * Bit 4: Direction (0=IN/Tx, 1 = OUT/Rx) + * Bit 3: PPBI, the ping point buffer index bit. + * Bits 0-2: Supports 8-byte BDT entries + */ + +static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS] + __attribute__ ((aligned(512))); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Register Operations + ****************************************************************************/ +/**************************************************************************** + * Name: khci_getreg + ****************************************************************************/ + +#ifdef CONFIG_KHCI_USBDEV_REGDEBUG +static uint16_t khci_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint16_t val = getreg8(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + lldbg("...\n"); + } + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + lldbg("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + lldbg("%08x->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: khci_putreg + ****************************************************************************/ + +#ifdef CONFIG_KHCI_USBDEV_REGDEBUG +static void khci_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + lldbg("%08x<-%04x\n", addr, val); + + /* Write the value */ + + putreg8(val, addr); +} +#endif + +/**************************************************************************** + * Request Helpers + ****************************************************************************/ +/**************************************************************************** + * Name: khci_remfirst + ****************************************************************************/ + +static struct khci_req_s *khci_remfirst(struct khci_queue_s *queue) +{ + struct khci_req_s *ret = queue->head; + + if (ret) + { + queue->head = ret->flink; + if (!queue->head) + { + queue->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + + +/**************************************************************************** + * Name: khci_remlast + ****************************************************************************/ + +static struct khci_req_s *khci_remlast(struct khci_queue_s *queue) +{ + struct khci_req_s *prev; + struct khci_req_s *ret = queue->tail; + + ret = queue->tail; + if (ret) + { + if (queue->head == queue->tail) + { + queue->head = NULL; + queue->tail = NULL; + } + else + { + for (prev = queue->head; + prev && prev->flink != ret; + prev = prev->flink); + + if (prev) + { + prev->flink = NULL; + queue->tail = prev; + } + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: khci_addlast + ****************************************************************************/ + +static void khci_addlast(struct khci_queue_s *queue, struct khci_req_s *req) +{ + req->flink = NULL; + if (!queue->head) + { + queue->head = req; + queue->tail = req; + } + else + { + queue->tail->flink = req; + queue->tail = req; + } +} + +/**************************************************************************** + * Name: khci_addfirst + ****************************************************************************/ + +static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req) +{ + req->flink = queue->head; + if (!queue->head) + { + queue->tail = req; + } + queue->head = req; +} + +/**************************************************************************** + * Name: khci_reqreturn + ****************************************************************************/ + +static void khci_reqreturn(struct khci_ep_s *privep, + struct khci_req_s *privreq, int16_t result) +{ + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (USB_EPNO(privep->ep.eplog) == EP0) + { + privep->stalled = (privep->dev->ctrlstate == CTRLSTATE_STALLED); + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->flink = NULL; + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; +} + +/**************************************************************************** + * Name: khci_reqcomplete + ****************************************************************************/ + +static void khci_reqcomplete(struct khci_ep_s *privep, int16_t result) +{ + struct khci_req_s *privreq; + irqstate_t flags; + + /* Remove the completed request at the head of the endpoint's active + * request list. + */ + + flags = enter_critical_section(); + privreq = khci_remfirst(&privep->active); + leave_critical_section(flags); + + if (privreq) + { + /* Return the request to the class driver */ + + khci_reqreturn(privep, privreq, result); + } +} + +/**************************************************************************** + * Name: khci_epwrite + ****************************************************************************/ + +static void khci_epwrite(struct khci_ep_s *privep, + volatile struct usbotg_bdtentry_s *bdt, + const uint8_t *src, uint32_t nbytes) +{ + uint32_t status; + + usbtrace(TRACE_WRITE(USB_EPNO(privep->ep.eplog)), nbytes); + + /* Clear all bits in the status (assuring that we own the BDT) */ + + bdt->status = 0; + + /* Get the correct data toggle (as well as other BDT bits) */ + + if (privep->txdata1) + { + status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS); + privep->txdata1 = 0; + } + else + { + status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS); + privep->txdata1 = 1; + } + + /* Set the data pointer and data length */ + + bdt->addr = (uint8_t *)src; + status |= (nbytes << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS; + + /* And, finally, give the BDT to the USB */ + + bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n", + USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr); + + bdt->status = status; +} + +/**************************************************************************** + * Name: khci_wrcomplete + ****************************************************************************/ + +static void khci_wrcomplete(struct khci_usbdev_s *priv, + struct khci_ep_s *privep) +{ + volatile struct usbotg_bdtentry_s *bdtin; + struct khci_req_s *privreq; + int bytesleft; + int epno; + + /* Check the request at the head of the endpoint's active request queue. + * Since we got here from a write completion event, the active request queue + * should not be empty. + */ + + privreq = khci_rqhead(&privep->active); + DEBUGASSERT(privreq != NULL); + + /* An outgoing IN packet has completed. bdtin should point to the BDT + * that just completed. + */ + + bdtin = privep->bdtin; + epno = USB_EPNO(privep->ep.eplog); + +#ifdef CONFIG_USBDEV_NOWRITEAHEAD + ullvdbg("EP%d: len=%d xfrd=%d inflight=%d\n", + epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]); +#else + ullvdbg("EP%d: len=%d xfrd=%d inflight={%d, %d}\n", + epno, privreq->req.len, privreq->req.xfrd, + privreq->inflight[0], privreq->inflight[1]); +#endif + bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdtin, bdtin->status, bdtin->addr); + + /* We should own the BDT that just completed. But NULLify the entire BDT IN. + * Why? So that we can tell later that the BDT available. No, it is not + * sufficient to look at the UOWN bit. If UOWN==0, then the transfer has + * been completed BUT it may not yet have been processed. But a completely + * NULLified BDT is a sure indication + */ + + DEBUGASSERT((bdtin->status & USB_BDT_UOWN) == USB_BDT_COWN); + bdtin->status = 0; + bdtin->addr = 0; + + /* Toggle bdtin to the other BDT. Is the current bdtin the EVEN bdt? */ + + privep->bdtin = &g_bdt[EP_IN_EVEN(epno)]; + if (bdtin == privep->bdtin) + { + /* Yes.. Then the other BDT is the ODD BDT */ + + privep->bdtin++; + } + + /* Update the number of bytes transferred. */ + + privreq->req.xfrd += privreq->inflight[0]; +#ifdef CONFIG_USBDEV_NOWRITEAHEAD + privreq->inflight[0] = 0; +#else + privreq->inflight[0] = privreq->inflight[1]; + privreq->inflight[1] = 0; +#endif + bytesleft = privreq->req.len - privreq->req.xfrd; + + /* If all of the bytes were sent (bytesleft == 0) and no NULL packet is + * needed (!txnullpkt), then we are finished with the transfer + */ + + if (bytesleft == 0 && !privep->txnullpkt) + { + /* The transfer is complete. Give the completed request back to + * the class driver. + */ + + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + khci_reqcomplete(privep, OK); + + /* Special case writes to endpoint zero. If there is no transfer in + * progress, then we need to configure to received the next SETUP packet. + */ + + if (USB_EPNO(privep->ep.eplog) == 0) + { + priv->ctrlstate = CTRLSTATE_WAITSETUP; + } + } +} + +/**************************************************************************** + * Name: khci_rqrestart + ****************************************************************************/ + +static void khci_rqrestart(int argc, uint32_t arg1, ...) +{ + struct khci_usbdev_s *priv; + struct khci_ep_s *privep; + struct khci_req_s *privreq; + uint16_t epstalled; + uint16_t mask; + int epno; + + /* Recover the pointer to the driver structure */ + + priv = (struct khci_usbdev_s *)((uintptr_t)arg1); + DEBUGASSERT(priv != NULL); + + /* Sample and clear the set of endpoints that have recovered from a stall */ + + epstalled = priv->epstalled; + priv->epstalled = 0; + + /* Loop, checking each bit in the epstalled bit set */ + + for (epno = 0; epstalled && epno < KHCI_NENDPOINTS; epno++) + { + /* Has this encpoint recovered from a stall? */ + + mask = (1 << epno); + if ((epstalled & mask) != 0) + { + /* Yes, this endpoint needs to be restarteed */ + + epstalled &= ~mask; + privep = &priv->eplist[epno]; + + /* Reset some endpoint state variables */ + + privep->stalled = false; + privep->txnullpkt = false; + + /* Check the request at the head of the endpoint's pending request queue */ + + privreq = khci_rqhead(&privep->pend); + if (privreq) + { + /* Restart transmission after we have recovered from a stall */ + + privreq->req.xfrd = 0; + privreq->inflight[0] = 0; +#ifndef CONFIG_USBDEV_NOWRITEAHEAD + privreq->inflight[1] = 0; +#endif + (void)khci_wrrequest(priv, privep); + } + } + } +} + +/**************************************************************************** + * Name: khci_delayedrestart + ****************************************************************************/ + +static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno) +{ + /* Add endpoint to the set of endpoints that need to be restarted */ + + priv->epstalled |= (1 << epno); + + /* And start (or re-start) the watchdog timer */ + + wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1, (uint32_t)priv); +} + +/**************************************************************************** + * Name: khci_rqstop + ****************************************************************************/ + +static void khci_rqstop(struct khci_ep_s *privep) +{ + struct khci_req_s *privreq; + + /* Move all of the active requests back to the pending request queue */ + + while ((privreq = khci_remlast(&privep->active))) + { + /* Move the request back to the head of the pending list */ + + khci_addfirst(&privep->pend, privreq); + } +} + +/**************************************************************************** + * Name: khci_wrstart + ****************************************************************************/ + +static int khci_wrstart(struct khci_usbdev_s *priv, + struct khci_ep_s *privep) +{ + volatile struct usbotg_bdtentry_s *bdt; + struct khci_req_s *privreq; + uint8_t *buf; + uint8_t epno; + int nbytes; + int bytesleft; + int xfrd; + int index; + + /* We get here when either (1) an IN endpoint completion interrupt occurs, + * or (2) a new write request is reqeived from the class. + */ + + /* Get the endpoint number that we are servicing */ + + epno = USB_EPNO(privep->ep.eplog); + + /* Decide which BDT to use. bdtin points to the "current" BDT. That is, + * the one that either (1) available for next transfer, or (2) the one + * that is currently busy with the current transfer. If the current + * BDT is busy, we have the option of setting up the other BDT in advance + * in order to improve data transfer performance. + */ + + bdt = privep->bdtin; + index = 0; + + if (bdt->status || bdt->addr) + { +#ifdef CONFIG_USBDEV_NOWRITEAHEAD + /* The current BDT is not available and write ahead is disabled. There + * is nothing we can do now. Return -EBUSY to indicate this condition. + */ + + return -EBUSY; +#else + /* The current BDT is not available, check the other BDT */ + + volatile struct usbotg_bdtentry_s *otherbdt; + otherbdt = &g_bdt[EP(epno, EP_DIR_IN, EP_PP_EVEN)]; + if (otherbdt == bdt) + { + otherbdt++; + } + + /* Is it available? */ + + if (otherbdt->status || otherbdt->addr) + { + /* No, neither are available. We cannot perform the transfer now. + * Return -EBUSY to indicate this condition. + */ + + return -EBUSY; + } + + /* Yes... use the other BDT */ + + bdt = otherbdt; + index = 1; +#endif + } + + /* A BDT is available. Which request should we be operating on? The last + * incomplete, active request would be at the tail of the active list. + */ + + privreq = khci_rqtail(&privep->active); + + /* This request would be NULL if there is no incomplete, active request. */ + + if (privreq) + { + /* Get the number of bytes left to be transferred in the request */ + + xfrd = privreq->req.xfrd; + bytesleft = privreq->req.len - xfrd; + + /* Even if the request is incomplete, transfer of all the requested + * bytes may already been started. NOTE: inflight[1] should be zero + * because we know that there is a BDT available. + */ + +#ifndef CONFIG_USBDEV_NOWRITEAHEAD + DEBUGASSERT(privreq->inflight[1] == 0); +#endif + /* Has the transfer been initiated for all of the bytes? */ + + if (bytesleft > privreq->inflight[0]) + { + /* No.. we have more work to do with this request */ + + xfrd += privreq->inflight[0]; + bytesleft -= privreq->inflight[0]; + } + + /* Do we need to send a null packet after this packet? */ + + else if (privep->txnullpkt) + { + /* Yes... set up for the NULL packet transfer */ + + xfrd = privreq->req.len; + bytesleft = 0; + } + else + { + /* No.. We are finished with this request. We need to get the + * next request from the head of the pending request list. + */ + + privreq = NULL; + } + } + + /* If privreq is NULL here then either (1) there is no active request, or + * (2) the (only) active request is fully queued. In either case, we need + * to get the next request from the head of the pending request list. + */ + + if (!privreq) + { + /* Remove the next request from the head of the pending request list */ + + privreq = khci_remfirst(&privep->pend); + if (!privreq) + { + /* The pending request list is empty. There are no queued TX + * requests to be sent. + */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINQEMPTY), epno); + + /* Return -ENODATA to indicate that there are no further requests + * to be processed. + */ + + return -ENODATA; + } + + /* Add this request to the tail of the active request list */ + + khci_addlast(&privep->active, privreq); + + /* Set up the first transfer for this request */ + + xfrd = 0; + bytesleft = privreq->req.len; + } + + ullvdbg("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n", + epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt); + + /* Get the number of bytes left to be sent in the packet */ + + nbytes = bytesleft; + if (nbytes > 0 || privep->txnullpkt) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + privep->txnullpkt = 0; + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + privep->txnullpkt = 1; + } + } + } + + /* Send the packet (might be a null packet with nbytes == 0) */ + + buf = privreq->req.buf + xfrd; + + /* Setup the writes to the endpoints */ + + khci_epwrite(privep, bdt, buf, nbytes); + + /* Special case endpoint 0 state information. The write request is in + * progress. + */ + + if (epno == 0) + { + priv->ctrlstate = CTRLSTATE_WRREQUEST; + } + + /* Update for the next data IN interrupt */ + + privreq->inflight[index] = nbytes; + return OK; +} + +/**************************************************************************** + * Name: khci_wrrequest + ****************************************************************************/ + +static int khci_wrrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep) +{ + int ret; + + /* Always try to start two transfers in order to take advantage of the + * KHCI's ping pong buffering. + */ + + ret = khci_wrstart(priv, privep); +#ifndef CONFIG_USBDEV_NOWRITEAHEAD + if (ret == OK) + { + /* Note: We need to return the error condition only if nothing was + * queued + */ + + (void)khci_wrstart(priv, privep); + } +#else + UNUSED(ret); +#endif + + /* We return OK to indicate that a write request is still in progress */ + + return khci_rqhead(&privep->active) == NULL ? -ENODATA : OK; +} + +/**************************************************************************** + * Name: khci_rdcomplete + ****************************************************************************/ + +static int khci_rdcomplete(struct khci_usbdev_s *priv, + struct khci_ep_s *privep) +{ + volatile struct usbotg_bdtentry_s *bdtout; + struct khci_req_s *privreq; + int epno; + + /* Check the request at the head of the endpoint's active request queue */ + + privreq = khci_rqhead(&privep->active); + if (!privreq) + { + /* There is no active packet waiting to receive any data. Then why are + * we here? + */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY), + USB_EPNO(privep->ep.eplog)); + return -EINVAL; + } + + /* bdtout should point to the BDT that just completed */ + + bdtout = privep->bdtout; + epno = USB_EPNO(privep->ep.eplog); + + ullvdbg("EP%d: len=%d xfrd=%d\n", + epno, privreq->req.len, privreq->req.xfrd); + bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdtout, bdtout->status, bdtout->addr); + + /* We should own the BDT that just completed */ + + DEBUGASSERT((bdtout->status & USB_BDT_UOWN) == USB_BDT_COWN); + + /* Get the length of the data received from the BDT. */ + + privreq->req.xfrd = (bdtout->status & USB_BDT_BYTECOUNT_MASK) >> USB_BDT_BYTECOUNT_SHIFT; + + /* Complete the transfer and return the request to the class driver. */ + + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + khci_reqcomplete(privep, OK); + + /* Nullify the BDT entry that just completed. Why? So that we can tell later + * that the BDT has been processed. No, it is not sufficient to look at the + * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may not + * yet have been processed. + */ + + bdtout->status = 0; + bdtout->addr = 0; + + /* Toggle bdtout to the other BDT. Is the current bdtout the EVEN bdt? */ + + privep->bdtout = &g_bdt[EP_OUT_EVEN(epno)]; + if (bdtout == privep->bdtout) + { + /* Yes.. Then the other BDT is the ODD BDT */ + + privep->bdtout++; + } + + /* Set up the next read operation */ + + return khci_rdrequest(priv, privep); +} + +/**************************************************************************** + * Name: khci_ep0rdsetup + ****************************************************************************/ + +static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest, + int readlen) +{ + volatile struct usbotg_bdtentry_s *bdtout; + volatile struct usbotg_bdtentry_s *otherbdt; + struct khci_ep_s *privep; + uint32_t status; + + /* bdtout refers to the next ping-pong BDT to use. */ + + privep = &priv->eplist[EP0]; + bdtout = privep->bdtout; + + /* Get the other BDT. Check if the current BDT the EVEN BDT? */ + + otherbdt = &g_bdt[EP_OUT_EVEN(EP0)]; + if (bdtout == otherbdt) + { + /* Yes.. then the other BDT is the ODD BDT. */ + + otherbdt++; + } + + /* If there is no RX transfer in progress, then the other BDT is setup + * to receive the next setup packet. There is a race condition here! + * Stop any setup packet. + */ + + if (!priv->rxbusy) + { + /* Nullify all BDT OUT entries. Why? So that we can tell later + * that the BDT available. No, it is not sufficient to look at the + * UOWN bit. If UOWN==0, then the transfer has been completed BUT + * it may not yet have been processed. But a completely NULLified + * BDT is a sure indication + */ + + bdtout->status = 0; + bdtout->addr = 0; + otherbdt->status = 0; + otherbdt->addr = 0; + + /* Reset the other BDT to zero... this will cause any attempted use + * of the other BDT to be NAKed. Set the first DATA0/1 value to 1. + */ + + privep->rxdata1 = 1; + } + + /* Otherwise, there are RX transfers in progress. bdtout may be + * unavailable now. In that case, we are free to setup the other BDT + * in order to improve performance. NOTE: That we check if the + * entire BDT has been NULLified. That is the only sure indication + * that the BDT is available (see above). + */ + + if (bdtout->status || bdtout->addr) + { +#ifdef CONFIG_USBDEV_NOREADAHEAD + /* We will not try to read ahead */ + + return -EBUSY; +#else + /* bdtout is not available. Is the other BDT available? */ + + if (otherbdt->status || otherbdt->addr) + { + /* Neither are available... we cannot accept the request now */ + + return -EBUSY; + } + + /* Use the other BDT */ + + bdtout = otherbdt; +#endif + } + + usbtrace(TRACE_READ(EP0), readlen); + + /* Get the correct data toggle (as well as other BDT bits) */ + + if (privep->rxdata1) + { + status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS); + privep->rxdata1 = 0; + } + else + { + status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS); + privep->rxdata1 = 1; + } + + /* Set the data pointer, data length, and enable the endpoint */ + + bdtout->addr = (uint8_t *)dest; + status |= ((uint32_t)readlen << USB_BDT_BYTECOUNT_SHIFT); + + /* Then give the BDT to the USB */ + + bdtdbg("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr); + bdtout->status = status; + + priv->ctrlstate = CTRLSTATE_RDREQUEST; + priv->rxbusy = 1; + return OK; +} + +/**************************************************************************** + * Name: khci_rdsetup + ****************************************************************************/ + +static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen) +{ + volatile struct usbotg_bdtentry_s *bdtout; + uint32_t status; + int epno; + + /* Select a BDT. Check both the even and the ODD BDT and use the first one + * that we own. + */ + + epno = USB_EPNO(privep->ep.eplog); + + /* bdtout refers to the next ping-pong BDT to use. However, bdtout may be + * unavailable now. But, in that case, we are free to setup the other BDT + * in order to improve performance. + * + * Note that we NULLify the BDT OUT entries. This is so that we can tell + * that the BDT readlly available. No, it is not sufficient to look at the + * UOWN bit. If UOWN==0, then the transfer has been completed BUT it may + * not yet have been processed. But a completely NULLified BDT is a sure + * indication + */ + + bdtout = privep->bdtout; + if (bdtout->status || bdtout->addr) + { +#ifdef CONFIG_USBDEV_NOREADAHEAD + /* We will not try to read-ahead */ + + return -EBUSY; +#else + volatile struct usbotg_bdtentry_s *otherbdt; + + /* Is the current BDT the EVEN BDT? */ + + otherbdt = &g_bdt[EP_OUT_EVEN(epno)]; + if (bdtout == otherbdt) + { + /* Yes.. select the ODD BDT */ + + otherbdt++; + } + + /* Is the other BDT available? */ + + if (otherbdt->status || otherbdt->addr) + { + /* Neither are available... we cannot accept the request now */ + + return -EBUSY; + } + + /* Use the other BDT */ + + bdtout = otherbdt; +#endif + } + + usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), readlen); + + /* Clear status bits (making sure that UOWN is cleared before doing anything + * else). + */ + + bdtout->status = 0; + + /* Set the data pointer, data length, and enable the endpoint */ + + bdtout->addr = (uint8_t *)dest; + + /* Get the correct data toggle. */ + + if (privep->rxdata1) + { + status = (USB_BDT_UOWN | USB_BDT_DATA1 | USB_BDT_DTS); + privep->rxdata1 = 0; + } + else + { + status = (USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS); + privep->rxdata1 = 1; + } + + /* Set the data length (preserving the data toggle). */ + + status |= ((uint32_t)readlen << USB_BDT_BYTECOUNT_SHIFT); + + /* Then give the BDT to the USB */ + + bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdtout, status, bdtout->addr); + + bdtout->status = status; + return OK; +} + +/**************************************************************************** + * Name: khci_rdrequest + ****************************************************************************/ + +static int khci_rdrequest(struct khci_usbdev_s *priv, + struct khci_ep_s *privep) +{ + struct khci_req_s *privreq; + int readlen; + int ret; + + /* Check the request at the head of the endpoint request queue */ + + privreq = khci_rqhead(&privep->pend); + if (!privreq) + { + /* There is no packet to receive any data. */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTQEMPTY), + USB_EPNO(privep->ep.eplog)); + + /* Special case reads from to endpoint zero. If there is no transfer in + * progress, then we need to configure to received the next SETUP packet. + */ + + if (USB_EPNO(privep->ep.eplog) == 0 && + priv->ctrlstate == CTRLSTATE_RDREQUEST) + { + priv->ctrlstate = CTRLSTATE_WAITSETUP; + priv->rxbusy = 0; + } + + return OK; + } + + ullvdbg("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len); + + /* Ignore any attempt to receive a zero length packet */ + + if (privreq->req.len == 0) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EPOUTNULLPACKET), 0); + khci_reqcomplete(privep, OK); + return OK; + } + + /* Limit the size of the transfer to either the buffer size or the max + * packet size of the endpoint. + */ + + readlen = MIN(privreq->req.len, privep->ep.maxpacket); + + /* Handle EP0 in a few special ways */ + + if (USB_EPNO(privep->ep.eplog) == EP0) + { + ret = khci_ep0rdsetup(priv, privreq->req.buf, readlen); + } + else + { + ret = khci_rdsetup(privep, privreq->req.buf, readlen); + } + + /* If the read request was successfully setup, then move the request from + * the head of the pending request queue to the tail of the active request + * queue. + */ + + if (ret == OK) + { + privreq = khci_remfirst(&privep->pend); + DEBUGASSERT(privreq != NULL); + khci_addlast(&privep->active, privreq); + } + + return ret; +} + +/**************************************************************************** + * Name: khci_cancelrequests + ****************************************************************************/ + +static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result) +{ + struct khci_req_s *privreq; + + while ((privreq = khci_remfirst(&privep->active))) + { + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + khci_reqreturn(privep, privreq, result); + } + + while ((privreq = khci_remfirst(&privep->pend))) + { + usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); + khci_reqreturn(privep, privreq, result); + } +} + +/**************************************************************************** + * Interrupt Level Processing + ****************************************************************************/ +/**************************************************************************** + * Name: khci_dispatchrequest + ****************************************************************************/ + +static void khci_dispatchrequest(struct khci_usbdev_s *priv) +{ + int ret; + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DISPATCH), 0); + if (priv && priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, NULL, 0); + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DISPATCHSTALL), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } +} + +/**************************************************************************** + * Name: khci_ep0stall + ****************************************************************************/ + +static void khci_ep0stall(struct khci_usbdev_s *priv) +{ + uint32_t regval; + + /* Check if EP0 is stalled */ + + regval = khci_getreg(KINETIS_USB0_ENDPT0); + if ((regval & USB_ENDPT_EPSTALL) != 0) + { + /* If so, clear the EP0 stall status */ + + regval &= ~USB_ENDPT_EPSTALL; + khci_putreg(regval, KINETIS_USB0_ENDPT0); + } +} + +/**************************************************************************** + * Name: khci_eptransfer + ****************************************************************************/ + +static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno, + uint16_t ustat) +{ + struct khci_ep_s *privep; + int ret; + + /* Decode and service non control endpoints interrupt */ + + privep = &priv->eplist[epno]; + + /* Check if the last transaction was an EP0 OUT transaction */ + + if ((ustat & USB_STAT_TX) == USB_STAT_TX_OUT) + { + /* OUT: host-to-device */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPOUTDONE), ustat); + + /* Handle read requests. Call khci_rdcomplete() to complete the OUT + * transfer and setup the next out transfer. + */ + + ret = khci_rdcomplete(priv, privep); +#ifdef CONFIG_USBDEV_NOREADAHEAD + if (ret == OK) + { + /* If that succeeds, then try to set up another OUT transfer. */ + + (void)khci_rdrequest(priv, privep); + } +#else + UNUSED(ret); +#endif + } + else + { + /* IN: device-to-host */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPINDONE), ustat); + + /* An outgoing IN packet has completed. Update the number of bytes transferred + * and check for completion of the transfer. + */ + + khci_wrcomplete(priv, privep); + + /* Handle additional queued write requests */ + + (void)khci_wrrequest(priv, privep); + } +} + +/**************************************************************************** + * Name: khci_ep0nextsetup + * + * Description: + * This function is called (1) after sucessful completion of an EP0 Setup + * command, or (2) after receipt of the OUT complete event (for simple + * transfers). It simply sets up the single BDT to accept the next + * SETUP commend. + * + ****************************************************************************/ + +static void khci_ep0nextsetup(struct khci_usbdev_s *priv) +{ + volatile struct usbotg_bdtentry_s *bdt = priv->eplist[EP0].bdtout; + uint32_t bytecount; + + /* This operation should be performed no more than once per OUT transaction. + * priv->ep0done is set to zero at the beginning of processing of each EP0 + * transfer. It is set the first time that this function runs after the EP0 + * transfer. + */ + + if (!priv->ep0done) + { + bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); + bdt->addr = (uint8_t *)&priv->ctrl; + bdt->status = (USB_BDT_UOWN | bytecount); + priv->ep0done = 1; + } +} + +/**************************************************************************** + * Name: khci_ep0rdcomplete + * + * Description: + * This function is called after a sequence of read sequence. In this + * context, only one BDT is used. Both BDTs must be prepared to receive + * SETUP packets. + * + ****************************************************************************/ + +static void khci_ep0rdcomplete(struct khci_usbdev_s *priv) +{ + volatile struct usbotg_bdtentry_s *bdt; + struct khci_ep_s *ep0; + uint32_t physaddr; + uint32_t bytecount; + + /* This operation should be performed no more than once per OUT transaction. + * priv->ep0done is set to zero at the beginning of processing of each EP0 + * transfer. It is set the first time that this function runs after the EP0 + * transfer. + */ + + if (!priv->ep0done) + { + bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); + physaddr = &priv->ctrl; + + bdt = &g_bdt[EP0_OUT_EVEN]; + bdt->addr = (uint8_t *)physaddr; + bdt->status = (USB_BDT_UOWN | bytecount); + + bdt = &g_bdt[EP0_OUT_ODD]; + bdt->addr = (uint8_t *)physaddr; + bdt->status = (USB_BDT_UOWN | bytecount); + + priv->ep0done = 1; + + /* Data toggling is not used on SETUP transfers. And IN transfer + * resulting from a SETUP command should begin with DATA1. + */ + + ep0 = &priv->eplist[EP0]; + ep0->rxdata1 = 0; + ep0->txdata1 = 1; + } +} + +/**************************************************************************** + * Name: khci_ep0setup + ****************************************************************************/ + +static void khci_ep0setup(struct khci_usbdev_s *priv) +{ + volatile struct usbotg_bdtentry_s *bdt; + struct khci_ep_s *ep0; + struct khci_ep_s *privep; + union wb_u value; + union wb_u index; + union wb_u len; + union wb_u response; + uint32_t regval; + bool dispatched = false; + uint8_t epno; + int nbytes = 0; /* Assume zero-length packet */ + int ret; + + /* Cancel any pending requests. */ + + ep0 = &priv->eplist[EP0]; + khci_cancelrequests(ep0, -EPROTO); + + /* Assume NOT stalled; no TX in progress; no RX overrun. Data 0/1 toggling + * is not used on SETUP packets, but any following EP0 IN transfer should + * beginning with DATA1. + */ + + ep0->stalled = false; + ep0->rxdata1 = 0; + ep0->txdata1 = 1; + + /* Initialize for the SETUP */ + + priv->ctrlstate = CTRLSTATE_WAITSETUP; + + /* And extract the little-endian 16-bit values to host order */ + + value.w = GETUINT16(priv->ctrl.value); + index.w = GETUINT16(priv->ctrl.index); + len.w = GETUINT16(priv->ctrl.len); + + ullvdbg("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n", + priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w); + + /* Dispatch any non-standard requests */ + + if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_NOSTDREQ), priv->ctrl.type); + + /* Let the class implementation handle all non-standar requests */ + + khci_dispatchrequest(priv); + dispatched = true; + goto resume_packet_processing; /* Sorry about the goto */ + } + + /* Handle standard request. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver + */ + + switch (priv->ctrl.req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSTATUS), priv->ctrl.type); + if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || + index.b[MSB] != 0 || value.w != 0) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + else + { + switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + epno = USB_EPNO(index.b[LSB]); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EPGETSTATUS), epno); + if (epno >= KHCI_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPGETSTATUS), epno); + priv->ctrlstate = CTRLSTATE_STALL; + } + else + { + privep = &priv->eplist[epno]; + response.w = 0; /* Not stalled */ + nbytes = 2; /* Response size: 2 bytes */ + + if (USB_ISEPIN(index.b[LSB])) + { + /* IN endpoint */ + + bdt = privep->bdtin; + } + else + { + /* OUT endpoint */ + + bdt = privep->bdtout; + } + + /* BSTALL set if stalled */ + + if ((bdt->status & USB_BDT_BSTALL) != 0) + { + response.b[LSB] = 1; /* Stalled, set bit 0 */ + } + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (index.w == 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup=YES; selfpowered=? */ + + response.w = 0; + response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) | + (priv->rwakeup << USB_FEATURE_REMOTEWAKEUP); + nbytes = 2; /* Response size: 2 bytes */ + } + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADDEVGETSTATUS), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IFGETSTATUS), 0); + response.w = 0; + nbytes = 2; /* Response size: 2 bytes */ + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSTATUS), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_CLEARFEATURE), priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + { + /* Disable B device from performing HNP */ + +#ifdef CONFIG_USBOTG + if (value.w == USBOTG_FEATURE_B_HNP_ENABLE) + { + /* Disable HNP */ +#warning Missing Logic + } + + /* Disable A device HNP support */ + + else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT) + { + /* Disable HNP support */ +#warning Missing Logic + } + + /* Disable alternate HNP support */ + + else if (value.w == USBOTG_FEATURE_A_ALT_HNP_SUPPORT) + { + /* Disable alternate HNP */ +#warning Missing Logic + } + else +#endif + /* Disable remote wakeup */ + + if (value.w == USB_FEATURE_REMOTEWAKEUP) + { + priv->rwakeup = 0; + } + else + { + /* Let the class implementation handle all other device features */ + + khci_dispatchrequest(priv); + dispatched = true; + } + } + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_ENDPOINT) + { + epno = USB_EPNO(index.b[LSB]); + if (epno > 0 && epno < KHCI_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = false; + ret = khci_epstall(&privep->ep, true); + UNUSED(ret); + } + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADCLEARFEATURE), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } + else + { + /* Let the class implementation handle all other recipients. */ + + khci_dispatchrequest(priv); + dispatched = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETFEATURE), priv->ctrl.type); + + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + { + /* Enable B device to perform HNP */ + +#ifdef CONFIG_USBOTG + if (value.w == USBOTG_FEATURE_B_HNP_ENABLE) + { + /* Enable HNP */ +#warning "Missing logic" + } + + /* Enable A device HNP supports */ + + else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT) + { + /* Enable HNP support */ +#warning "Missing logic" + } + + /* Another port on the A device supports HNP */ + + else if (value.w == USBOTG_FEATURE_A_ALT_HNP_SUPPORT) + { + /* Enable alternate HNP */ +#warning "Missing logic" + } + else +#endif + + if (value.w == USB_FEATURE_REMOTEWAKEUP) + { + priv->rwakeup = 0; + } + else if (value.w == USB_FEATURE_TESTMODE) + { + /* Special case recipient=device test mode */ + + ullvdbg("test mode: %d\n", index.w); + } + else + { + /* Let the class implementation handle all other device features */ + + khci_dispatchrequest(priv); + dispatched = true; + } + } + else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_ENDPOINT) + { + /* Handler recipient=endpoint */ + + epno = USB_EPNO(index.b[LSB]); + if (epno < KHCI_NENDPOINTS && index.b[MSB] == 0 && + value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) + { + privep = &priv->eplist[epno]; + privep->halted = true; + ret = khci_epstall(&privep->ep, false); + UNUSED(ret); + } + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETFEATURE), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } + else + { + /* The class driver handles all recipients except recipient=endpoint */ + + khci_dispatchrequest(priv); + dispatched = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPSETADDRESS), value.w); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || + index.w != 0 || len.w != 0 || value.w > 127) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETADDRESS), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + else + { + /* Note that setting of the device address will be deferred. A zero-length + * packet will be sent and the device address will be set when the zero- + * length packet transfer completes. + */ + + priv->devstate = DEVSTATE_ADDRPENDING; + } + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETDESC), priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + { + /* The request seems valid... let the class implementation handle it */ + + khci_dispatchrequest(priv); + dispatched = true; + } + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETSETDESC), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETCONFIG), priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + value.w == 0 && index.w == 0 && len.w == 1) + { + /* The request seems valid... let the class implementation handle it */ + + khci_dispatchrequest(priv); + dispatched = true; + } + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADGETCONFIG), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SETCONFIG), priv->ctrl.type); + if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + index.w == 0 && len.w == 0) + { + /* The request seems valid... let the class implementation handle it */ + + khci_dispatchrequest(priv); + dispatched = true; + } + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADSETCONFIG), 0); + priv->ctrlstate = CTRLSTATE_STALL; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + /* Let the class implementation handle the request */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_GETSETIF), priv->ctrl.type); + khci_dispatchrequest(priv); + dispatched = true; + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); + priv->ctrlstate = CTRLSTATE_STALL; + } + break; + } + + /* PKTDIS bit is set when a Setup Transaction is received. Clear to resume + * packet processing. + */ + +resume_packet_processing: + regval = khci_getreg(KINETIS_USB0_CTL); + regval &= ~USB_CTL_TXSUSPENDTOKENBUSY; + khci_putreg(regval, KINETIS_USB0_CTL); + + /* At this point, the request has been handled and there are three possible + * outcomes: + * + * 1. The setup request was successfully handled above and a response packet + * must be sent (may be a zero length packet). + * 2. The request was successfully handled by the class implementation. In + * case, the EP0 IN response has already been queued and the local variable + * 'dispatched' will be set to true and ctrlstate != CTRLSTATE_STALL; + * 3. An error was detected in either the above logic or by the class implementation + * logic. In either case, priv->state will be set CTRLSTATE_STALL + * to indicate this case. + * + * NOTE: Non-standard requests are a special case. They are handled by the + * class implementation and this function returned early above, skipping this + * logic altogether. + */ + + if (!dispatched && (priv->ctrlstate != CTRLSTATE_STALL)) + { + /* The SETUP command was not dispatched to the class driver and the SETUP + * command did not cause a stall. We will respond. First, restrict the + * data length to the length requested in the setup packet + */ + + if (nbytes > len.w) + { + nbytes = len.w; + } + + /* Send the EP0 SETUP response (might be a zero-length packet) */ + + khci_epwrite(ep0, ep0->bdtin, response.b, nbytes); + priv->ctrlstate = CTRLSTATE_WAITSETUP; + } + + /* Did we stall? This might have occurred from the above logic OR the stall + * condition may have been set less obviously in khci_dispatchrequest(). + * In either case, we handle the stall condition the same. + * + * However, bad things happen if we try to stall a SETUP packet. So lets + * not. If we wait a bit, things will recover. Hmmm.. If we completed + * the data phase (perhaps by sending a NULL packet), then I think we + * could stall the endpoint and perhaps speed things up a bit???. + */ + + /* Set up the BDT to accept the next setup commend. */ + + khci_ep0nextsetup(priv); + priv->ctrlstate = CTRLSTATE_WAITSETUP; +} + +/**************************************************************************** + * Name: khci_ep0incomplete + ****************************************************************************/ + +static void khci_ep0incomplete(struct khci_usbdev_s *priv) +{ + struct khci_ep_s *ep0 = &priv->eplist[EP0]; + volatile struct usbotg_bdtentry_s *bdtlast; + int ret; + + /* Get the last BDT and make sure that we own it. */ + + bdtlast = ep0->bdtin; + + /* Make sure that we own the last BDT. */ + + bdtlast->status = 0; + bdtlast->addr = 0; + + /* Are we processing the completion of one packet of an outgoing request + * from the class driver? + */ + + if (priv->ctrlstate == CTRLSTATE_WRREQUEST) + { + /* An outgoing EP0 transfer has completed. Update the byte count and + * check for the completion of the transfer. + * + * NOTE: khci_wrcomplete() will toggle bdtin to the other buffer so + * we do not need to that for this case. + */ + + khci_wrcomplete(priv, &priv->eplist[EP0]); + + /* Handle the next queue IN transfer. If there are no further queued + * IN transfers, khci_wrrequest will return -ENODATA and that is the + * only expected error return value in this context. + */ + + ret = khci_wrrequest(priv, &priv->eplist[EP0]); + if (ret < 0) + { + DEBUGASSERT(ret == -ENODATA); + + /* If there is nothing to be sent, then we need to configure to + * receive the next SETUP packet. + */ + + priv->ctrlstate = CTRLSTATE_WAITSETUP; + } + } + + /* No.. Are we processing the completion of a status response? */ + + else if (priv->ctrlstate == CTRLSTATE_WAITSETUP) + { + /* Get the next IN BDT */ + + if (bdtlast == &g_bdt[EP0_IN_EVEN]) + { + ep0->bdtin = &g_bdt[EP0_IN_ODD]; + } + else + { + DEBUGASSERT(bdtlast == &g_bdt[EP0_IN_ODD]); + ep0->bdtin = &g_bdt[EP0_IN_EVEN]; + } + + /* Look at the saved SETUP command. Was it a SET ADDRESS request? + * If so, then now is the time to set the address. + */ + + if (priv->devstate == DEVSTATE_ADDRPENDING) + { + uint16_t addr = GETUINT16(priv->ctrl.value); + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0ADDRESSSET), addr); + + /* This should be the equivalent state */ + + DEBUGASSERT(priv->ctrl.req == USB_REQ_SETADDRESS && + (priv->ctrl.type & REQRECIPIENT_MASK) == + (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)); + + /* Set (or clear) the address */ + + khci_putreg(addr, KINETIS_USB0_ADDR); + if (addr > 0) + { + priv->devstate = DEVSTATE_ADDRESS; + } + else + { + priv->devstate = DEVSTATE_DEFAULT; + } + } + } + + /* No other state is expected in this context */ + + else + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate); + priv->ctrlstate = CTRLSTATE_STALL; + } +} + +/**************************************************************************** + * Name: khci_ep0outcomplete + ****************************************************************************/ + +static void khci_ep0outcomplete(struct khci_usbdev_s *priv) +{ + struct khci_ep_s *ep0 = &priv->eplist[EP0]; + + switch (priv->ctrlstate) + { + /* Read request in progress */ + + case CTRLSTATE_RDREQUEST: + + /* Process the next read request for EP0 */ + + khci_rdcomplete(priv, ep0); + + /* Was this the end of the OUT transfer? */ + + if (priv->ctrlstate == CTRLSTATE_WAITSETUP) + { + /* Prepare EP0 OUT for the next SETUP transaction. */ + + khci_ep0rdcomplete(priv); + } + break; + + /* No transfer in progress, waiting for SETUP */ + + case CTRLSTATE_WAITSETUP: + { + /* In this case the last OUT transaction must have been a status + * stage of a CTRLSTATE_WRREQUEST: Prepare EP0 OUT for the next SETUP + * transaction. + */ + + khci_ep0nextsetup(priv); + } + break; + + /* Unexpected state OR host aborted the OUT transfer before it completed, + * STALL the endpoint in either case + */ + + default: + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDSTATE), priv->ctrlstate); + priv->ctrlstate = CTRLSTATE_STALL; + } + break; + } +} + +/**************************************************************************** + * Name: khci_ep0transfer + ****************************************************************************/ + +static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) +{ + volatile struct usbotg_bdtentry_s *bdt; + + /* The following information is available in the status register : + * + * ENDPT - The 4 bit endpoint number that cause the interrupt. + * DIR - The direction of the endpoint. + * PPBI - The ping-pong buffer used in the transaction. + */ + + priv->ep0done = 0; + + /* Check if the last transaction was an EP0 OUT transaction */ + + if ((ustat & USB_STAT_TX) == USB_STAT_TX_OUT) + { + int index; + + /* It was an EP0 OUT transaction. Get the index to the BDT. */ + + index = ((ustat & USB_STAT_ODD) == 0 ? EP0_OUT_EVEN : EP0_OUT_ODD); + bdt = &g_bdt[index]; + priv->eplist[0].bdtout = bdt; + + bdtdbg("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr); + + /* Check the current EP0 OUT buffer contains a SETUP packet */ + + if (((bdt->status & USB_BDT_PID_MASK) >> USB_BDT_PID_SHIFT) == USB_PID_SETUP_TOKEN) + { + /* Check if the SETUP transaction data went into the priv->ctrl + * buffer. If not, then we will need to copy it. + */ + + if (bdt->addr != (uint8_t *)&priv->ctrl) + { + void *src = (void *)bdt->addr; + void *dest = &priv->ctrl; + + memcpy(dest, src, USB_SIZEOF_CTRLREQ); + bdt->addr = (uint8_t *)&priv->ctrl; + } + + /* Handle the control OUT transfer */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0SETUPDONE), bdt->status); + khci_ep0setup(priv); + } + else + { + /* Handle the data OUT transfer */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0OUTDONE), ustat); + khci_ep0outcomplete(priv); + } + } + + /* No.. it was an EP0 IN transfer */ + + else /* if ((status & USB_STAT_TX) == USB_STAT_TX_IN) */ + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_EP0INDONE), ustat); + + /* Handle the IN transfer complete */ + + khci_ep0incomplete(priv); + } + + /* Check for a request to stall EP0 */ + + if (priv->ctrlstate == CTRLSTATE_STALL) + { + /* Stall EP0 */ + + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EP0SETUPSTALLED), priv->ctrlstate); + (void)khci_epstall(&priv->eplist[EP0].ep, false); + } +} + +/**************************************************************************** + * Name: khci_interrupt + ****************************************************************************/ + +static int khci_interrupt(int irq, void *context) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct khci_usbdev_s *priv = &g_usbdev; + uint16_t usbir; + uint16_t otgir; + uint32_t regval; + int i; + + /* Get the set of pending USB and OTG interrupts interrupts */ + + usbir = khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_INTEN); + otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & khci_getreg(KINETIS_USB0_OTGICR); +// ulldbg("Interrupt: ISTAT %04x\n", khci_getreg(KINETIS_USB0_ISTAT)); +// ulldbg("Interrupt: OTGISTAT %04x\n", khci_getreg(KINETIS_USB0_OTGISTAT)); +// ulldbg("Interrupt: ERRSTAT %04x\n", khci_getreg(KINETIS_USB0_ERRSTAT)); + usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir | otgir); + +#ifdef CONFIG_USBOTG + /* Session Request Protocol (SRP) Time Out Check */ + + /* if USB OTG SRP is ready */ +# warning "Missing logic" + { + /* Check if the 1 millisecond timer has expired */ + + if ((otgir & USBOTG_INT_T1MSEC) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_T1MSEC), otgir); + + /* Check for the USB OTG SRP timeout */ +# warning "Missing logic" + { + /* Handle OTG events of the SRP timeout has expired */ +# warning "Missing logic" + } + + /* Clear Interrupt 1 msec timer Flag */ + + khci_putreg(USBOTG_INT_T1MSEC, KINETIS_USB0_ISTAT); + } + } +#endif + + /* Handle events while we are in the attached state */ + + if (priv->devstate == DEVSTATE_ATTACHED) + { + /* Clear all USB interrupts */ + + khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT); + + /* Make sure that the USE reset and IDLE detect interrupts are enabled */ + + regval = khci_getreg(KINETIS_USB0_INTEN); + regval |= (USB_INT_USBRST | USB_INT_SLEEP); + khci_putreg(regval, KINETIS_USB0_INTEN); + + /* Now were are in the powered state */ + + priv->devstate = DEVSTATE_POWERED; + } + +#ifdef CONFIG_USBOTG + /* Check if the ID Pin Changed State */ + + if ((otgir & USBOTG_INT_ID) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_OTGID), otgir); + + /* Re-detect and re-initialize */ +#warning "Missing logic" + + khci_putreg(USBOTG_INT_ID, KINETIS_USB0_ISTAT); + } +#endif +#if 0 + /* Service the USB Activity Interrupt */ + + if ((otgir & USBOTG_INT_ACTV) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_WKUP), otgir); + + /* Wake-up from susepnd mode */ + + khci_putreg(USBOTG_INT_ACTV, KINETIS_USB0_ISTAT); + khci_resume(priv); + } + + /* It is pointless to continue servicing if the device is in suspend mode. */ +x + if ((khci_getreg(KINETIS_USB0_CTL) & USB_USBCTRL_SUSP) != 0) + { + /* Just clear the interrupt and return */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SUSPENDED), khci_getreg(KINETIS_USB0_CTL)); + goto interrupt_exit; + } +#endif + + /* Service USB Bus Reset Interrupt. When bus reset is received during + * suspend, ACTVIF will be set first, once the UCONbits.SUSPND is clear, + * then the URSTIF bit will be asserted. This is why URSTIF is checked + * after ACTVIF. The USB reset flag is masked when the USB state is in + * DEVSTATE_DETACHED or DEVSTATE_ATTACHED, and therefore cannot cause a + * USB reset event during these two states. + */ + + if ((usbir & USB_INT_USBRST) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_RESET), usbir); + + /* Reset interrupt received. Restore our initial state. NOTE: the + * hardware automatically resets the USB address, so we really just + * need reset any existing configuration/transfer states. + */ + khci_reset(priv); + priv->devstate = DEVSTATE_DEFAULT; + +#ifdef CONFIG_USBOTG + /* Disable and deactivate HNP */ +#warning Missing Logic +#endif + /* Acknowlege the reset interrupt */ + + khci_putreg(USB_INT_USBRST, KINETIS_USB0_ISTAT); + goto interrupt_exit; + } + + /* Service IDLE interrupts */ + + if ((usbir & USB_INT_SLEEP) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_IDLE), usbir); + +#ifdef CONFIG_USBOTG + /* If Suspended, Try to switch to Host */ +#warning "Missing logic" +#else + khci_suspend(priv); + +#endif + khci_putreg(USB_INT_SLEEP, KINETIS_USB0_ISTAT); + } + + /* Service SOF interrupts */ + +#ifdef CONFIG_USB_SOFINTS + if ((usbir & USB_INT_SOFTOK) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_SOF), 0); + + /* I am not sure why you would ever enable SOF interrupts */ + + khci_putreg(USB_INT_SOFTOK, KINETIS_USB0_ISTAT); + } +#endif + + /* Service stall interrupts */ + + if ((usbir & USB_INT_STALL) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_STALL), usbir); + + khci_ep0stall(priv); + + /* Clear the pending STALL interrupt */ + + khci_putreg(USB_INT_STALL, KINETIS_USB0_ISTAT); + } + + /* Service error interrupts */ + + if ((usbir & USB_INT_ERROR) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir); + ulldbg("Error: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT)); + + /* Clear all pending USB error interrupts */ + + khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT); + } + + /* There is no point in continuing if the host has not sent a bus reset. + * Once bus reset is received, the device transitions into the DEFAULT + * state and is ready for communication. + */ + +#if 0 + if (priv->devstate < DEVSTATE_DEFAULT) + { + /* Just clear the interrupt and return */ + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_WAITRESET), priv->devstate); + goto interrupt_exit; + } +#endif + + /* Service USB Transaction Complete Interrupt */ + + if ((usbir & USB_INT_TOKDNE) != 0) + { + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_TRNC), usbir); + + /* Drain the USAT FIFO entries. If the USB FIFO ever gets full, USB + * bandwidth utilization can be compromised, and the device won't be + * able to receive SETUP packets. + */ + + for (i = 0; i < 4; i++) + { + uint8_t epno; + + /* Check the pending interrupt register. Is token processing complete. */ + + if ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0) + { + regval = khci_getreg(KINETIS_USB0_STAT); + khci_putreg(USB_INT_TOKDNE, KINETIS_USB0_ISTAT); + + usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_TRNCS), regval); + + /* Handle the endpoint transfer complete event. */ + + epno = (regval & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT; + if (epno == 0) + { + khci_ep0transfer(priv, regval); + } + else + { + khci_eptransfer(priv, epno, regval); + } + } + else + { + /* USTAT FIFO must be empty. */ + + break; + } + } + } + + /* Clear the pending USB interrupt. Goto is used in the above to assure + * that all interrupt exists pass through this logic. + */ + +interrupt_exit: + //up_clrpend_irq(KINETIS_IRQ_USBOTG); + kinetis_clrpend(KINETIS_IRQ_USBOTG); + usbtrace(TRACE_INTEXIT(KHCI_TRACEINTID_INTERRUPT), usbir | otgir); + return OK; +} + +/**************************************************************************** + * Suspend/Resume Helpers + ****************************************************************************/ +/**************************************************************************** + * Name: khci_suspend + ****************************************************************************/ + +static void khci_suspend(struct khci_usbdev_s *priv) +{ + uint32_t regval; + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + + /* Enable the ACTV interrupt. + * + * NOTE: Do not clear UIRbits.ACTVIF here! Reason: ACTVIF is only + * generated once an IDLEIF has been generated. This is a 1:1 ratio + * interrupt generation. For every IDLEIF, there will be only one ACTVIF + * regardless of the number of subsequent bus transitions. If the ACTIF + * is cleared here, a problem could occur. The driver services IDLEIF + * first because ACTIVIE=0. If this routine clears the only ACTIVIF, + * then it can never get out of the suspend mode. + */ +#if 0 + regval = khci_getreg(KINETIS_USB0_OTGICR); + regval |= USBOTG_INT_ACTV; + khci_putreg(regval, KINETIS_USB0_OTGICR); + + /* Disable further IDLE interrupts. Once is enough. */ + + regval = khci_getreg(KINETIS_USB0_INTEN); + regval &= ~USB_INT_SLEEP; + khci_putreg(regval, KINETIS_USB0_INTEN); +#endif + + /* Invoke a callback into board-specific logic. The board-specific logic + * may enter into sleep or idle modes or switch to a slower clock, etc. + */ + + kinetis_usbsuspend((struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: khci_resume + ****************************************************************************/ + +static void khci_resume(struct khci_usbdev_s *priv) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + + /* Start RESUME signaling */ + + regval = khci_getreg(KINETIS_USB0_CTL); + regval |= USB_CTL_RESUME; + khci_putreg(regval, KINETIS_USB0_CTL); + + /* Keep the RESUME line set for 1-13 ms */ + + up_mdelay(10); + + regval &= ~USB_CTL_RESUME; + khci_putreg(regval, KINETIS_USB0_CTL); + + /* This function is called when the USB activity interrupt occurs. + * If using clock switching, this is the place to call out to + * logic to restore the original MCU core clock frequency. + */ + + kinetis_usbsuspend((struct usbdev_s *)priv, true); + + /* Disable further activity interrupts */ +#if 0 + regval = khci_getreg(KINETIS_USB0_OTGICR); + regval &= ~USBOTG_INT_ACTV; + khci_putreg(regval, KINETIS_USB0_OTGICR); +#endif + + /* The ACTVIF bit cannot be cleared immediately after the USB module wakes + * up from Suspend or while the USB module is suspended. A few clock cycles + * are required to synchronize the internal hardware state machine before + * the ACTIVIF bit can be cleared by firmware. Clearing the ACTVIF bit + * before the internal hardware is synchronized may not have an effect on + * the value of ACTVIF. Additionally, if the USB module uses the clock from + * the 96 MHz PLL source, then after clearing the SUSPND bit, the USB + * module may not be immediately operational while waiting for the 96 MHz + * PLL to lock. + */ + + khci_putreg(USB_INT_SLEEP, KINETIS_USB0_ISTAT); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Endpoint Helpers + ****************************************************************************/ +/**************************************************************************** + * Name: khci_epreserve + ****************************************************************************/ + +static inline struct khci_ep_s * +khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset) +{ + struct khci_ep_s *privep = NULL; + irqstate_t flags; + int epndx = 0; + + flags = enter_critical_section(); + epset &= priv->epavail; + if (epset) + { + /* Select the lowest bit in the set of matching, available endpoints + * (skipping EP0) + */ + + for (epndx = 1; epndx < KHCI_NENDPOINTS; epndx++) + { + uint8_t bit = KHCI_ENDP_BIT(epndx); + if ((epset & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail &= ~bit; + + /* And return the pointer to the standard endpoint structure */ + + privep = &priv->eplist[epndx]; + break; + } + } + } + + leave_critical_section(flags); + return privep; +} + +/**************************************************************************** + * Name: khci_epunreserve + ****************************************************************************/ + +static inline void +khci_epunreserve(struct khci_usbdev_s *priv, struct khci_ep_s *privep) +{ + irqstate_t flags = enter_critical_section(); + priv->epavail |= KHCI_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: khci_epreserved + ****************************************************************************/ + +static inline bool +khci_epreserved(struct khci_usbdev_s *priv, int epno) +{ + return ((priv->epavail & KHCI_ENDP_BIT(epno)) == 0); +} + +/**************************************************************************** + * Name: khci_ep0configure + ****************************************************************************/ + +static void khci_ep0configure(struct khci_usbdev_s *priv) +{ + volatile struct usbotg_bdtentry_s *bdt; + struct khci_ep_s *ep0; + uint32_t bytecount; + + /* Enable the EP0 endpoint */ + + khci_putreg(KHCI_EP_CONTROL, KINETIS_USB0_ENDPT0); + + /* Configure the OUT BDTs. We assume that the ping-poing buffer index has + * just been reset and we expect to receive on the EVEN BDT first. Data + * toggle synchronization is not needed for SETUP packets. + */ + + ep0 = &priv->eplist[EP0]; + bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); + + bdt = &g_bdt[EP0_OUT_EVEN]; + bdt->addr = (uint8_t *)&priv->ctrl; + bdt->status = (USB_BDT_UOWN | bytecount); + ep0->bdtout = bdt; + + bdt++; + bdt->status = (USB_BDT_UOWN | bytecount); + bdt->addr = (uint8_t *)&priv->ctrl; + + /* Configure the IN BDTs. */ + + bdt = &g_bdt[EP0_IN_EVEN]; + bdt->status = 0; + bdt->addr = 0; + ep0->bdtin = bdt; + + bdt++; + bdt->status = 0; + bdt->addr = 0; + + /* Data toggling is not used on SETUP transfers. And IN transfer resulting + * from a SETUP command should begin with DATA1. + */ + + ep0->rxdata1 = 0; + ep0->txdata1 = 1; +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ +/**************************************************************************** + * Name: khci_epconfigure + ****************************************************************************/ + +static int khci_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct khci_ep_s *privep = (struct khci_ep_s *)ep; + volatile struct usbotg_bdtentry_s *bdt; + uint16_t maxpacket; + uint32_t regval; + uint8_t epno; + bool epin; + bool bidi; + int index; + +#ifdef CONFIG_DEBUG + if (!ep || !desc) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + ulldbg("ERROR: ep=%p desc=%p\n"); + return -EINVAL; + } +#endif + + /* Get the unadorned endpoint address */ + + epno = USB_EPNO(desc->addr); + epin = USB_ISEPIN(desc->addr); + + usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno); + DEBUGASSERT(epno == USB_EPNO(ep->eplog)); + + /* Set the requested type */ + + switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) + { + case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ + regval = epin ? KHCI_EP_INTIN : KHCI_EP_INTOUT; + break; + + case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ + regval = epin ? KHCI_EP_BULKIN : KHCI_EP_BULKOUT; + break; + + case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ + regval = epin ? KHCI_EP_ISOCIN : KHCI_EP_ISOCOUT; + break; + + case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */ + regval = KHCI_EP_CONTROL; + bidi = true; + break; + + default: + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPTYPE), (uint16_t)desc->type); + return -EINVAL; + } + + /* Enable the endpoint */ + + khci_putreg(regval, KINETIS_USB0_ENDPT(epno)); + + /* Setup up buffer descriptor table (BDT) entry/ies for this endpoint */ + + if (epin || bidi) + { + /* Get the pointer to BDT entry */ + + index = EP(epno, EP_DIR_IN, EP_PP_EVEN); + bdt = &g_bdt[index]; + privep->bdtin = bdt; + + /* Mark that we own the entry */ + + bdt->status = 0; + bdt->addr = 0; + + bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + + /* Now do the same for the other buffer. */ + + bdt++; + bdt->status = 0; + bdt->addr = 0; + + bdtdbg("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + } + + if (!epin || bidi) + { + index = EP(epno, EP_DIR_OUT, EP_PP_EVEN); + bdt = &g_bdt[index]; + privep->bdtout = bdt; + + /* Mark that we own the entry */ + + bdt->status = 0; + bdt->addr = 0; + + bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + + /* Now do the same for the other buffer. */ + + bdt++; + bdt->status = 0; + bdt->addr = 0; + + bdtdbg("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + } + + /* Get the maxpacket size of the endpoint. */ + + maxpacket = GETUINT16(desc->mxpacketsize); + DEBUGASSERT(maxpacket <= KHCI_MAXPACKET_SIZE); + ep->maxpacket = maxpacket; + + /* Set the full, logic EP number (that includes direction encoded in bit 7) */ + + if (epin) + { + ep->eplog = USB_EPIN(epno); + } + else + { + ep->eplog = USB_EPOUT(epno); + } + + return OK; +} + +/**************************************************************************** + * Name: khci_epdisable + ****************************************************************************/ + +static int khci_epdisable(struct usbdev_ep_s *ep) +{ + struct khci_ep_s *privep; + volatile uint32_t *ptr; + int epno; + int i; + irqstate_t flags; + +#ifdef CONFIG_DEBUG + if (!ep) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + ulldbg("ERROR: ep=%p\n", ep); + return -EINVAL; + } +#endif + + privep = (struct khci_ep_s *)ep; + epno = USB_EPNO(ep->eplog); + usbtrace(TRACE_EPDISABLE, epno); + + /* Cancel any ongoing activity */ + + flags = enter_critical_section(); + khci_cancelrequests(privep, -ESHUTDOWN); + + /* Disable the endpoint */ + + khci_putreg(0, KINETIS_USB0_ENDPT(epno)); + + /* Reset the BDTs for the endpoint. Four BDT entries per endpoint; Two + * 32-bit words per BDT. + */ + + ptr = (uint32_t *)&g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)]; + for (i = 0; i < USB_BDT_WORD_SIZE * USB_NBDTS_PER_EP; i++) + { + *ptr++ = 0; + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: khci_epallocreq + ****************************************************************************/ + +static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep) +{ + struct khci_req_s *privreq; + +#ifdef CONFIG_DEBUG + if (!ep) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); + + privreq = (struct khci_req_s *)kmm_malloc(sizeof(struct khci_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct khci_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: khci_epfreereq + ****************************************************************************/ + +static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct khci_req_s *privreq = (struct khci_req_s *)req; + +#ifdef CONFIG_DEBUG + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); + + kmm_free(privreq); +} + +/**************************************************************************** + * Name: khci_epsubmit + ****************************************************************************/ + +static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct khci_req_s *privreq = (struct khci_req_s *)req; + struct khci_ep_s *privep = (struct khci_ep_s *)ep; + struct khci_usbdev_s *priv; + irqstate_t flags; + uint8_t epno; + int ret = OK; + +#ifdef CONFIG_DEBUG + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + ulldbg("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog)); + priv = privep->dev; + +#ifdef CONFIG_DEBUG + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + ulldbg("ERROR: driver=%p\n", priv->driver); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + epno = USB_EPNO(ep->eplog); + req->result = -EINPROGRESS; + req->xfrd = 0; + privreq->inflight[0] = 0; +#ifndef CONFIG_USBDEV_NOWRITEAHEAD + privreq->inflight[1] = 0; +#endif + flags = enter_critical_section(); + + /* Add the new request to the request queue for the OUT endpoint */ + + khci_addlast(&privep->pend, privreq); + + /* Handle IN (device-to-host) requests. NOTE: If the class device is + * using the bi-directional EP0, then we assume that they intend the EP0 + * IN functionality. + */ + + if (USB_ISEPIN(ep->eplog) || epno == EP0) + { + usbtrace(TRACE_INREQQUEUED(epno), req->len); + + /* If the endpoint is not stalled and an IN endpoint BDT is available, + * then transfer the data now. + */ + + if (!privep->stalled) + { + (void)khci_wrrequest(priv, privep); + } + } + + /* Handle OUT (host-to-device) requests */ + + else + { + usbtrace(TRACE_OUTREQQUEUED(epno), req->len); + + /* Set up the read operation (unless the endpoint is stalled). Because + * the KHCI supports ping-pong* buffering. There may be two pending + * read requests. The following call will attempt to setup a read + * using this request for this endpoint. It is not harmful if this + * fails. + */ + + if (!privep->stalled) + { + (void)khci_rdrequest(priv, privep); + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: khci_epcancel + ****************************************************************************/ + +static int khci_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +{ + struct khci_ep_s *privep = (struct khci_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); + + flags = enter_critical_section(); + khci_cancelrequests(privep, -EAGAIN); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: khci_epbdtstall + ****************************************************************************/ + +static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) +{ + struct khci_ep_s *privep; + struct khci_usbdev_s *priv; + volatile struct usbotg_bdtentry_s *bdt; + volatile struct usbotg_bdtentry_s *otherbdt; + uint32_t regaddr; + uint32_t regval; + uint8_t epno; + + /* Recover pointers */ + + privep = (struct khci_ep_s *)ep; + priv = (struct khci_usbdev_s *)privep->dev; + epno = USB_EPNO(ep->eplog); + + /* Check for an IN endpoint */ + + if (epin) + { + /* Get a pointer to the current IN BDT */ + + bdt = privep->bdtin; + + /* Get the other BDT */ + + otherbdt = &g_bdt[EP(epno, EP_DIR_IN, EP_PP_EVEN)]; + if (otherbdt == bdt) + { + otherbdt++; + } + + /* Reset the data toggle */ + + privep->txdata1 = false; + } + + /* Otherwise it is an an OUT endpoint. */ + + else + { + /* Get a pointer to the current OUT BDT */ + + bdt = privep->bdtout; + + /* Get a pointer to the other BDT */ + + otherbdt = &g_bdt[EP(epno, EP_DIR_OUT, EP_PP_EVEN)]; + if (otherbdt == bdt) + { + otherbdt++; + } + + /* Reset the data toggle */ + + privep->rxdata1 = false; + } + + /* Handle the resume condition */ + + if (resume) + { + /* Resuming a stalled endpoint */ + + usbtrace(TRACE_EPRESUME, epno); + + /* Point to the appropriate EP register */ + + regaddr = KINETIS_USB0_ENDPT(epno); + + /* Clear the STALL bit in the UEP register */ + + regval = khci_getreg(regaddr); + regval &= ~USB_ENDPT_EPSTALL; + khci_putreg(regval, regaddr); + + /* Check for the EP0 OUT endpoint. This is a special case because we + * need to set it up to receive the next setup packet (Hmmm... what + * if there are queued outgoing reponses. We need to revisit this.) + */ + + if (epno == 0 && !epin) + { + uint32_t bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); + uint32_t physaddr = &priv->ctrl; + + /* Configure the other BDT to receive a SETUP command. */ + + otherbdt->addr = (uint8_t *)physaddr; + otherbdt->status = (USB_BDT_UOWN | bytecount); + + /* Configure the current BDT to receive a SETUP command. */ + + bdt->addr = (uint8_t *)physaddr; + bdt->status = (USB_BDT_UOWN | bytecount); + + bdtdbg("EP0 BDT IN [%p] {%08x, %08x}\n", + bdt, bdt->status, bdt->addr); + bdtdbg("EP0 BDT IN [%p] {%08x, %08x}\n", + otherbdt, otherbdt->status, otherbdt->addr); + } + else + { + /* Return the other BDT to the CPU. */ + + otherbdt->addr = 0; + otherbdt->status = 0; + + /* Return the current BDT to the CPU. */ + + bdt->addr = 0; + bdt->status = 0; + + bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); + bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + + /* Restart any queued requests (after a delay so that we can be assured + * that the hardware has recovered from the stall -- I don't know of any + * other way to assure this.). + */ + + khci_delayedrestart(priv, epno); + } + } + + /* Handle the stall condition */ + + else + { + usbtrace(TRACE_EPSTALL, epno); + privep->stalled = true; + + /* Stall the other BDT. */ + + otherbdt->status = (USB_BDT_UOWN | USB_BDT_BSTALL); + otherbdt->addr = 0; + + /* Stall the current BDT. */ + + bdt->status = (USB_BDT_UOWN | USB_BDT_BSTALL); + bdt->addr = 0; + + /* Stop any queued requests. Hmmm.. is there a race condition here? */ + + khci_rqstop(privep); + + bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); + bdtdbg("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + } + + return OK; +} + +/**************************************************************************** + * Name: khci_epstall + ****************************************************************************/ + +static int khci_epstall(struct usbdev_ep_s *ep, bool resume) +{ + struct khci_ep_s *privep; + irqstate_t flags; + int ret; + +#ifdef CONFIG_DEBUG + if (!ep) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Recover pointers */ + + privep = (struct khci_ep_s *)ep; + + /* STALL or RESUME the endpoint */ + + flags = enter_critical_section(); + + /* Special case EP0. When we stall EP0 we have to stall both the IN and + * OUT BDTs. + */ + + if (USB_EPNO(ep->eplog) == 0) + { + ret = khci_epbdtstall(ep, resume, true); + if (ret == OK) + { + ret = khci_epbdtstall(ep, resume, false); + } + + /* Set the EP0 control state appropriately */ + + privep->dev->ctrlstate = resume ? CTRLSTATE_WAITSETUP : CTRLSTATE_STALLED; + } + + /* Otherwise, select the BDT for the endpoint direction */ + + else + { + /* It is a unidirectional endpoint */ + + ret = khci_epbdtstall(ep, resume, USB_ISEPIN(ep->eplog)); + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Device Controller Operations + ****************************************************************************/ +/**************************************************************************** + * Name: khci_allocep + ****************************************************************************/ + +static struct usbdev_ep_s *khci_allocep(struct usbdev_s *dev, uint8_t epno, + bool epin, uint8_t eptype) +{ + struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev; + struct khci_ep_s *privep = NULL; + uint16_t epset = KHCI_ENDP_ALLSET; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); +#ifdef CONFIG_DEBUG + if (!dev) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + /* Ignore any direction bits in the logical address */ + + epno = USB_EPNO(epno); + + /* A logical address of 0 means that any endpoint will do */ + + if (epno > 0) + { + /* Otherwise, we will return the endpoint structure only for the requested + * 'logical' endpoint. All of the other checks will still be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epno >= KHCI_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BADEPNO), (uint16_t)epno); + return NULL; + } + + /* Convert the logical address to a physical OUT endpoint address and + * remove all of the candidate endpoints from the bitset except for the + * the IN/OUT pair for this logical address. + */ + + epset = KHCI_ENDP_BIT(epno); + } + + /* Check if the selected endpoint number is available */ + + privep = khci_epreserve(priv, epset); + if (!privep) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EPRESERVE), (uint16_t)epset); + return NULL; + } + + return &privep->ep; +} + +/**************************************************************************** + * Name: khci_freeep + ****************************************************************************/ + +static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +{ + struct khci_usbdev_s *priv; + struct khci_ep_s *privep; + +#ifdef CONFIG_DEBUG + if (!dev || !ep) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + priv = (struct khci_usbdev_s *)dev; + privep = (struct khci_ep_s *)ep; + usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); + DEBUGASSERT(priv && privep); + + /* Disable the endpoint */ + + (void)khci_epdisable(ep); + + /* Mark the endpoint as available */ + + khci_epunreserve(priv, privep); +} + +/**************************************************************************** + * Name: khci_getframe + ****************************************************************************/ + +static int khci_getframe(struct usbdev_s *dev) +{ + uint16_t frml; + uint16_t frmh; + uint16_t tmp; + +#ifdef CONFIG_DEBUG + if (!dev) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Return the last frame number detected by the hardware. Thr FRMH/L + * registers are updated with the current frame number whenever a SOF + * TOKEN is received. + */ + + do + { + /* Loop until we can be sure that there was no wrap from the FRML + * to the FRMH register. + */ + + frmh = khci_getreg(KINETIS_USB0_FRMNUMH) & USB_FRMNUMH_MASK; + frml = khci_getreg(KINETIS_USB0_FRMNUML) & USB_FRMNUML_MASK; + tmp = khci_getreg(KINETIS_USB0_FRMNUMH) & USB_FRMNUMH_MASK; + } + while (frmh != tmp); + + /* Combine to for the full 11-bit value */ + + tmp = (frmh) << 8 | frml; + usbtrace(TRACE_DEVGETFRAME, tmp); + return tmp; +} + +/**************************************************************************** + * Name: khci_wakeup + ****************************************************************************/ + +static int khci_wakeup(struct usbdev_s *dev) +{ + struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev; + + usbtrace(TRACE_DEVWAKEUP, 0); +#ifdef CONFIG_DEBUG + if (!dev) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Resume normal operation. */ + + khci_resume(priv); + return OK; +} + +/**************************************************************************** + * Name: khci_selfpowered + ****************************************************************************/ + +static int khci_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct khci_usbdev_s *priv = (struct khci_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG + if (!dev) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Initialization/Reset + ****************************************************************************/ + +/**************************************************************************** + * Name: khci_reset + * + * Description: + * Reset the software and hardware states. If the USB controller has been + * attached to a host, then connect to the bus as well. At the end of + * this reset, the hardware should be in the full up, ready-to-run state. + * + ****************************************************************************/ + +static void khci_reset(struct khci_usbdev_s *priv) +{ + /* Reset the software configuration */ + + khci_swreset(priv); + + /* Re-configure the USB controller in its initial, unconnected state */ + + khci_hwreset(priv); + + /* khci_attach() was called, then the attach flag will be set and we + * should also attach to the USB bus. + */ + + if (priv->attached) + { + /* usbdev_attach() has already been called.. attach to the bus + * now + */ + + khci_attach(priv); + } +} + +/**************************************************************************** + * Name: khci_attach + ****************************************************************************/ + +static void khci_attach(struct khci_usbdev_s *priv) +{ + uint32_t regval; + + /* Check if we are in the detached state */ + + if (priv->devstate == DEVSTATE_DETACHED) + { + /* Disable USB interrupts at the interrupt controller */ + + up_disable_irq(KINETIS_IRQ_USBOTG); + + /* Initialize registers to known states. */ + + //khci_putreg(0, KINETIS_USB0_CTL); + +#if 1 + khci_putreg(0x1,KINETIS_USB0_CTL); + khci_putreg(0,KINETIS_USB0_USBCTRL); +#endif + + /* Enable interrupts at the USB controller */ + + khci_putreg(ERROR_INTERRUPTS, KINETIS_USB0_ERREN); + khci_putreg(NORMAL_INTERRUPTS, KINETIS_USB0_INTEN); + + /* Configure EP0 */ + + khci_ep0configure(priv); + + /* Flush any pending transactions */ +#if 1 + while ((khci_getreg(KINETIS_USB0_ISTAT) & USB_INT_TOKDNE) != 0) + { + khci_putreg(USB_INT_TOKDNE, KINETIS_USB0_ISTAT); + } + + /* Make sure packet processing is enabled */ + + regval = khci_getreg(KINETIS_USB0_CTL); + regval &= ~USB_CTL_TXSUSPENDTOKENBUSY; + khci_putreg(regval, KINETIS_USB0_CTL); + + /* Enable the USB module and attach to bus */ + + do + { + regval = khci_getreg(KINETIS_USB0_CTL); + if ((regval & USB_CTL_USBENSOFEN) == 0) + { + khci_putreg(regval | USB_CTL_USBENSOFEN, KINETIS_USB0_CTL); + } + } + while ((regval & USB_CTL_USBENSOFEN) == 0); + + /* Enable OTG */ + +#ifdef CONFIG_USBOTG + regval = khci_getreg(KINETIS_USB0_OTGCTL); + regval |= (USBOTG_CON_DPPULUP | USBOTG_CON_OTGEN); + khci_putreg(regval, KINETIS_USB0_OTGCTL); +#endif + + /* Transition to the attached state */ + + priv->devstate = DEVSTATE_ATTACHED; + priv->usbdev.speed = USB_SPEED_FULL; + + /* Clear all pending USB interrupts */ + + khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT); + khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT); +#endif + + /* Enable USB interrupts at the interrupt controller */ + + up_enable_irq(KINETIS_IRQ_USBOTG); + + /* Enable pull-up to connect the device. The host should enumerate us + * some time after this + */ + + kinetis_usbpullup(&priv->usbdev, true); + } +} + +/**************************************************************************** + * Name: khci_detach + ****************************************************************************/ + +static void khci_detach(struct khci_usbdev_s *priv) +{ + uint32_t regval; + /* Disable USB interrupts at the interrupt controller */ + + up_disable_irq(KINETIS_IRQ_USBOTG); + + /* Disable the USB controller and detach from the bus. */ + + khci_putreg(0, KINETIS_USB0_CTL); + + /* Mask all USB interrupts */ + + khci_putreg(0, KINETIS_USB0_INTEN); + + /* We are now in the detached state */ + + priv->attached = 0; + priv->devstate = DEVSTATE_DETACHED; + +#ifdef CONFIG_USBOTG + /* Disable the D+ Pullup */ + + regval = khci_getreg(KINETIS_USB0_OTGCTL); + regval &= ~USBOTG_CON_DPPULUP; + khci_putreg(regval, KINETIS_USB0_OTGCTL); + + /* Disable and deactivate HNP */ +#warning Missing Logic + + /* Check if the ID Pin Changed State */ + + if ((khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_OTGICR) & USBOTG_INT_ID) != 0) + { + /* Re-detect & Initialize */ +#warning "Missing logic" + + /* Clear ID Interrupt Flag */ + + khci_putreg(USBOTG_INT_ID, KINETIS_USB0_ISTAT); + } +#endif +} + +/**************************************************************************** + * Name: khci_swreset + ****************************************************************************/ + +static void khci_swreset(struct khci_usbdev_s *priv) +{ + int epno; + + /* Tell the class driver that we are disconnected. The class driver + * should then accept any new configurations. + */ + + if (priv->driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + /* Flush and reset endpoint states (except EP0) */ + + for (epno = 1; epno < KHCI_NENDPOINTS; epno++) + { + struct khci_ep_s *privep = &priv->eplist[epno]; + + /* Cancel any queued requests. Since they are canceled + * with status -ESHUTDOWN, then will not be requeued + * until the configuration is reset. NOTE: This should + * not be necessary... the CLASS_DISCONNECT above should + * result in the class implementation calling khci_epdisable + * for each of its configured endpoints. + */ + + khci_cancelrequests(privep, -EAGAIN); + + /* Reset endpoint status */ + + privep->stalled = false; + privep->halted = false; + privep->txnullpkt = false; + } + + /* Reset to the default address */ + + khci_putreg(0, KINETIS_USB0_ADDR); + + /* Unconfigure each endpoint by clearing the endpoint control registers + * (except EP0) + */ + + for (epno = 1; epno < KHCI_NENDPOINTS; epno++) + { + khci_putreg(0, KINETIS_USB0_ENDPT(epno)); + } + + /* Reset the control state */ + + priv->ctrlstate = CTRLSTATE_WAITSETUP; + priv->rxbusy = 0; +} + +/**************************************************************************** + * Name: khci_hwreset + * + * Description: + * Reset the hardware and leave it in a known, unready state. + * + ****************************************************************************/ + +static void khci_hwreset(struct khci_usbdev_s *priv) +{ + uint32_t physaddr; + uint32_t regval; + +#define USB_FLASH_ACCESS +#ifdef USB_FLASH_ACCESS + /* Allow USBOTG-FS Controller to Read from FLASH */ + regval = getreg32(KINETIS_FMC_PFAPR); + regval &= ~(FMC_PFAPR_M4AP_MASK); + regval |= (FMC_PFAPR_RDONLY << FMC_PFAPR_M4AP_SHIFT); + putreg32(regval, KINETIS_FMC_PFAPR); +#endif + + /* Clear all of the buffer descriptor table (BDT) entries */ + + memset((void *)g_bdt, 0, sizeof(g_bdt)); + + /* Soft reset the USB Module*/ + regval = khci_getreg(KINETIS_USB0_USBTRC0); + regval |= USB_USBTRC0_USBRESET; + khci_putreg(regval,KINETIS_USB0_USBTRC0); + + //is this really necessary? + while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET); + + /* Set the address of the buffer descriptor table (BDT) + * + * BDTP1: Bit 1-7: Bits 9-15 of the BDT base address + * BDTP2: Bit 0-7: Bits 16-23 of the BDT base address + * BDTP3: Bit 0-7: Bits 24-31 of the BDT base address + */ + + khci_putreg((uint8_t)((uint32_t)g_bdt >> 24), KINETIS_USB0_BDTPAGE3); + khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2); + khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1); + + ulldbg("BDT Address %hhx \n" ,&g_bdt); + ulldbg("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3)); + ulldbg("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2)); + ulldbg("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1)); + + + /* Clear any pending interrupts */ + + khci_putreg(0xFF, KINETIS_USB0_ERRSTAT); + khci_putreg(0xFF, KINETIS_USB0_ISTAT); + khci_putreg(0xFF,KINETIS_USB0_OTGISTAT); + +#if 1 + + /* Assert reset request to all of the Ping Pong buffer pointers. This + * will reset all Even/Odd buffer pointers to the EVEN BD banks. + */ + + regval = khci_getreg(KINETIS_USB0_CTL); + regval |= USB_CTL_ODDRST; + khci_putreg(regval, KINETIS_USB0_CTL); + + /* Bring the ping pong buffer pointers out of reset */ + + regval &= ~USB_CTL_ODDRST; + khci_putreg(regval, KINETIS_USB0_CTL); + +#endif + +#if 1 + /*Undocumented bit*/ + regval = khci_getreg(KINETIS_USB0_USBTRC0); + regval |= 0x40; + khci_putreg(regval,KINETIS_USB0_USBTRC0); +#endif + + priv->devstate = DEVSTATE_DETACHED; +} + +/**************************************************************************** + * Name: khci_stateinit + ****************************************************************************/ + +static void khci_stateinit(struct khci_usbdev_s *priv) +{ + int epno; + + /* Disconnect the device / disable the pull-up. We don't want the + * host to enumerate us until the class driver is registered. + */ + + kinetis_usbpullup(&priv->usbdev, false); + + /* Initialize the device state structure. NOTE: many fields + * have the initial value of zero and, hence, are not explicitly + * initialized here. + */ + + memset(priv, 0, sizeof(struct khci_usbdev_s)); + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->eplist[EP0].ep; + priv->epavail = KHCI_ENDP_ALLSET & ~KHCI_ENDP_BIT(EP0); + priv->rwakeup = 1; + + /* Initialize the endpoint list */ + + for (epno = 0; epno < KHCI_NENDPOINTS; epno++) + { + struct khci_ep_s *privep = &priv->eplist[epno]; + + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the (physical) endpoint number which is just the index to the + * endpoint. + */ + + privep->ep.ops = &g_epops; + privep->dev = priv; + privep->ep.eplog = epno; + + /* We will use a fixed maxpacket size for all endpoints (perhaps + * ISOC endpoints could have larger maxpacket???). A smaller + * packet size can be selected when the endpoint is configured. + */ + + privep->ep.maxpacket = KHCI_MAXPACKET_SIZE; + } + + /* Select a smaller endpoint size for EP0 */ + +#if KHCI_EP0MAXPACKET < KHCI_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = KHCI_EP0MAXPACKET; +#endif +} + +/**************************************************************************** + * Name: khci_hwshutdown + ****************************************************************************/ + +static void khci_hwshutdown(struct khci_usbdev_s *priv) +{ + uint32_t regval; + + /* Put the hardware and driver in its initial, unconnected state */ + + khci_swreset(priv); + khci_hwreset(priv); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable all interrupts and force the USB controller into reset */ + + khci_putreg(0, KINETIS_USB0_ERREN); + khci_putreg(0, KINETIS_USB0_INTEN); + + /* Clear any pending interrupts */ + + khci_putreg(USB_EINT_ALL, KINETIS_USB0_ERRSTAT); + khci_putreg(USB_INT_ALL, KINETIS_USB0_ISTAT); + + /* Disconnect the device / disable the pull-up */ + + kinetis_usbpullup(&priv->usbdev, false); + + /* Power down the USB controller */ +#warning FIXME powerdown USB Controller +#if 0 + regval = khci_getreg(KHCI_USB_PWRC); + regval &= ~USB_PWRC_USBPWR; + khci_putreg(regval, KHCI_USB_PWRC); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +/**************************************************************************** + * Name: up_usbinitialize + * + * Description: + * Initialize the USB driver + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) + +void up_usbinitialize(void) +{ + uint32_t regval; + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ +#if 1 + //1: Select clock source + regval = getreg32(KINETIS_SIM_SOPT2); + regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC; + putreg32(regval, KINETIS_SIM_SOPT2); + + regval = getreg32(KINETIS_SIM_CLKDIV2); +#if defined(CONFIG_TEENSY_3X_OVERCLOCK) + regval = SIM_CLKDIV2_USBDIV(1); //(USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock +#else + //72Mhz + regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC; +#endif + putreg32(regval, KINETIS_SIM_CLKDIV2); + + //2: Gate USB clock + regval = getreg32(KINETIS_SIM_SCGC4); + regval |= SIM_SCGC4_USBOTG; + putreg32(regval, KINETIS_SIM_SCGC4); + +#endif + + + struct khci_usbdev_s *priv = &g_usbdev; + + usbtrace(TRACE_DEVINIT, 0); + + /* Initialize the driver state structure */ + + khci_stateinit(priv); + + /* Then perform a few one-time initialization operstions. First, initialize + * the watchdog timer that is used to perform a delayed queue restart + * after recovering from a stall. + */ + + priv->epstalled = 0; + priv->wdog = wd_create(); + + /* Attach USB controller interrupt handler. The hardware will not be + * initialized and interrupts will not be enabled until the class device + * driver is bound. Getting the IRQs here only makes sure that we have + * them when we need them later. + */ + + if (irq_attach(KINETIS_IRQ_USBOTG, khci_interrupt) != 0) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_IRQREGISTRATION), + (uint16_t)KINETIS_IRQ_USBOTG); + up_usbuninitialize(); + } +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(KINETIS_IRQ_USBOTG, 112); +#endif +} + +/**************************************************************************** + * Name: up_usbuninitialize + * Description: + * Initialize the USB driver + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_usbuninitialize(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct khci_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + flags = enter_critical_section(); + usbtrace(TRACE_DEVUNINIT, 0); + + /* Disable and detach the USB IRQs */ + + up_disable_irq(KINETIS_IRQ_USBOTG); + irq_detach(KINETIS_IRQ_USBOTG); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Put the hardware in an inactive state */ + + khci_hwshutdown(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct khci_usbdev_s *priv = &g_usbdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_BINDFAILED), (uint16_t)-ret); + priv->driver = NULL; + } + + /* The class driver has been successfully bound. */ + + else + { + /* Setup the USB controller in it initial ready-to-run state (might + * be connected or unconnected, depending on usbdev_attach() has + * been called). + */ + + DEBUGASSERT(priv->devstate == DEVSTATE_DETACHED); + khci_reset(priv); + } + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver. If the USB device is connected to a + * USB host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct khci_usbdev_s *priv = &g_usbdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. This will put + * the hardware back into its initial, unconnected state. + */ + + flags = enter_critical_section(); + khci_swreset(priv); + khci_hwreset(priv); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts (but keep them attached) */ + + up_disable_irq(KINETIS_IRQ_USBOTG); + + /* Put the hardware in an inactive state. Then bring the hardware back up + * in the reset state (this is probably not necessary, the khci_hwreset() + * call above was probably sufficient). + */ + + khci_hwshutdown(priv); + khci_stateinit(priv); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: khci_usbattach and khci_usbdetach + * + * Description: + * The USB stack must be notified when the device is attached or detached + * by calling one of these functions. + * + ****************************************************************************/ + +void khci_usbattach(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct khci_usbdev_s *priv = &g_usbdev; + + /* Mark that we are attached */ + + priv->attached = 1; + + /* This API may be called asynchronously from other initialization + * interfaces. In particular, we may not want to attach the bus yet... + * that should only be done when the class driver is attached. Has + * the class driver been attached? + */ + + if (priv->driver) + { + /* Yes.. then attach to the bus */ + + khci_attach(priv); + } +} + +void khci_usbdetach(void) +{ + /* For now there is only one USB controller, but we will always refer to + * it using a pointer to make any future ports to multiple USB controllers + * easier. + */ + + struct khci_usbdev_s *priv = &g_usbdev; + + /* Detach from the bus */ + + khci_detach(priv); +} + +#endif /* CONFIG_USBDEV && CONFIG_KHCI_USB */ diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h index 127c718312..22a474a824 100644 --- a/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -217,6 +217,8 @@ #define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */ #define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */ +#define USB_INT_ALL 0xFF + /* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */ #define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */ @@ -228,6 +230,8 @@ /* Bit 6: Reserved */ #define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */ +#define USB_EINT_ALL 0xBF + /* Status Register (8-bit) */ /* Bits 0-1: Reserved */ @@ -259,6 +263,7 @@ #define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT) /* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */ +#define USB_FRMNUML_MASK 0xFF /* Frame Number Register High (8-bit) */ /* Bits 3-7: Reserved */ #define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */ @@ -313,9 +318,50 @@ #define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */ #define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */ -/******************************************************************************************** +/* Buffer Descriptor Table (BDT) ****************************************************/ +/* Offset 0: On write (software->hardware) */ + +#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */ +#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */ +#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */ +#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */ +#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */ +#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */ +#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */ +#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */ +#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT) + +#define USB_BDT_DATA0 0 /* DATA0 packet expected next */ +#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */ +#define USB_BDT_COWN 0 /* CPU owns the descriptor */ + +/* Offset 0: On read (hardware->software) */ + +#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */ +#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT) + /* Bit 7: USB Own bit (same) */ + /* Bits 16-25: Byte Count bits (same) */ + +/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */ + +#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */ +#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */ +#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */ + +/************************************************************************************ * Public Types - ********************************************************************************************/ + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Buffer Descriptor Status Register layout. */ + +struct usbotg_bdtentry_s +{ + uint32_t status; /* Status, byte count, and PID */ + uint8_t *addr; /* Buffer address */ +}; +#endif /******************************************************************************************** * Public Data @@ -325,4 +371,9 @@ * Public Functions ********************************************************************************************/ +struct usbdev_s; +int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable); +void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume); +void khci_usbattach(void); + #endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */ From 983ac18c51cd475d11ca4c66baf26f56fc28997d Mon Sep 17 00:00:00 2001 From: kfazz Date: Mon, 6 Jun 2016 14:00:02 -0400 Subject: [PATCH 03/18] Teensy 3.x usb support and example configuration --- configs/teensy-3.x/src/Makefile | 3 + configs/teensy-3.x/src/k20_appinit.c | 6 + configs/teensy-3.x/src/k20_usbdev.c | 133 ++++ configs/teensy-3.x/usbnsh/.config | 989 +++++++++++++++++++++++++++ configs/teensy-3.x/usbnsh/Make.defs | 117 ++++ configs/teensy-3.x/usbnsh/defconfig | 989 +++++++++++++++++++++++++++ configs/teensy-3.x/usbnsh/setenv.sh | 80 +++ 7 files changed, 2317 insertions(+) create mode 100644 configs/teensy-3.x/src/k20_usbdev.c create mode 100644 configs/teensy-3.x/usbnsh/.config create mode 100644 configs/teensy-3.x/usbnsh/Make.defs create mode 100644 configs/teensy-3.x/usbnsh/defconfig create mode 100755 configs/teensy-3.x/usbnsh/setenv.sh diff --git a/configs/teensy-3.x/src/Makefile b/configs/teensy-3.x/src/Makefile index ad839632dd..ff73a6953a 100644 --- a/configs/teensy-3.x/src/Makefile +++ b/configs/teensy-3.x/src/Makefile @@ -43,6 +43,9 @@ CSRCS += k20_autoleds.c else CSRCS += k20_userleds.c endif +ifeq ($(CONFIG_KINETIS_USBOTG),y) +CSRCS += k20_usbdev.c +endif ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += k20_appinit.c diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c index a66f7a38b0..8512a35d33 100644 --- a/configs/teensy-3.x/src/k20_appinit.c +++ b/configs/teensy-3.x/src/k20_appinit.c @@ -74,5 +74,11 @@ int board_app_initialize(uintptr_t arg) { +#ifdef CONFIG_USBDEV + /* Teensy is powered from usb and (bug?) only boots from being programmed, + * so if usb is compiled in signal the controller driver that we're attached now. + */ + khci_usbattach(); +#endif return OK; } diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c new file mode 100644 index 0000000000..a2b3c20ddf --- /dev/null +++ b/configs/teensy-3.x/src/k20_usbdev.c @@ -0,0 +1,133 @@ +/************************************************************************************ + * configs/teensy-3.x/src/k20_usbdev.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "kinetis.h" +#include "kinetis_usbotg.h" +#include "kinetis_sim.h" +#include "teensy-3x.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +#define khci_getreg(addr) getreg8(addr) +#define khci_putreg(val,addr) putreg8(val,addr) +#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: kinetis_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the KwikStik-K40 board. + * + ************************************************************************************/ + +void kinetis_usbinitialize(void) +{ + uint32_t regval; + +// khci_usbattach(); +} + +/************************************************************************************ + * Name: kinetis_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB software + * connect and disconnect), then the board software must provide kinetis_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be + * NULL. + * + ************************************************************************************/ + +int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + uint32_t regval; +if (enable) +khci_putreg(USB_CONTROL_DPPULLUPNONOTG, KINETIS_USB0_CONTROL); +else +khci_putreg(0,KINETIS_USB0_CONTROL); +#if 0 + regval = khci_getreg(KINETIS_USB0_OTGCTL); + if (enable) + regval |= (1<<2); + else + regval &= ~(1<<2); + khci_putreg(regval,KINETIS_USB0_OTGCTL); +#endif + + return OK; +} + +/************************************************************************************ + * Name: kinetis_usbsuspend + * + * Description: + * Board logic must provide the kinetis_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + ulldbg("resume: %d\n", resume); +#warning "Missing logic" +} diff --git a/configs/teensy-3.x/usbnsh/.config b/configs/teensy-3.x/usbnsh/.config new file mode 100644 index 0000000000..0f0f54c88e --- /dev/null +++ b/configs/teensy-3.x/usbnsh/.config @@ -0,0 +1,989 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +CONFIG_EXPERIMENTAL=y +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG=y +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_VERBOSE is not set + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_LEDS is not set +# CONFIG_DEBUG_ANALOG is not set +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_SPI is not set +# CONFIG_DEBUG_USB is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +CONFIG_ARCH_CHIP_KINETIS=y +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="kinetis" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +# CONFIG_DEBUG_HARDFAULT is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# Kinetis Configuration Options +# +# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set +CONFIG_ARCH_CHIP_MK20DX256VLH7=y +# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set +CONFIG_ARCH_FAMILY_K20=y +# CONFIG_ARCH_FAMILY_K40 is not set +# CONFIG_ARCH_FAMILY_K60 is not set + +# +# Kinetis Peripheral Support +# +# CONFIG_KINETIS_TRACE is not set +# CONFIG_KINETIS_FLEXBUS is not set +CONFIG_KINETIS_UART0=y +# CONFIG_KINETIS_UART1 is not set +# CONFIG_KINETIS_UART2 is not set +# CONFIG_KINETIS_UART3 is not set +# CONFIG_KINETIS_UART4 is not set +# CONFIG_KINETIS_UART5 is not set +# CONFIG_KINETIS_FLEXCAN0 is not set +# CONFIG_KINETIS_FLEXCAN1 is not set +# CONFIG_KINETIS_SPI0 is not set +# CONFIG_KINETIS_SPI1 is not set +# CONFIG_KINETIS_SPI2 is not set +# CONFIG_KINETIS_I2C0 is not set +# CONFIG_KINETIS_I2C1 is not set +# CONFIG_KINETIS_I2S is not set +# CONFIG_KINETIS_DAC0 is not set +# CONFIG_KINETIS_DAC1 is not set +# CONFIG_KINETIS_ADC0 is not set +# CONFIG_KINETIS_ADC1 is not set +# CONFIG_KINETIS_CMP is not set +# CONFIG_KINETIS_VREF is not set +# CONFIG_KINETIS_SDHC is not set +# CONFIG_KINETIS_FTM0 is not set +# CONFIG_KINETIS_FTM1 is not set +# CONFIG_KINETIS_FTM2 is not set +# CONFIG_KINETIS_LPTIMER is not set +# CONFIG_KINETIS_RTC is not set +# CONFIG_KINETIS_EWM is not set +# CONFIG_KINETIS_CMT is not set +CONFIG_KINETIS_USBOTG=y +# CONFIG_KINETIS_USBDCD is not set +# CONFIG_KINETIS_LLWU is not set +# CONFIG_KINETIS_TSI is not set +# CONFIG_KINETIS_FTFL is not set +# CONFIG_KINETIS_DMA is not set +# CONFIG_KINETIS_CRC is not set +# CONFIG_KINETIS_PDB is not set +# CONFIG_KINETIS_PIT is not set + +# +# Kinetis GPIO Interrupt Configuration +# +# CONFIG_GPIO_IRQ is not set + +# +# Kinetis UART Configuration +# +CONFIG_KINETIS_UARTFIFOS=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ARCH_USBDUMP is not set +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=6024 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x1fff8000 +CONFIG_RAM_SIZE=65536 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_TEENSY_3X=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="teensy-3.x" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# +# CONFIG_TEENSY_3X_OVERCLOCK is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_USBDEVCTRL=y +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CRCGENERATION is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_IOEXPANDER is not set +# CONFIG_LCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y +# CONFIG_16550_UART is not set +# CONFIG_ARCH_HAVE_UART is not set +CONFIG_ARCH_HAVE_UART0=y +# CONFIG_ARCH_HAVE_UART1 is not set +# CONFIG_ARCH_HAVE_UART2 is not set +# CONFIG_ARCH_HAVE_UART3 is not set +# CONFIG_ARCH_HAVE_UART4 is not set +# CONFIG_ARCH_HAVE_UART5 is not set +# CONFIG_ARCH_HAVE_UART6 is not set +# CONFIG_ARCH_HAVE_UART7 is not set +# CONFIG_ARCH_HAVE_UART8 is not set +# CONFIG_ARCH_HAVE_SCI0 is not set +# CONFIG_ARCH_HAVE_SCI1 is not set +# CONFIG_ARCH_HAVE_USART0 is not set +# CONFIG_ARCH_HAVE_USART1 is not set +# CONFIG_ARCH_HAVE_USART2 is not set +# CONFIG_ARCH_HAVE_USART3 is not set +# CONFIG_ARCH_HAVE_USART4 is not set +# CONFIG_ARCH_HAVE_USART5 is not set +# CONFIG_ARCH_HAVE_USART6 is not set +# CONFIG_ARCH_HAVE_USART7 is not set +# CONFIG_ARCH_HAVE_USART8 is not set +# CONFIG_ARCH_HAVE_OTHER_UART is not set + +# +# USART Configuration +# +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=128 +CONFIG_USBDEV_TRACE_INITIALIDSET=y + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +# CONFIG_CDCACM_CONSOLE is not set +# CONFIG_CDCACM_IFLOWCONTROL is not set +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=768 +CONFIG_CDCACM_RXBUFSIZE=513 +CONFIG_CDCACM_TXBUFSIZE=769 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set +# CONFIG_USBHOST is not set +# CONFIG_DRIVERS_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_CONSOLE is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set +# CONFIG_SYSLOG_TIMESTAMP is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# +# CONFIG_WIRELESS is not set + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_NSH_USBCONDEV="/dev/ttyACM0" +CONFIG_USBDEV_MINOR=0 + +# +# USB Device Trace Support +# +# CONFIG_NSH_USBDEV_TRACE is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_HEX2BIN is not set +CONFIG_SYSTEM_HEXED=y +CONFIG_SYSTEM_HEXED_STACKSIZE=2048 +CONFIG_SYSTEM_HEXED_PRIORITY=100 +CONFIG_SYSTEM_RAMTEST=y +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_READLINE_MAX_BUILTINS=64 +CONFIG_READLINE_MAX_EXTCMDS=64 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LINELEN=80 +CONFIG_READLINE_CMD_HISTORY_LEN=16 +# CONFIG_SYSTEM_SDCARD is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_VI is not set +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=0 +# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set +# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set +# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set +# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set +# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +CONFIG_SYSTEM_USBMONITOR=y +CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 +CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 +CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 +CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y +CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y +CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y +CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y +CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/teensy-3.x/usbnsh/Make.defs b/configs/teensy-3.x/usbnsh/Make.defs new file mode 100644 index 0000000000..597d2e8cf3 --- /dev/null +++ b/configs/teensy-3.x/usbnsh/Make.defs @@ -0,0 +1,117 @@ +############################################################################ +# configs/teensy-3.1/nsh/Make.defs +# +# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_MK20DX256VLH7),y) + LDSCRIPT = mk20dx256vlh7.ld +else ifeq ($(CONFIG_ARCH_CHIP_MK20DX128VLH5),y) + LDSCRIPT = mk20dx128vlh5.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig new file mode 100644 index 0000000000..0f0f54c88e --- /dev/null +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -0,0 +1,989 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +CONFIG_EXPERIMENTAL=y +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG=y +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_VERBOSE is not set + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_LEDS is not set +# CONFIG_DEBUG_ANALOG is not set +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_SPI is not set +# CONFIG_DEBUG_USB is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +CONFIG_ARCH_CHIP_KINETIS=y +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="kinetis" +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +# CONFIG_DEBUG_HARDFAULT is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# Kinetis Configuration Options +# +# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set +CONFIG_ARCH_CHIP_MK20DX256VLH7=y +# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set +CONFIG_ARCH_FAMILY_K20=y +# CONFIG_ARCH_FAMILY_K40 is not set +# CONFIG_ARCH_FAMILY_K60 is not set + +# +# Kinetis Peripheral Support +# +# CONFIG_KINETIS_TRACE is not set +# CONFIG_KINETIS_FLEXBUS is not set +CONFIG_KINETIS_UART0=y +# CONFIG_KINETIS_UART1 is not set +# CONFIG_KINETIS_UART2 is not set +# CONFIG_KINETIS_UART3 is not set +# CONFIG_KINETIS_UART4 is not set +# CONFIG_KINETIS_UART5 is not set +# CONFIG_KINETIS_FLEXCAN0 is not set +# CONFIG_KINETIS_FLEXCAN1 is not set +# CONFIG_KINETIS_SPI0 is not set +# CONFIG_KINETIS_SPI1 is not set +# CONFIG_KINETIS_SPI2 is not set +# CONFIG_KINETIS_I2C0 is not set +# CONFIG_KINETIS_I2C1 is not set +# CONFIG_KINETIS_I2S is not set +# CONFIG_KINETIS_DAC0 is not set +# CONFIG_KINETIS_DAC1 is not set +# CONFIG_KINETIS_ADC0 is not set +# CONFIG_KINETIS_ADC1 is not set +# CONFIG_KINETIS_CMP is not set +# CONFIG_KINETIS_VREF is not set +# CONFIG_KINETIS_SDHC is not set +# CONFIG_KINETIS_FTM0 is not set +# CONFIG_KINETIS_FTM1 is not set +# CONFIG_KINETIS_FTM2 is not set +# CONFIG_KINETIS_LPTIMER is not set +# CONFIG_KINETIS_RTC is not set +# CONFIG_KINETIS_EWM is not set +# CONFIG_KINETIS_CMT is not set +CONFIG_KINETIS_USBOTG=y +# CONFIG_KINETIS_USBDCD is not set +# CONFIG_KINETIS_LLWU is not set +# CONFIG_KINETIS_TSI is not set +# CONFIG_KINETIS_FTFL is not set +# CONFIG_KINETIS_DMA is not set +# CONFIG_KINETIS_CRC is not set +# CONFIG_KINETIS_PDB is not set +# CONFIG_KINETIS_PIT is not set + +# +# Kinetis GPIO Interrupt Configuration +# +# CONFIG_GPIO_IRQ is not set + +# +# Kinetis UART Configuration +# +CONFIG_KINETIS_UARTFIFOS=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ARCH_USBDUMP is not set +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=6024 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x1fff8000 +CONFIG_RAM_SIZE=65536 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_TEENSY_3X=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="teensy-3.x" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# +# CONFIG_TEENSY_3X_OVERCLOCK is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_USBDEVCTRL=y +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CRCGENERATION is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_IOEXPANDER is not set +# CONFIG_LCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y +# CONFIG_16550_UART is not set +# CONFIG_ARCH_HAVE_UART is not set +CONFIG_ARCH_HAVE_UART0=y +# CONFIG_ARCH_HAVE_UART1 is not set +# CONFIG_ARCH_HAVE_UART2 is not set +# CONFIG_ARCH_HAVE_UART3 is not set +# CONFIG_ARCH_HAVE_UART4 is not set +# CONFIG_ARCH_HAVE_UART5 is not set +# CONFIG_ARCH_HAVE_UART6 is not set +# CONFIG_ARCH_HAVE_UART7 is not set +# CONFIG_ARCH_HAVE_UART8 is not set +# CONFIG_ARCH_HAVE_SCI0 is not set +# CONFIG_ARCH_HAVE_SCI1 is not set +# CONFIG_ARCH_HAVE_USART0 is not set +# CONFIG_ARCH_HAVE_USART1 is not set +# CONFIG_ARCH_HAVE_USART2 is not set +# CONFIG_ARCH_HAVE_USART3 is not set +# CONFIG_ARCH_HAVE_USART4 is not set +# CONFIG_ARCH_HAVE_USART5 is not set +# CONFIG_ARCH_HAVE_USART6 is not set +# CONFIG_ARCH_HAVE_USART7 is not set +# CONFIG_ARCH_HAVE_USART8 is not set +# CONFIG_ARCH_HAVE_OTHER_UART is not set + +# +# USART Configuration +# +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=128 +CONFIG_USBDEV_TRACE_INITIALIDSET=y + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +# CONFIG_CDCACM_CONSOLE is not set +# CONFIG_CDCACM_IFLOWCONTROL is not set +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=768 +CONFIG_CDCACM_RXBUFSIZE=513 +CONFIG_CDCACM_TXBUFSIZE=769 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set +# CONFIG_USBHOST is not set +# CONFIG_DRIVERS_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_CONSOLE is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set +# CONFIG_SYSLOG_TIMESTAMP is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# +# CONFIG_WIRELESS is not set + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_NSH_USBCONDEV="/dev/ttyACM0" +CONFIG_USBDEV_MINOR=0 + +# +# USB Device Trace Support +# +# CONFIG_NSH_USBDEV_TRACE is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_HEX2BIN is not set +CONFIG_SYSTEM_HEXED=y +CONFIG_SYSTEM_HEXED_STACKSIZE=2048 +CONFIG_SYSTEM_HEXED_PRIORITY=100 +CONFIG_SYSTEM_RAMTEST=y +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_READLINE_MAX_BUILTINS=64 +CONFIG_READLINE_MAX_EXTCMDS=64 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LINELEN=80 +CONFIG_READLINE_CMD_HISTORY_LEN=16 +# CONFIG_SYSTEM_SDCARD is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_VI is not set +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=0 +# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set +# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set +# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set +# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set +# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +CONFIG_SYSTEM_USBMONITOR=y +CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 +CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 +CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 +CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y +CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y +CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y +CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y +CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/teensy-3.x/usbnsh/setenv.sh b/configs/teensy-3.x/usbnsh/setenv.sh new file mode 100755 index 0000000000..e96a2ff345 --- /dev/null +++ b/configs/teensy-3.x/usbnsh/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/teensy-3.1/nsh/setenv.sh +# +# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" From a39ff55340408ef6e10b9eea70014ff962078e7d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 6 Jun 2016 12:53:03 -0600 Subject: [PATCH 04/18] Update TODO and README.txt files --- README.txt | 18 +++++++++++------- TODO | 5 +++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/README.txt b/README.txt index db0e5e6c10..b3cb19a407 100644 --- a/README.txt +++ b/README.txt @@ -960,10 +960,13 @@ Native Windows Build In this build, you cannot use a Cygwin or MSYS shell. Rather the build must be performed in a Windows console window. Here is a better terminal than the standard issue, CMD.exe terminal: ConEmu which can be downloaded from: - http://code.google.com/p/conemu-maximus5/ + https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ . Build Tools. The build still relies on some Unix-like commands. I use - the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/. + the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/ + using the 'Download all' selection. Individual packages can be download + instead if you know what you are doing and want a faster download (No, I + can't tell you which packages you should or should not download). Host Compiler: I use the MingGW GCC compiler which can be downloaded from http://www.mingw.org/. If you are using GNUWin32, then it is recommended @@ -971,12 +974,13 @@ Native Windows Build This capability should still be considered a work in progress because: - (1) It has not been verified on all targets and tools, and - (2) it still lacks some of the creature-comforts of the more mature environments. + (1) It has not been verified on all targets and tools, and + (2) it still lacks some of the creature-comforts of the more mature + environments. - There is an alternative to the setenv.sh script available for the Windows - native environment: tools/configure.bat. See tools/README.txt for additional - information. + There is an alternative to the setenv.sh script available for the Windows + native environment: tools/configure.bat. See tools/README.txt for additional + information. Installing GNUWin32 ------------------- diff --git a/TODO b/TODO index 0ce0c457ef..a4c960e2e1 100644 --- a/TODO +++ b/TODO @@ -1605,6 +1605,11 @@ o Build system Description: The way that apps/ no generates Kmenu files depends on changes added to apps/tools/mkkconfig.sh. Similar changes need to be made to apps/tools/mkkconfig.bat to restore the Windows Native build. + UPDATE: The mkkconfig.bat script has been updated and appears to work. + A native build has still not been attempted and there could likely be + issues the carriage returns in Kconfig files. There are also some + issues the interpreters/ficl and bas directories during 'make menuconfig' + that still need to be investigated. Status: Open Priority: Low, since I am not aware of anyone using the Windows Native build. But, of course, very high if you want to use it. From f75837a1109eab571528ccc0a5fc699c546f9d60 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 6 Jun 2016 13:35:27 -0600 Subject: [PATCH 05/18] Changes from review of the last PR --- arch/arm/src/kinetis/kinetis_usbdev.c | 348 +++++---- arch/arm/src/kinetis/kinetis_usbotg.h | 6 +- configs/teensy-3.x/src/k20_appinit.c | 2 + configs/teensy-3.x/src/k20_usbdev.c | 40 +- configs/teensy-3.x/usbnsh/.config | 989 -------------------------- configs/teensy-3.x/usbnsh/Make.defs | 3 +- configs/teensy-3.x/usbnsh/defconfig | 125 ++-- configs/teensy-3.x/usbnsh/setenv.sh | 12 +- 8 files changed, 254 insertions(+), 1271 deletions(-) delete mode 100644 configs/teensy-3.x/usbnsh/.config diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 75fcdb2cc7..287f0f3abd 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_usbdev.c * - * Copyright (C) 2011-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -65,8 +65,6 @@ #include #include "up_arch.h" -//#include "pic32mx.h" -//#include "pic32mx-usbotg.h" #include "kinetis.h" #include "kinetis_usbotg.h" #include "kinetis_sim.h" @@ -77,9 +75,8 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ************************************************************/ -//#define CONFIG_USBOTG +/* Configuration ************************************************************/ #ifndef CONFIG_USBDEV_EP0_MAXSIZE # define CONFIG_USBDEV_EP0_MAXSIZE 64 @@ -94,9 +91,6 @@ # undef CONFIG_KHCI_USBDEV_BDTDEBUG #endif -//#define CONFIG_KHCI_USBDEV_REGDEBUG -//#define CONFIG_KHCI_USBDEV_BDTDEBUG - /* Disable this logic because it is buggy. It works most of the time but * has some lurking issues that keep this higher performance solution from * being usable. @@ -110,8 +104,6 @@ /* Interrupts ***************************************************************/ /* Initial interrupt sets */ -//#define CONFIG_USB_SOFINTS - #ifdef CONFIG_USB_SOFINTS # define USB_SOF_INTERRUPT USB_INT_SOFTOK #else @@ -122,29 +114,31 @@ USB_ERRSTAT_CRC16 | USB_ERRSTAT_DFN8 | USB_ERRSTAT_BTOERR | \ USB_ERRSTAT_BTSERR) -#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \ +#define NORMAL_INTERRUPTS (USB_INT_USBRST | USB_INT_ERROR | USB_SOF_INTERRUPT | \ USB_INT_TOKDNE | USB_INT_SLEEP | USB_INT_STALL) /* Endpoints ****************************************************************/ -#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */ +#define USB_STAT_ENDPT(n) ((n) << USB_STAT_ENDP_SHIFT) /* Endpoint n, n=0..15 */ -#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */ -#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */ +#define USB_STAT_ODD_ODD USB_STAT_ODD /* The last transaction was to the ODD BD bank */ +#define USB_STAT_ODD_EVEN 0 /* The last transaction was to the EVEN BD bank */ -#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */ -#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */ +#define USB_STAT_TX_IN USB_STAT_TX /* Last transaction was a transmit transfer (TX) */ +#define USB_STAT_TX_OUT 0 /* Last transaction was a receive transfer (RX) */ -#define KHCI_NENDPOINTS (16) +#define KHCI_NENDPOINTS (16) #define EP0 (0) -#define KHCI_ENDP_BIT(ep) (1 << (ep)) -#define KHCI_ENDP_ALLSET 0xffff +#define KHCI_ENDP_BIT(ep) (1 << (ep)) +#define KHCI_ENDP_ALLSET 0xffff + +#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) /* BDT Table Indexing. The BDT is addressed in the hardware as follows: * * Bits 9-31: These come the BDT address bits written into the BDTP3, - * BDTP2, and BDTP1 registers + * BDTP2, and BDTP1 registers * Bits 5-8: The endpoint number * Bit 4: Direction: * 1 = Transmit: SETUP/OUT for host, IN for function @@ -170,32 +164,32 @@ /* Packet sizes. We use a fixed 64 max packet size for all endpoint types */ -#define KHCI_MAXPACKET_SHIFT (6) -#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT)) +#define KHCI_MAXPACKET_SHIFT (6) +#define KHCI_MAXPACKET_SIZE (1 << (KHCI_MAXPACKET_SHIFT)) -#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE +#define KHCI_EP0MAXPACKET KHCI_MAXPACKET_SIZE /* Endpoint register initialization parameters */ -#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK|USB_ENDPT_EPTXEN|USB_ENDPT_EPRXEN) -#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) -#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) -#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) -#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS|USB_ENDPT_EPHSHK) -#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN|USB_ENDPT_EPCTLDIS) -#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN|USB_ENDPT_EPCTLDIS) +#define KHCI_EP_CONTROL (USB_ENDPT_EPHSHK | USB_ENDPT_EPTXEN | USB_ENDPT_EPRXEN) +#define KHCI_EP_BULKIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK) +#define KHCI_EP_BULKOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK) +#define KHCI_EP_INTIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK) +#define KHCI_EP_INTOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS | USB_ENDPT_EPHSHK) +#define KHCI_EP_ISOCIN (USB_ENDPT_EPTXEN | USB_ENDPT_EPCTLDIS) +#define KHCI_EP_ISOCOUT (USB_ENDPT_EPRXEN | USB_ENDPT_EPCTLDIS) /* USB-related masks */ -#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK) +#define REQRECIPIENT_MASK (USB_REQ_TYPE_MASK | USB_REQ_RECIPIENT_MASK) /* Request queue operations *************************************************/ -#define khci_rqempty(q) ((q)->head == NULL) -#define khci_rqhead(q) ((q)->head) -#define khci_rqtail(q) ((q)->tail) +#define khci_rqempty(q) ((q)->head == NULL) +#define khci_rqhead(q) ((q)->head) +#define khci_rqtail(q) ((q)->tail) -#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000) +#define RESTART_DELAY (150 * CLOCKS_PER_SEC / 1000) /* USB trace ****************************************************************/ /* Trace error codes */ @@ -266,47 +260,45 @@ #define KHCI_TRACEINTID_SUSPENDED 0x0023 #define KHCI_TRACEINTID_WAITRESET 0x0024 - - #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), //0001 - TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), //0002 - TRACE_STR(KHCI_TRACEINTID_DISPATCH ), //0003 - TRACE_STR(KHCI_TRACEINTID_EP0IN ), //0004 - TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), //0005 - TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), //0006 - TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), //0007 - TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), //0008 - TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), //0009 - TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), //000a - TRACE_STR(KHCI_TRACEINTID_EPINDONE ), //000b - TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), //000c - TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), //000d - TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), //000e - TRACE_STR(KHCI_TRACEINTID_SOF ), //000f - TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), //0010 - TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), //0011 - TRACE_STR(KHCI_TRACEINTID_GETSETIF ), //0012 - TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), //0013 - TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), //0014 - TRACE_STR(KHCI_TRACEINTID_TRNC ), //0015 - TRACE_STR(KHCI_TRACEINTID_TRNCS ), //0016 - TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), //0017 - TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), //0018 - TRACE_STR(KHCI_TRACEINTID_RESET ), //0019 - TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), //001a - TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), //001b - TRACE_STR(KHCI_TRACEINTID_IDLE ), //001c - TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), //001d - TRACE_STR(KHCI_TRACEINTID_WKUP ), //001e - TRACE_STR(KHCI_TRACEINTID_T1MSEC ), //001f - TRACE_STR(KHCI_TRACEINTID_OTGID ), //0020 - TRACE_STR(KHCI_TRACEINTID_STALL ), //0021 - TRACE_STR(KHCI_TRACEINTID_UERR ), //0022 - TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), //0023 - TRACE_STR(KHCI_TRACEINTID_WAITRESET ), //0024 + TRACE_STR(KHCI_TRACEINTID_CLEARFEATURE ), /* 0x0001 */ + TRACE_STR(KHCI_TRACEINTID_DEVGETSTATUS ), /* 0x0002 */ + TRACE_STR(KHCI_TRACEINTID_DISPATCH ), /* 0x0003 */ + TRACE_STR(KHCI_TRACEINTID_EP0IN ), /* 0x0004 */ + TRACE_STR(KHCI_TRACEINTID_EP0INDONE ), /* 0x0005 */ + TRACE_STR(KHCI_TRACEINTID_EP0OUTDONE ), /* 0x0006 */ + TRACE_STR(KHCI_TRACEINTID_EP0SETUPDONE ), /* 0x0007 */ + TRACE_STR(KHCI_TRACEINTID_EP0SETUPSETADDRESS ), /* 0x0008 */ + TRACE_STR(KHCI_TRACEINTID_EP0ADDRESSSET ), /* 0x0009 */ + TRACE_STR(KHCI_TRACEINTID_EPGETSTATUS ), /* 0x000a */ + TRACE_STR(KHCI_TRACEINTID_EPINDONE ), /* 0x000b */ + TRACE_STR(KHCI_TRACEINTID_EPINQEMPTY ), /* 0x000c */ + TRACE_STR(KHCI_TRACEINTID_EPOUTDONE ), /* 0x000d */ + TRACE_STR(KHCI_TRACEINTID_EPOUTQEMPTY ), /* 0x000e */ + TRACE_STR(KHCI_TRACEINTID_SOF ), /* 0x000f */ + TRACE_STR(KHCI_TRACEINTID_GETCONFIG ), /* 0x0010 */ + TRACE_STR(KHCI_TRACEINTID_GETSETDESC ), /* 0x0011 */ + TRACE_STR(KHCI_TRACEINTID_GETSETIF ), /* 0x0012 */ + TRACE_STR(KHCI_TRACEINTID_GETSTATUS ), /* 0x0013 */ + TRACE_STR(KHCI_TRACEINTID_IFGETSTATUS ), /* 0x0014 */ + TRACE_STR(KHCI_TRACEINTID_TRNC ), /* 0x0015 */ + TRACE_STR(KHCI_TRACEINTID_TRNCS ), /* 0x0016 */ + TRACE_STR(KHCI_TRACEINTID_INTERRUPT ), /* 0x0017 */ + TRACE_STR(KHCI_TRACEINTID_NOSTDREQ ), /* 0x0018 */ + TRACE_STR(KHCI_TRACEINTID_RESET ), /* 0x0019 */ + TRACE_STR(KHCI_TRACEINTID_SETCONFIG ), /* 0x001a */ + TRACE_STR(KHCI_TRACEINTID_SETFEATURE ), /* 0x001b */ + TRACE_STR(KHCI_TRACEINTID_IDLE ), /* 0x001c */ + TRACE_STR(KHCI_TRACEINTID_SYNCHFRAME ), /* 0x001d */ + TRACE_STR(KHCI_TRACEINTID_WKUP ), /* 0x001e */ + TRACE_STR(KHCI_TRACEINTID_T1MSEC ), /* 0x001f */ + TRACE_STR(KHCI_TRACEINTID_OTGID ), /* 0x0020 */ + TRACE_STR(KHCI_TRACEINTID_STALL ), /* 0x0021 */ + TRACE_STR(KHCI_TRACEINTID_UERR ), /* 0x0022 */ + TRACE_STR(KHCI_TRACEINTID_SUSPENDED ), /* 0x0023 */ + TRACE_STR(KHCI_TRACEINTID_WAITRESET ), /* 0x0024 */ TRACE_STR_END }; #endif @@ -314,32 +306,32 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), //0001 - TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), //0002 - TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), //0003 - TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), //0004 - TRACE_STR(KHCI_TRACEERR_BADEPNO ), //0005 - TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), //0006 - TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), //0007 - TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), //0008 - TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), //0009 - TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), //000a - TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), //000b - TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), //000c - TRACE_STR(KHCI_TRACEERR_BINDFAILED ), //000d - TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), //000e - TRACE_STR(KHCI_TRACEERR_DRIVER ), //000f - TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), //0010 - TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), //0011 - TRACE_STR(KHCI_TRACEERR_EPDISABLED ), //0012 - TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), //0013 - TRACE_STR(KHCI_TRACEERR_EPRESERVE ), //0014 - TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), //0015 - TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), //0016 - TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), //0017 - TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), //0018 - TRACE_STR(KHCI_TRACEERR_REQABORTED ), //0019 - TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), //001a + TRACE_STR(KHCI_TRACEERR_ALLOCFAIL ), /* 0x0001 */ + TRACE_STR(KHCI_TRACEERR_BADCLEARFEATURE ), /* 0x0002 */ + TRACE_STR(KHCI_TRACEERR_BADDEVGETSTATUS ), /* 0x0003 */ + TRACE_STR(KHCI_TRACEERR_BADEPGETSTATUS ), /* 0x0004 */ + TRACE_STR(KHCI_TRACEERR_BADEPNO ), /* 0x0005 */ + TRACE_STR(KHCI_TRACEERR_BADEPTYPE ), /* 0x0006 */ + TRACE_STR(KHCI_TRACEERR_BADGETCONFIG ), /* 0x0007 */ + TRACE_STR(KHCI_TRACEERR_BADGETSETDESC ), /* 0x0008 */ + TRACE_STR(KHCI_TRACEERR_BADGETSTATUS ), /* 0x0009 */ + TRACE_STR(KHCI_TRACEERR_BADSETADDRESS ), /* 0x000a */ + TRACE_STR(KHCI_TRACEERR_BADSETCONFIG ), /* 0x000b */ + TRACE_STR(KHCI_TRACEERR_BADSETFEATURE ), /* 0x000c */ + TRACE_STR(KHCI_TRACEERR_BINDFAILED ), /* 0x000d */ + TRACE_STR(KHCI_TRACEERR_DISPATCHSTALL ), /* 0x000e */ + TRACE_STR(KHCI_TRACEERR_DRIVER ), /* 0x000f */ + TRACE_STR(KHCI_TRACEERR_DRIVERREGISTERED ), /* 0x0010 */ + TRACE_STR(KHCI_TRACEERR_EP0SETUPSTALLED ), /* 0x0011 */ + TRACE_STR(KHCI_TRACEERR_EPDISABLED ), /* 0x0012 */ + TRACE_STR(KHCI_TRACEERR_EPOUTNULLPACKET ), /* 0x0013 */ + TRACE_STR(KHCI_TRACEERR_EPRESERVE ), /* 0x0014 */ + TRACE_STR(KHCI_TRACEERR_INVALIDCTRLREQ ), /* 0x0015 */ + TRACE_STR(KHCI_TRACEERR_INVALIDPARMS ), /* 0x0016 */ + TRACE_STR(KHCI_TRACEERR_IRQREGISTRATION ), /* 0x0017 */ + TRACE_STR(KHCI_TRACEERR_NOTCONFIGURED ), /* 0x0018 */ + TRACE_STR(KHCI_TRACEERR_REQABORTED ), /* 0x0019 */ + TRACE_STR(KHCI_TRACEERR_INVALIDSTATE ), /* 0x001a */ TRACE_STR_END }; #endif @@ -451,21 +443,21 @@ union wb_u struct khci_req_s { - struct usbdev_req_s req; /* Standard USB request */ + struct usbdev_req_s req; /* Standard USB request */ #ifdef CONFIG_USBDEV_NOWRITEAHEAD - uint16_t inflight[1]; /* The number of bytes "in-flight" */ + uint16_t inflight[1]; /* The number of bytes "in-flight" */ #else - uint16_t inflight[2]; /* The number of bytes "in-flight" */ + uint16_t inflight[2]; /* The number of bytes "in-flight" */ #endif - struct khci_req_s *flink; /* Supports a singly linked list */ + struct khci_req_s *flink; /* Supports a singly linked list */ }; /* This structure represents the 'head' of a singly linked list of requests */ struct khci_queue_s { - struct khci_req_s *head; /* Head of the request queue */ - struct khci_req_s *tail; /* Tail of the request queue */ + struct khci_req_s *head; /* Head of the request queue */ + struct khci_req_s *tail; /* Tail of the request queue */ }; /* This is the internal representation of an endpoint */ @@ -477,18 +469,18 @@ struct khci_ep_s * to struct khci_ep_s. */ - struct usbdev_ep_s ep; /* Standard endpoint structure */ + struct usbdev_ep_s ep; /* Standard endpoint structure */ /* KHCI-specific fields */ - struct khci_usbdev_s *dev; /* Reference to private driver data */ - struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */ - struct khci_queue_s active; /* List of active requests for this endpoint */ - uint8_t stalled:1; /* true: Endpoint is stalled */ - uint8_t halted:1; /* true: Endpoint feature halted */ - uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */ - uint8_t txdata1:1; /* Data0/1 of next TX transfer */ - uint8_t rxdata1:1; /* Data0/1 of next RX transfer */ + struct khci_usbdev_s *dev; /* Reference to private driver data */ + struct khci_queue_s pend; /* List of pending (inactive) requests for this endpoint */ + struct khci_queue_s active; /* List of active requests for this endpoint */ + uint8_t stalled:1; /* true: Endpoint is stalled */ + uint8_t halted:1; /* true: Endpoint feature halted */ + uint8_t txnullpkt:1; /* Null packet needed at end of TX transfer */ + uint8_t txdata1:1; /* Data0/1 of next TX transfer */ + uint8_t rxdata1:1; /* Data0/1 of next RX transfer */ volatile struct usbotg_bdtentry_s *bdtin; /* BDT entry for the IN transaction */ volatile struct usbotg_bdtentry_s *bdtout; /* BDT entry for the OUT transaction */ }; @@ -508,21 +500,21 @@ struct khci_usbdev_s /* KHCI-specific fields */ - struct usb_ctrlreq_s ctrl; /* Last EP0 request */ - uint8_t devstate; /* Driver state (see enum khci_devstate_e) */ - uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t rwakeup:1; /* 1: Device supports remote wakeup */ - uint8_t attached:1; /* Device is attached to the host */ - uint8_t ep0done:1; /* EP0 OUT already prepared */ - uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */ - uint16_t epavail; /* Bitset of available endpoints */ - uint16_t epstalled; /* Bitset of stalled endpoints */ - WDOG_ID wdog; /* Supports the restart delay */ + struct usb_ctrlreq_s ctrl; /* Last EP0 request */ + uint8_t devstate; /* Driver state (see enum khci_devstate_e) */ + uint8_t ctrlstate; /* Control EP state (see enum khci_ctrlstate_e) */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t rwakeup:1; /* 1: Device supports remote wakeup */ + uint8_t attached:1; /* Device is attached to the host */ + uint8_t ep0done:1; /* EP0 OUT already prepared */ + uint8_t rxbusy:1; /* EP0 OUT data transfer in progress */ + uint16_t epavail; /* Bitset of available endpoints */ + uint16_t epstalled; /* Bitset of stalled endpoints */ + WDOG_ID wdog; /* Supports the restart delay */ /* The endpoint list */ - struct khci_ep_s eplist[KHCI_NENDPOINTS]; + struct khci_ep_s eplist[KHCI_NENDPOINTS]; }; /**************************************************************************** @@ -548,7 +540,7 @@ static struct khci_req_s *khci_remlast(struct khci_queue_s *queue); static void khci_addlast(struct khci_queue_s *queue, struct khci_req_s *req); static void khci_addfirst(struct khci_queue_s *queue, - struct khci_req_s *req); + struct khci_req_s *req); /* Request Helpers **********************************************************/ @@ -601,7 +593,7 @@ static inline struct khci_ep_s * khci_epreserve(struct khci_usbdev_s *priv, uint8_t epset); static inline void khci_epunreserve(struct khci_usbdev_s *priv, - struct khci_ep_s *privep); + struct khci_ep_s *privep); static inline bool khci_epreserved(struct khci_usbdev_s *priv, int epno); static void khci_ep0configure(struct khci_usbdev_s *priv); @@ -689,10 +681,6 @@ static const struct usbdev_ops_s g_devops = static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS] __attribute__ ((aligned(512))); -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Private Functions ****************************************************************************/ @@ -700,7 +688,8 @@ static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS] /**************************************************************************** * Register Operations ****************************************************************************/ -/**************************************************************************** + + /**************************************************************************** * Name: khci_getreg ****************************************************************************/ @@ -778,6 +767,7 @@ static void khci_putreg(uint32_t val, uint32_t addr) /**************************************************************************** * Request Helpers ****************************************************************************/ + /**************************************************************************** * Name: khci_remfirst ****************************************************************************/ @@ -867,6 +857,7 @@ static void khci_addfirst(struct khci_queue_s *queue, struct khci_req_s *req) { queue->tail = req; } + queue->head = req; } @@ -1781,6 +1772,7 @@ static void khci_cancelrequests(struct khci_ep_s *privep, int16_t result) /**************************************************************************** * Interrupt Level Processing ****************************************************************************/ + /**************************************************************************** * Name: khci_dispatchrequest ****************************************************************************/ @@ -1967,17 +1959,17 @@ static void khci_ep0rdcomplete(struct khci_usbdev_s *priv) static void khci_ep0setup(struct khci_usbdev_s *priv) { volatile struct usbotg_bdtentry_s *bdt; - struct khci_ep_s *ep0; - struct khci_ep_s *privep; - union wb_u value; - union wb_u index; - union wb_u len; - union wb_u response; - uint32_t regval; - bool dispatched = false; - uint8_t epno; - int nbytes = 0; /* Assume zero-length packet */ - int ret; + struct khci_ep_s *ep0; + struct khci_ep_s *privep; + union wb_u value; + union wb_u index; + union wb_u len; + union wb_u response; + uint32_t regval; + bool dispatched = false; + uint8_t epno; + int nbytes = 0; /* Assume zero-length packet */ + int ret; /* Cancel any pending requests. */ @@ -1989,9 +1981,9 @@ static void khci_ep0setup(struct khci_usbdev_s *priv) * beginning with DATA1. */ - ep0->stalled = false; - ep0->rxdata1 = 0; - ep0->txdata1 = 1; + ep0->stalled = false; + ep0->rxdata1 = 0; + ep0->txdata1 = 1; /* Initialize for the SETUP */ @@ -2760,9 +2752,7 @@ static int khci_interrupt(int irq, void *context) usbir = khci_getreg(KINETIS_USB0_ISTAT) & khci_getreg(KINETIS_USB0_INTEN); otgir = khci_getreg(KINETIS_USB0_OTGISTAT) & khci_getreg(KINETIS_USB0_OTGICR); -// ulldbg("Interrupt: ISTAT %04x\n", khci_getreg(KINETIS_USB0_ISTAT)); -// ulldbg("Interrupt: OTGISTAT %04x\n", khci_getreg(KINETIS_USB0_OTGISTAT)); -// ulldbg("Interrupt: ERRSTAT %04x\n", khci_getreg(KINETIS_USB0_ERRSTAT)); + usbtrace(TRACE_INTENTRY(KHCI_TRACEINTID_INTERRUPT), usbir | otgir); #ifdef CONFIG_USBOTG @@ -2995,7 +2985,6 @@ x */ interrupt_exit: - //up_clrpend_irq(KINETIS_IRQ_USBOTG); kinetis_clrpend(KINETIS_IRQ_USBOTG); usbtrace(TRACE_INTEXIT(KHCI_TRACEINTID_INTERRUPT), usbir | otgir); return OK; @@ -3227,6 +3216,7 @@ static void khci_ep0configure(struct khci_usbdev_s *priv) /**************************************************************************** * Endpoint operations ****************************************************************************/ + /**************************************************************************** * Name: khci_epconfigure ****************************************************************************/ @@ -3422,6 +3412,7 @@ static struct usbdev_req_s *khci_epallocreq(struct usbdev_ep_s *ep) return NULL; } #endif + usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); privreq = (struct khci_req_s *)kmm_malloc(sizeof(struct khci_req_s)); @@ -3450,6 +3441,7 @@ static void khci_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) return; } #endif + usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); kmm_free(privreq); @@ -4026,11 +4018,9 @@ static void khci_attach(struct khci_usbdev_s *priv) /* Initialize registers to known states. */ - //khci_putreg(0, KINETIS_USB0_CTL); - #if 1 khci_putreg(0x1,KINETIS_USB0_CTL); - khci_putreg(0,KINETIS_USB0_USBCTRL); + khci_putreg(0,KINETIS_USB0_USBCTRL); #endif /* Enable interrupts at the USB controller */ @@ -4221,6 +4211,7 @@ static void khci_hwreset(struct khci_usbdev_s *priv) #define USB_FLASH_ACCESS #ifdef USB_FLASH_ACCESS /* Allow USBOTG-FS Controller to Read from FLASH */ + regval = getreg32(KINETIS_FMC_PFAPR); regval &= ~(FMC_PFAPR_M4AP_MASK); regval |= (FMC_PFAPR_RDONLY << FMC_PFAPR_M4AP_SHIFT); @@ -4231,13 +4222,15 @@ static void khci_hwreset(struct khci_usbdev_s *priv) memset((void *)g_bdt, 0, sizeof(g_bdt)); - /* Soft reset the USB Module*/ + /* Soft reset the USB Module */ + regval = khci_getreg(KINETIS_USB0_USBTRC0); regval |= USB_USBTRC0_USBRESET; khci_putreg(regval,KINETIS_USB0_USBTRC0); - //is this really necessary? - while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET); + /* Is this really necessary? */ + + while (khci_getreg(KINETIS_USB0_USBTRC0) & USB_USBTRC0_USBRESET); /* Set the address of the buffer descriptor table (BDT) * @@ -4245,7 +4238,7 @@ static void khci_hwreset(struct khci_usbdev_s *priv) * BDTP2: Bit 0-7: Bits 16-23 of the BDT base address * BDTP3: Bit 0-7: Bits 24-31 of the BDT base address */ - + khci_putreg((uint8_t)((uint32_t)g_bdt >> 24), KINETIS_USB0_BDTPAGE3); khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2); khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1); @@ -4255,7 +4248,6 @@ static void khci_hwreset(struct khci_usbdev_s *priv) ulldbg("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2)); ulldbg("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1)); - /* Clear any pending interrupts */ khci_putreg(0xFF, KINETIS_USB0_ERRSTAT); @@ -4263,7 +4255,6 @@ static void khci_hwreset(struct khci_usbdev_s *priv) khci_putreg(0xFF,KINETIS_USB0_OTGISTAT); #if 1 - /* Assert reset request to all of the Ping Pong buffer pointers. This * will reset all Even/Odd buffer pointers to the EVEN BD banks. */ @@ -4276,11 +4267,11 @@ static void khci_hwreset(struct khci_usbdev_s *priv) regval &= ~USB_CTL_ODDRST; khci_putreg(regval, KINETIS_USB0_CTL); - #endif #if 1 - /*Undocumented bit*/ + /* Undocumented bit */ + regval = khci_getreg(KINETIS_USB0_USBTRC0); regval |= 0x40; khci_putreg(regval,KINETIS_USB0_USBTRC0); @@ -4385,6 +4376,7 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv) /**************************************************************************** * Public Functions ****************************************************************************/ + /**************************************************************************** * Name: up_usbinitialize * @@ -4399,40 +4391,42 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv) * ****************************************************************************/ -#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) - void up_usbinitialize(void) { + struct khci_usbdev_s *priv = &g_usbdev; uint32_t regval; + /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers * easier. */ #if 1 - //1: Select clock source + /* 1: Select clock source */ + regval = getreg32(KINETIS_SIM_SOPT2); regval |= SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_USBSRC; putreg32(regval, KINETIS_SIM_SOPT2); regval = getreg32(KINETIS_SIM_CLKDIV2); #if defined(CONFIG_TEENSY_3X_OVERCLOCK) - regval = SIM_CLKDIV2_USBDIV(1); //(USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock + /* (USBFRAC + 0)/(USBDIV + 1) = (1 + 0)/(1 + 1) = 1/2 for 96Mhz clock */ + + regval = SIM_CLKDIV2_USBDIV(1); #else - //72Mhz + /* 72Mhz */ + regval = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC; #endif putreg32(regval, KINETIS_SIM_CLKDIV2); - - //2: Gate USB clock + + /* 2: Gate USB clock */ + regval = getreg32(KINETIS_SIM_SCGC4); regval |= SIM_SCGC4_USBOTG; putreg32(regval, KINETIS_SIM_SCGC4); - + #endif - - struct khci_usbdev_s *priv = &g_usbdev; - usbtrace(TRACE_DEVINIT, 0); /* Initialize the driver state structure */ @@ -4459,10 +4453,11 @@ void up_usbinitialize(void) (uint16_t)KINETIS_IRQ_USBOTG); up_usbuninitialize(); } -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - up_prioritize_irq(KINETIS_IRQ_USBOTG, 112); +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(KINETIS_IRQ_USBOTG, 112); #endif } @@ -4569,6 +4564,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) DEBUGASSERT(priv->devstate == DEVSTATE_DETACHED); khci_reset(priv); } + return ret; } diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h index 22a474a824..de53d51293 100644 --- a/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -1,7 +1,7 @@ /******************************************************************************************** * arch/arm/src/kinetis/kinetis_usbotg.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -363,10 +363,6 @@ struct usbotg_bdtentry_s }; #endif -/******************************************************************************************** - * Public Data - ********************************************************************************************/ - /******************************************************************************************** * Public Functions ********************************************************************************************/ diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c index 8512a35d33..c4d9e3fd44 100644 --- a/configs/teensy-3.x/src/k20_appinit.c +++ b/configs/teensy-3.x/src/k20_appinit.c @@ -78,7 +78,9 @@ int board_app_initialize(uintptr_t arg) /* Teensy is powered from usb and (bug?) only boots from being programmed, * so if usb is compiled in signal the controller driver that we're attached now. */ + khci_usbattach(); #endif + return OK; } diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c index a2b3c20ddf..d8b801193a 100644 --- a/configs/teensy-3.x/src/k20_usbdev.c +++ b/configs/teensy-3.x/src/k20_usbdev.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/teensy-3.x/src/k20_usbdev.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -56,13 +56,10 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + #define khci_getreg(addr) getreg8(addr) #define khci_putreg(val,addr) putreg8(val,addr) -#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) - -/************************************************************************************ - * Private Functions - ************************************************************************************/ +#define SIM_CLKDIV2_USBDIV(n) (uint32_t)(((n) & 0x07) << 1) /************************************************************************************ * Public Functions @@ -78,9 +75,6 @@ void kinetis_usbinitialize(void) { - uint32_t regval; - -// khci_usbattach(); } /************************************************************************************ @@ -99,16 +93,28 @@ int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable) { usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); uint32_t regval; -if (enable) -khci_putreg(USB_CONTROL_DPPULLUPNONOTG, KINETIS_USB0_CONTROL); -else -khci_putreg(0,KINETIS_USB0_CONTROL); + + if (enable) + { + khci_putreg(USB_CONTROL_DPPULLUPNONOTG, KINETIS_USB0_CONTROL); + } + else + { + khci_putreg(0,KINETIS_USB0_CONTROL); + } + #if 0 regval = khci_getreg(KINETIS_USB0_OTGCTL); - if (enable) - regval |= (1<<2); - else - regval &= ~(1<<2); + + if (enable) + { + regval |= (1 << 2); + } + else + { + regval &= ~(1 << 2); + } + khci_putreg(regval,KINETIS_USB0_OTGCTL); #endif diff --git a/configs/teensy-3.x/usbnsh/.config b/configs/teensy-3.x/usbnsh/.config deleted file mode 100644 index 0f0f54c88e..0000000000 --- a/configs/teensy-3.x/usbnsh/.config +++ /dev/null @@ -1,989 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -CONFIG_EXPERIMENTAL=y -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -CONFIG_INTELHEX_BINARY=y -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG=y -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_VERBOSE is not set - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_BINFMT is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set - -# -# OS Function Debug Options -# -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_LEDS is not set -# CONFIG_DEBUG_ANALOG is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_SPI is not set -# CONFIG_DEBUG_USB is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_SH is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -CONFIG_ARCH_CHIP_KINETIS=y -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -CONFIG_ARCH_CORTEXM4=y -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="kinetis" -# CONFIG_ARMV7M_USEBASEPRI is not set -CONFIG_ARCH_HAVE_FPU=y -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -CONFIG_ARM_HAVE_MPU_UNIFIED=y -# CONFIG_ARM_MPU is not set -# CONFIG_DEBUG_HARDFAULT is not set - -# -# ARMV7M Configuration Options -# -# CONFIG_ARMV7M_HAVE_ICACHE is not set -# CONFIG_ARMV7M_HAVE_DCACHE is not set -# CONFIG_ARMV7M_HAVE_ITCM is not set -# CONFIG_ARMV7M_HAVE_DTCM is not set -# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y -# CONFIG_ARMV7M_HAVE_STACKCHECK is not set -# CONFIG_ARMV7M_ITMSYSLOG is not set - -# -# Kinetis Configuration Options -# -# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set -# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set -# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set -# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set -# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set -# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set -# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set -# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set -CONFIG_ARCH_CHIP_MK20DX256VLH7=y -# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set -# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set -# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set -# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set -# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set -# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set -# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set -# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set -# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set -# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set -# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set -# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set -# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set -CONFIG_ARCH_FAMILY_K20=y -# CONFIG_ARCH_FAMILY_K40 is not set -# CONFIG_ARCH_FAMILY_K60 is not set - -# -# Kinetis Peripheral Support -# -# CONFIG_KINETIS_TRACE is not set -# CONFIG_KINETIS_FLEXBUS is not set -CONFIG_KINETIS_UART0=y -# CONFIG_KINETIS_UART1 is not set -# CONFIG_KINETIS_UART2 is not set -# CONFIG_KINETIS_UART3 is not set -# CONFIG_KINETIS_UART4 is not set -# CONFIG_KINETIS_UART5 is not set -# CONFIG_KINETIS_FLEXCAN0 is not set -# CONFIG_KINETIS_FLEXCAN1 is not set -# CONFIG_KINETIS_SPI0 is not set -# CONFIG_KINETIS_SPI1 is not set -# CONFIG_KINETIS_SPI2 is not set -# CONFIG_KINETIS_I2C0 is not set -# CONFIG_KINETIS_I2C1 is not set -# CONFIG_KINETIS_I2S is not set -# CONFIG_KINETIS_DAC0 is not set -# CONFIG_KINETIS_DAC1 is not set -# CONFIG_KINETIS_ADC0 is not set -# CONFIG_KINETIS_ADC1 is not set -# CONFIG_KINETIS_CMP is not set -# CONFIG_KINETIS_VREF is not set -# CONFIG_KINETIS_SDHC is not set -# CONFIG_KINETIS_FTM0 is not set -# CONFIG_KINETIS_FTM1 is not set -# CONFIG_KINETIS_FTM2 is not set -# CONFIG_KINETIS_LPTIMER is not set -# CONFIG_KINETIS_RTC is not set -# CONFIG_KINETIS_EWM is not set -# CONFIG_KINETIS_CMT is not set -CONFIG_KINETIS_USBOTG=y -# CONFIG_KINETIS_USBDCD is not set -# CONFIG_KINETIS_LLWU is not set -# CONFIG_KINETIS_TSI is not set -# CONFIG_KINETIS_FTFL is not set -# CONFIG_KINETIS_DMA is not set -# CONFIG_KINETIS_CRC is not set -# CONFIG_KINETIS_PDB is not set -# CONFIG_KINETIS_PIT is not set - -# -# Kinetis GPIO Interrupt Configuration -# -# CONFIG_GPIO_IRQ is not set - -# -# Kinetis UART Configuration -# -CONFIG_KINETIS_UARTFIFOS=y - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -CONFIG_ARCH_HAVE_MPU=y -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_USE_MPU is not set -# CONFIG_ARCH_IRQPRIO is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ARCH_USBDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -CONFIG_ARCH_HAVE_RAMFUNCS=y -CONFIG_ARCH_RAMFUNCS=y -CONFIG_ARCH_HAVE_RAMVECTORS=y -# CONFIG_ARCH_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=6024 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y -# CONFIG_ARCH_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x1fff8000 -CONFIG_RAM_SIZE=65536 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_TEENSY_3X=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="teensy-3.x" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -# CONFIG_TEENSY_3X_OVERCLOCK is not set -CONFIG_LIB_BOARDCTL=y -# CONFIG_BOARDCTL_RESET is not set -# CONFIG_BOARDCTL_UNIQUEID is not set -CONFIG_BOARDCTL_USBDEVCTRL=y -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=6 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=16 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=4 - -# -# Tasks and Scheduling -# -# CONFIG_SPINLOCK is not set -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -CONFIG_SCHED_WAITPID=y - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# POSIX Message Queue Options -# -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set -# CONFIG_LCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -CONFIG_SERIAL_REMOVABLE=y -# CONFIG_16550_UART is not set -# CONFIG_ARCH_HAVE_UART is not set -CONFIG_ARCH_HAVE_UART0=y -# CONFIG_ARCH_HAVE_UART1 is not set -# CONFIG_ARCH_HAVE_UART2 is not set -# CONFIG_ARCH_HAVE_UART3 is not set -# CONFIG_ARCH_HAVE_UART4 is not set -# CONFIG_ARCH_HAVE_UART5 is not set -# CONFIG_ARCH_HAVE_UART6 is not set -# CONFIG_ARCH_HAVE_UART7 is not set -# CONFIG_ARCH_HAVE_UART8 is not set -# CONFIG_ARCH_HAVE_SCI0 is not set -# CONFIG_ARCH_HAVE_SCI1 is not set -# CONFIG_ARCH_HAVE_USART0 is not set -# CONFIG_ARCH_HAVE_USART1 is not set -# CONFIG_ARCH_HAVE_USART2 is not set -# CONFIG_ARCH_HAVE_USART3 is not set -# CONFIG_ARCH_HAVE_USART4 is not set -# CONFIG_ARCH_HAVE_USART5 is not set -# CONFIG_ARCH_HAVE_USART6 is not set -# CONFIG_ARCH_HAVE_USART7 is not set -# CONFIG_ARCH_HAVE_USART8 is not set -# CONFIG_ARCH_HAVE_OTHER_UART is not set - -# -# USART Configuration -# -CONFIG_MCU_SERIAL=y -CONFIG_STANDARD_SERIAL=y -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_SERIAL_TIOCSERGSTRUCT is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_UART0_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# UART0 Configuration -# -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART0_2STOP=0 -# CONFIG_UART0_IFLOWCONTROL is not set -# CONFIG_UART0_OFLOWCONTROL is not set -# CONFIG_UART0_DMA is not set -CONFIG_USBDEV=y - -# -# USB Device Controller Driver Options -# -# CONFIG_USBDEV_ISOCHRONOUS is not set -CONFIG_USBDEV_DUALSPEED=y -CONFIG_USBDEV_SELFPOWERED=y -# CONFIG_USBDEV_BUSPOWERED is not set -CONFIG_USBDEV_MAXPOWER=100 -# CONFIG_USBDEV_DMA is not set -# CONFIG_ARCH_USBDEV_STALLQUEUE is not set -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=128 -CONFIG_USBDEV_TRACE_INITIALIDSET=y - -# -# USB Device Class Driver Options -# -# CONFIG_USBDEV_COMPOSITE is not set -# CONFIG_PL2303 is not set -CONFIG_CDCACM=y -# CONFIG_CDCACM_CONSOLE is not set -# CONFIG_CDCACM_IFLOWCONTROL is not set -CONFIG_CDCACM_EP0MAXPACKET=64 -CONFIG_CDCACM_EPINTIN=1 -CONFIG_CDCACM_EPINTIN_FSSIZE=64 -CONFIG_CDCACM_EPINTIN_HSSIZE=64 -CONFIG_CDCACM_EPBULKOUT=3 -CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 -CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 -CONFIG_CDCACM_EPBULKIN=2 -CONFIG_CDCACM_EPBULKIN_FSSIZE=64 -CONFIG_CDCACM_EPBULKIN_HSSIZE=512 -CONFIG_CDCACM_NRDREQS=4 -CONFIG_CDCACM_NWRREQS=4 -CONFIG_CDCACM_BULKIN_REQLEN=768 -CONFIG_CDCACM_RXBUFSIZE=513 -CONFIG_CDCACM_TXBUFSIZE=769 -CONFIG_CDCACM_VENDORID=0x0525 -CONFIG_CDCACM_PRODUCTID=0xa4a7 -CONFIG_CDCACM_VENDORSTR="NuttX" -CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" -# CONFIG_USBMSC is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_CONSOLE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -CONFIG_FS_MQUEUE_MPATH="/var/mqueue" -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# System Logging -# -# CONFIG_SYSLOG is not set -# CONFIG_SYSLOG_TIMESTAMP is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# -# CONFIG_WIRELESS is not set - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=64 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_CMDPARMS is not set -CONFIG_NSH_MAXARGUMENTS=6 -# CONFIG_NSH_ARGCAT is not set -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -# CONFIG_NSH_CMDOPT_DF_H is not set -CONFIG_NSH_CODECS_BUFSIZE=128 -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_NSH_FILEIOSIZE=512 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -CONFIG_NSH_USBCONSOLE=y -CONFIG_NSH_USBCONDEV="/dev/ttyACM0" -CONFIG_USBDEV_MINOR=0 - -# -# USB Device Trace Support -# -# CONFIG_NSH_USBDEV_TRACE is not set -CONFIG_NSH_ARCHINIT=y -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set -CONFIG_SYSTEM_HEXED=y -CONFIG_SYSTEM_HEXED_STACKSIZE=2048 -CONFIG_SYSTEM_HEXED_PRIORITY=100 -CONFIG_SYSTEM_RAMTEST=y -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_READLINE_MAX_BUILTINS=64 -CONFIG_READLINE_MAX_EXTCMDS=64 -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_READLINE_CMD_HISTORY_LINELEN=80 -CONFIG_READLINE_CMD_HISTORY_LEN=16 -# CONFIG_SYSTEM_SDCARD is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_VI is not set -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_CDCACM_DEVMINOR=0 -# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set -# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set -# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set -# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set -# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -CONFIG_SYSTEM_USBMONITOR=y -CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 -CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 -CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 -CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y -CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y -CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y -CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y -CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/teensy-3.x/usbnsh/Make.defs b/configs/teensy-3.x/usbnsh/Make.defs index 597d2e8cf3..e750c7b570 100644 --- a/configs/teensy-3.x/usbnsh/Make.defs +++ b/configs/teensy-3.x/usbnsh/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # configs/teensy-3.1/nsh/Make.defs # -# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -114,4 +114,3 @@ HOSTCC = gcc HOSTINCLUDES = -I. HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe HOSTLDFLAGS = - diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index 0f0f54c88e..1e750e8e6f 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -42,36 +42,11 @@ CONFIG_RAW_BINARY=y # # Debug Options # -CONFIG_DEBUG=y +# CONFIG_DEBUG is not set # CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_VERBOSE is not set - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_BINFMT is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set - -# -# OS Function Debug Options -# -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_LEDS is not set -# CONFIG_DEBUG_ANALOG is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_SPI is not set -# CONFIG_DEBUG_USB is not set CONFIG_ARCH_HAVE_STACKCHECK=y # CONFIG_STACK_COLORATION is not set -CONFIG_DEBUG_SYMBOLS=y +# CONFIG_DEBUG_SYMBOLS is not set CONFIG_ARCH_HAVE_CUSTOMOPT=y # CONFIG_DEBUG_NOOPT is not set # CONFIG_DEBUG_CUSTOMOPT is not set @@ -142,6 +117,8 @@ CONFIG_ARCH_CORTEXM4=y # CONFIG_ARCH_CORTEXR7F is not set CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="kinetis" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y # CONFIG_ARMV7M_USEBASEPRI is not set CONFIG_ARCH_HAVE_FPU=y # CONFIG_ARCH_HAVE_DPFPU is not set @@ -149,7 +126,6 @@ CONFIG_ARCH_HAVE_FPU=y # CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y # CONFIG_ARM_MPU is not set -# CONFIG_DEBUG_HARDFAULT is not set # # ARMV7M Configuration Options @@ -158,6 +134,7 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y # CONFIG_ARMV7M_HAVE_DCACHE is not set # CONFIG_ARMV7M_HAVE_ITCM is not set # CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set @@ -480,7 +457,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set # # LED Support @@ -501,38 +483,33 @@ CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y # CONFIG_16550_UART is not set -# CONFIG_ARCH_HAVE_UART is not set -CONFIG_ARCH_HAVE_UART0=y -# CONFIG_ARCH_HAVE_UART1 is not set -# CONFIG_ARCH_HAVE_UART2 is not set -# CONFIG_ARCH_HAVE_UART3 is not set -# CONFIG_ARCH_HAVE_UART4 is not set -# CONFIG_ARCH_HAVE_UART5 is not set -# CONFIG_ARCH_HAVE_UART6 is not set -# CONFIG_ARCH_HAVE_UART7 is not set -# CONFIG_ARCH_HAVE_UART8 is not set -# CONFIG_ARCH_HAVE_SCI0 is not set -# CONFIG_ARCH_HAVE_SCI1 is not set -# CONFIG_ARCH_HAVE_USART0 is not set -# CONFIG_ARCH_HAVE_USART1 is not set -# CONFIG_ARCH_HAVE_USART2 is not set -# CONFIG_ARCH_HAVE_USART3 is not set -# CONFIG_ARCH_HAVE_USART4 is not set -# CONFIG_ARCH_HAVE_USART5 is not set -# CONFIG_ARCH_HAVE_USART6 is not set -# CONFIG_ARCH_HAVE_USART7 is not set -# CONFIG_ARCH_HAVE_USART8 is not set -# CONFIG_ARCH_HAVE_OTHER_UART is not set - -# -# USART Configuration -# +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set -# CONFIG_SERIAL_TIOCSERGSTRUCT is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_UART0_SERIAL_CONSOLE=y # CONFIG_OTHER_SERIAL_CONSOLE is not set @@ -755,10 +732,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_FTPC is not set # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_MEDIA is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set @@ -767,17 +744,17 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set # CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -785,17 +762,17 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_SERIALRX is not set # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_WEBSERVER is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set # # File System Utilities @@ -817,8 +794,8 @@ CONFIG_EXAMPLES_NSH=y # Interpreters # # CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_PCODE is not set # # FreeModBus @@ -829,6 +806,7 @@ CONFIG_EXAMPLES_NSH=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -948,14 +926,21 @@ CONFIG_NSH_ARCHINIT=y # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_FREE is not set +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=0 +# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set +# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set +# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set +# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set +# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_HEX2BIN is not set CONFIG_SYSTEM_HEXED=y CONFIG_SYSTEM_HEXED_STACKSIZE=2048 CONFIG_SYSTEM_HEXED_PRIORITY=100 +# CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y CONFIG_READLINE_HAVE_EXTMATCH=y CONFIG_SYSTEM_READLINE=y @@ -966,16 +951,7 @@ CONFIG_READLINE_MAX_EXTCMDS=64 CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_CMD_HISTORY_LINELEN=80 CONFIG_READLINE_CMD_HISTORY_LEN=16 -# CONFIG_SYSTEM_SDCARD is not set # CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_VI is not set -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_CDCACM_DEVMINOR=0 -# CONFIG_SYSTEM_CDCACM_TRACEINIT is not set -# CONFIG_SYSTEM_CDCACM_TRACECLASS is not set -# CONFIG_SYSTEM_CDCACM_TRACETRANSFERS is not set -# CONFIG_SYSTEM_CDCACM_TRACECONTROLLER is not set -# CONFIG_SYSTEM_CDCACM_TRACEINTERRUPTS is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_USBMONITOR=y CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 @@ -986,4 +962,5 @@ CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y +# CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/teensy-3.x/usbnsh/setenv.sh b/configs/teensy-3.x/usbnsh/setenv.sh index e96a2ff345..dedab5191e 100755 --- a/configs/teensy-3.x/usbnsh/setenv.sh +++ b/configs/teensy-3.x/usbnsh/setenv.sh @@ -1,7 +1,7 @@ #!/bin/bash # configs/teensy-3.1/nsh/setenv.sh # -# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -62,13 +62,9 @@ fi # You can this free toolchain here https://launchpad.net/gcc-arm-embedded export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" # This is the Cygwin path to the location where I build the buildroot # toolchain. From 3fc7b6f0e5875efcf92359541ecebaf234f630ae Mon Sep 17 00:00:00 2001 From: Konstantin Berezenko Date: Mon, 6 Jun 2016 12:29:24 -0700 Subject: [PATCH 06/18] Add stm32f105r support --- arch/arm/include/stm32/chip.h | 37 +++ arch/arm/src/stm32/Kconfig | 10 + arch/arm/src/stm32/chip.h | 3 + arch/arm/src/stm32/chip/stm32f105r_pinmap.h | 328 ++++++++++++++++++++ arch/arm/src/stm32/chip/stm32f105v_pinmap.h | 38 --- 5 files changed, 378 insertions(+), 38 deletions(-) create mode 100644 arch/arm/src/stm32/chip/stm32f105r_pinmap.h diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index 0a920ccee0..e476bff892 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -903,6 +903,43 @@ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ +# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */ +# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */ +# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + #elif defined(CONFIG_ARCH_CHIP_STM32F107VC) # undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */ # undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */ diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index c871fdf30c..a9b89773ea 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -484,6 +484,16 @@ config ARCH_CHIP_STM32F105VB select STM32_HAVE_I2C2 select STM32_HAVE_TIM4 +config ARCH_CHIP_STM32F105RB + bool "STM32F105RB" + select ARCH_CORTEXM3 + select STM32_STM32F10XX + select STM32_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + config ARCH_CHIP_STM32F107VC bool "STM32F107VC" select ARCH_CORTEXM3 diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h index bba330edfa..4542a3885f 100644 --- a/arch/arm/src/stm32/chip.h +++ b/arch/arm/src/stm32/chip.h @@ -109,6 +109,9 @@ # elif defined(CONFIG_ARCH_CHIP_STM32F105VB) # include "chip/stm32f105v_pinmap.h" +# elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# include "chip/stm32f105r_pinmap.h" + # elif defined(CONFIG_ARCH_CHIP_STM32F107VC) # include "chip/stm32f107v_pinmap.h" # else diff --git a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h new file mode 100644 index 0000000000..ffd3ef35c4 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f105r_pinmap.h @@ -0,0 +1,328 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f105r_pinmap.h + * + * Copyright (C) 2009, 2011, 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Alternate Pin Functions: */ + +#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1) + +#if defined(CONFIG_STM32_CAN1_REMAP1) +# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8) +# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9) +#else +# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11) +# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) +#endif + +#if defined(CONFIG_STM32_CAN2_REMAP) +# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5) +# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +#else +# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12) +# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13) +#endif + +#if 0 /* Needs further investigation */ +#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5) +#endif + +#if defined(CONFIG_STM32_I2C1_REMAP) +# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8) +# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9) +#else +# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7) +#endif +#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5) + +#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11) +#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13) +#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12) + +#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) + +#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10) +#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) +#define GPIO_OTGFS_VBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) + +#if defined(CONFIG_STM32_SPI1_REMAP) +# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15) +# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4) +# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5) +#else +# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4) +# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5) +# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6) +# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7) +#endif + +#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12) +#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13) +#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15) + +#if defined(CONFIG_STM32_SPI3_REMAP) +# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4) +# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10) +# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11) +# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12) +#else +# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15) +# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4) +# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5) +#endif + +#if 0 /* Needs further investigation */ +#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13) +#endif + +#if defined(CONFIG_STM32_TIM1_PARTIAL_REMAP) +# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12) +# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8) +# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) +# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9) +# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) +# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10) +# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11) +# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11) +# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6) +# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7) +# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0) +# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1) +#else +# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12) +# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8) +# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) +# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9) +# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) +# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10) +# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11) +# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11) +# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12) +# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13) +# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14) +# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15) +#endif + +#if defined(CONFIG_STM32_TIM2_FULL_REMAP) +# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15) +# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15) +# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15) +# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3) +# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10) +# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10) +# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11) +# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11) +#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1) +# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15) +# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15) +# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15) +# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3) +# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2) +# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2) +# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3) +# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3) +#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2) +# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0) +# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1) +# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1) +# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10) +# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10) +# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11) +# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11) +#else +# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0) +# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1) +# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1) +# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2) +# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2) +# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3) +# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3) +#endif + +#if defined(CONFIG_STM32_TIM3_FULL_REMAP) +# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6) +# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6) +# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7) +# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7) +# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8) +# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8) +# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9) +# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9) +#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP) +# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4) +# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4) +# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5) +# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5) +# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0) +# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0) +# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1) +# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1) +#else +# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6) +# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6) +# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7) +# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7) +# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0) +# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0) +# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1) +# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1) +#endif +#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2) + +#define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3) + +#if 0 /* Needs further investigation */ +#if defined(CONFIG_STM32_TRACESWO_REMAP) +# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +#endif +#endif + +#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8) +#if defined(CONFIG_STM32_USART1_REMAP) +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +#else +# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9) +# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10) +#endif + +#define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4) + +#if defined(CONFIG_STM32_USART3_PARTIAL_REMAP) +# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10) +# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11) +# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12) +# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13) +# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14) +#else +# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10) +# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11) +# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12) +# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13) +# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14) +#endif + +#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11) +#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10) + +#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2) +#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12) + +#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0) + +/* Some GPIOs are accessible only as remapped, alternate functions */ + +#if 0 /* Needs further investigation */ +#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13) +#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14) +#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4) +#endif + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H */ diff --git a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h index 71ffe84648..5fd7029e2c 100644 --- a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f105v_pinmap.h @@ -91,44 +91,6 @@ #define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5) #endif -#if 0 /* Needs further investigation */ -#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1) -#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2) -#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3) -#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0) -#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1) - -#if defined(CONFIG_STM32_ETH_REMAP) -# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9) -# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10) -# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11) -# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12) -# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8) -#else -# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4) -# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5) -# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0) -# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1) -# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7) -#endif - -#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10) -#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3) -#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12) -#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13) -#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2) -#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8) -#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11) -#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5) -#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7) -#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1) -#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4) -#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5) -#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12) -#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13) -#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11) -#endif - #if defined(CONFIG_STM32_I2C1_REMAP) # define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8) # define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9) From 08fd09b8fe95bd51b2a5ed85c174bd6e0a26aedc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 6 Jun 2016 15:01:25 -0600 Subject: [PATCH 07/18] Update ChangeLog --- ChangeLog | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/ChangeLog b/ChangeLog index 36041eb279..9ca199d45d 100755 --- a/ChangeLog +++ b/ChangeLog @@ -11887,6 +11887,14 @@ violated the OS/application interface -- by calling flash_eraseall(). The old code can be found in the Obsoleted' repository (and a revised version can be found at apps/fsutils/flash_eraseall) (2016-06-03). + * arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per- + timer pre-scaler value. Add support for all timers (2016-6-03) + * drivers/lcd: Correct conditional compilation in ST7565 driver. From + Pierre-noel Bouteville (2016-6-03) + * arch/arm/src/stm32: Correct conditional compilation in STM32 timer + capture logic. From Pierre-noel Bouteville (2016-6-03) + * arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From + Pierre-noel Bouteville (2016-6-03) * arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d (phreakuencies) (2016-06-04) * arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove @@ -11896,11 +11904,15 @@ * arch/arm/src/stm32: Add the up_getc() function to STM32 in order to support the minnsh configuration. From Alan Carvalho de Assis (2016-06-04). - * arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per- - timer pre-scaler value. Add support for all timers (2016-6-03) - * drivers/lcd: Correct conditional compilation in ST7565 driver. From - Pierre-noel Bouteville (2016-6-03) - * arch/arm/src/stm32: Correct conditional compilation in STM32 timer - capture logic. From Pierre-noel Bouteville (2016-6-03) - * arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From - Pierre-noel Bouteville (2016-6-03) + * include/sys/boardctl.h: Needs to be usable with C++ files (2016-06-05). + * tools/tesbuild.sh will now build NxWM configurations (2016-06-05). + * arch/arm/src/stm32: In PWM driver, just update duty if frequency is + not changed and PSM started. This removeis glitch or blinking when + only duty is frequently changed. From Pierre-noel Bouteville (2016-06-05). + * arch/arm/src/kinetis: Add a USB device controller driver. Derived from + the pic32mx usb driver, which uses the same usb controller. From kfazz + (2016-06). + * configs/teensy-3.x: Add USB support and a usbnsh configuration. From + kfazz (2016-06). + * arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin + Berezenko (2016-06-06). From c939bbe47a962d8c906af910440b09148ab72447 Mon Sep 17 00:00:00 2001 From: Aleksandr Vyhovanec Date: Tue, 7 Jun 2016 06:56:19 -0600 Subject: [PATCH 08/18] include/signal.h: Change type of SIG_IGN and related defines to _sa_handler_t --- ChangeLog | 3 +++ include/signal.h | 17 ++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/ChangeLog b/ChangeLog index 9ca199d45d..bbd62c3cc0 100755 --- a/ChangeLog +++ b/ChangeLog @@ -11916,3 +11916,6 @@ kfazz (2016-06). * arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin Berezenko (2016-06-06). + * include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to + _sa_handler_t. They type void does not work with the IAR toolchain. + From Aleksandr Vyhovanec (2016-06-07). diff --git a/include/signal.h b/include/signal.h index 12585c91e3..7cfc93b136 100644 --- a/include/signal.h +++ b/include/signal.h @@ -175,22 +175,21 @@ /* Special values of of sa_handler used by sigaction and sigset. They are all * treated like NULL for now. This is okay for SIG_DFL and SIG_IGN because * in NuttX, the default action for all signals is to ignore them. - * - * REVISIT: Need to distinguish the value of SIG_HOLD. It is needed in the - * implementation of sigset() but would need to be recognized in all signal - * functions that deal with signal disposition. */ -#define SIG_ERR ((CODE void *)-1) /* And error occurred */ -#define SIG_DFL ((CODE void *)0) /* Default is SIG_IGN for all signals */ -#define SIG_IGN ((CODE void *)0) /* Ignore the signal */ -#define SIG_HOLD ((CODE void *)1) /* Used only with sigset() */ +#define SIG_ERR ((_sa_handler_t)-1) /* And error occurred */ +#define SIG_DFL ((_sa_handler_t)0) /* Default is SIG_IGN for all signals */ +#define SIG_IGN ((_sa_handler_t)0) /* Ignore the signal */ +#define SIG_HOLD ((_sa_handler_t)1) /* Used only with sigset() */ /******************************************************************************** * Public Type Definitions ********************************************************************************/ -/* This defines a set of 32 signals (numbered 0 through 31). */ +/* This defines a set of 32 signals (numbered 0 through 31). + * REVISIT: Signal 0 is, however, not generally usable since that value has + * special meaning in some circumstances (e.g., kill()). + */ typedef uint32_t sigset_t; /* Bit set of 32 signals */ #define __SIGSET_T_DEFINED 1 From db470d8ffd859a7e45d9e1eea47918fbba5befff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 7 Jun 2016 08:42:42 -0600 Subject: [PATCH 09/18] Update README --- configs/stm32f103-minimum/README.txt | 87 ++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 96e7be7a79..4ddee1fb07 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -428,6 +428,49 @@ Where is one of the following: configuration. This configuration has far fewer features than the nsh configuration but is also a fraction of the size. + This minnsh configuration is a "proof-of-concept" and not very usable in + its current state. This configuration was created by disabling + everything possible INCLUDING file system support. Without file system + support, NuttX is pretty much crippled. Here are some of the + consequences of disabling the file system: + + - All features that depend on the file system are lost: device drivers, + mountpoints, message queues, named semaphores. + + - Without device drivers, you cannot interact with the RTOS using POSIX + interfaces. You would have to work with NuttX as with those other + tiny RTOSs: As a scheduler and a callable hardare abstraction layer + (HAL). + + - You cannot use any of the NuttX upper half device drivers since they + depend on the pseudo-file system and device nodes. You can, of + course, continue to use the lower half drivers either directly. Or, + perhaps, you could write some custom minnsh upper half drivers that + do not depend on a file system and expose a HAL interface. + + There is a special version of readline() the NSH uses when there is no + file system. It uses a special up_putc() to write data to the console + and a special function up_getc() to read data from the console. + + - The current up_getc() implementationsa are a kludge. They are + analogous to the up_putc() implementations: They directly poll the + hardware for serial availability, locking up all lower priority tasks + in the entire system while they poll. So a version of NSH that uses + up_getc() essentially blocks the system until a character is received. + + This, of course, could be fixed by creating a special, upper half + implementation of the interrupt-driven serial lower half (like + stm32_serial) that just supports single character console I/O + (perhaps called up_putc and up_getc?). The NSH could wait for serial + input without blocking the system. But then that would increase the + footprint too. + + So although the minnsh configurations are a good starting point for + making things small, they not are really very practical. Why might + you want a NuttX minnsh solution? Perhaps you have software that runs + on a family of chips including some very tiny MCUs. Then perhaps having + the RTOS compatibility would justify the loss of functionality? + STATUS: 2016-06-03: Using that config I got this: @@ -446,6 +489,50 @@ Where is one of the following: Mem: 18624 2328 16296 16296 nsh> + 2016-06-07: As another experiment, I tried enabling just (1) the file + system, (2) the console device, and (3) the upper half serial driver in + the minnsh configuration. With these changes, NSH should behave better + nd we preserve the device driver interface. I made the following + configuration changes: + + Enable the file system: + CONFIG_NFILE_DESCRIPTORS=5 + CONFIG_NFILE_STREAMS=5 + + Enable the console device: + CONFIG_DEV_CONSOLE=y + + Disable most new NSH commands. Some like 'ls' are really mandatory + with a file system: + CONFIG_NSH_DISABLE_xxx=y + + Enable the upper half serial driver: + CONFIG_SERIAL=y + CONFIG_STANDARD_SERIAL=y + + Enable the USART1 serial driver: + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_USART1_SERIAL_CONSOLE=y + + CONFIG_USART1_2STOP=0 + CONFIG_USART1_BAUD=115200 + CONFIG_USART1_BITS=8 + CONFIG_USART1_PARITY=0 + CONFIG_USART1_RXBUFSIZE=16 + CONFIG_USART1_TXBUFSIZE=16 + + The resulting code was bigger as expected: + + $ arm-none-eabi-size nuttx + text data bss dec hex filename + 20093 88 876 21057 5241 nuttx + + I am sure that other things that could be disabled were also drawn into + the build, so perhaps this could be reduced. But as a ballpark + estimate, it looks like the cost of basic file system and serial console + driver support is around 7+KB. + nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. This From d4c101d2cf475a8e1ae6cc3e739dd4b77e5627df Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 7 Jun 2016 11:28:46 -0600 Subject: [PATCH 10/18] Update README files --- configs/freedom-kl25z/README.txt | 80 +++++++++++++++++++++++++++ configs/freedom-kl26z/README.txt | 80 +++++++++++++++++++++++++++ configs/lpcxpresso-lpc1115/README.txt | 80 +++++++++++++++++++++++++++ configs/stm32f103-minimum/README.txt | 27 +++++++-- 4 files changed, 261 insertions(+), 6 deletions(-) diff --git a/configs/freedom-kl25z/README.txt b/configs/freedom-kl25z/README.txt index 23390503de..f2cc8e0c02 100644 --- a/configs/freedom-kl25z/README.txt +++ b/configs/freedom-kl25z/README.txt @@ -301,6 +301,86 @@ Where is one of the following: configuration. This configuration has far fewer features than the nsh configuration but is also a fraction of the size. + This minnsh configuration is a "proof-of-concept" and not very usable in + its current state. This configuration was created by disabling + everything possible INCLUDING file system support. Without file system + support, NuttX is pretty much crippled. Here are some of the + consequences of disabling the file system: + + - All features that depend on the file system are lost: device drivers, + mountpoints, message queues, named semaphores. + + - Without device drivers, you cannot interact with the RTOS using POSIX + interfaces. You would have to work with NuttX as with those other + tiny RTOSs: As a scheduler and a callable hardare abstraction layer + (HAL). + + - You cannot use any of the NuttX upper half device drivers since they + depend on the pseudo-file system and device nodes. You can, of + course, continue to use the lower half drivers either directly. Or, + perhaps, you could write some custom minnsh upper half drivers that + do not depend on a file system and expose a HAL interface. + + There is a special version of readline() the NSH uses when there is no + file system. It uses a special up_putc() to write data to the console + and a special function up_getc() to read data from the console. + + - The current up_getc() implementationsa are a kludge. They are + analogous to the up_putc() implementations: They directly poll the + hardware for serial availability, locking up all lower priority tasks + in the entire system while they poll. So a version of NSH that uses + up_getc() essentially blocks the system until a character is received. + + This, of course, could be fixed by creating a special, upper half + implementation of the interrupt-driven serial lower half (like + stm32_serial) that just supports single character console I/O + (perhaps called up_putc and up_getc?). The NSH could wait for serial + input without blocking the system. But then that would increase the + footprint too. + + So although the minnsh configurations are a good starting point for + making things small, they not are really very practical. Why might + you want a NuttX minnsh solution? Perhaps you have software that runs + on a family of chips including some very tiny MCUs. Then perhaps having + the RTOS compatibility would justify the loss of functionality? + + You can re-enable the file system and (true) serial console with + these settings: + + Enable the file system: + CONFIG_NFILE_DESCRIPTORS=5 + CONFIG_NFILE_STREAMS=5 + + Enable the console device: + CONFIG_DEV_CONSOLE=y + + Disable most new NSH commands. Some like 'ls' are really mandatory + with a file system: + CONFIG_NSH_DISABLE_xxx=y + + Enable the upper half serial driver: + CONFIG_SERIAL=y + CONFIG_STANDARD_SERIAL=y + + Enable the USART1 serial driver: + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_USART1_SERIAL_CONSOLE=y + + CONFIG_USART1_2STOP=0 + CONFIG_USART1_BAUD=115200 + CONFIG_USART1_BITS=8 + CONFIG_USART1_PARITY=0 + CONFIG_USART1_RXBUFSIZE=16 + CONFIG_USART1_TXBUFSIZE=16 + + With these changes, NSH should behave better and we preserve the device + driver interface. But this result in a total size increase of about + 7KB: That is about 5KB of additional OS support for the file system and + serial console PLUS about 2KB for the 'ls' command logic (including OS + support for opendir(), readdir(), closedir(), stat(), and probably other + things). + nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. The diff --git a/configs/freedom-kl26z/README.txt b/configs/freedom-kl26z/README.txt index 260ee1b6be..55f593c7d0 100644 --- a/configs/freedom-kl26z/README.txt +++ b/configs/freedom-kl26z/README.txt @@ -279,6 +279,86 @@ Where is one of the following: configuration. This configuration has far fewer features than the nsh configuration but is also a fraction of the size. + This minnsh configuration is a "proof-of-concept" and not very usable in + its current state. This configuration was created by disabling + everything possible INCLUDING file system support. Without file system + support, NuttX is pretty much crippled. Here are some of the + consequences of disabling the file system: + + - All features that depend on the file system are lost: device drivers, + mountpoints, message queues, named semaphores. + + - Without device drivers, you cannot interact with the RTOS using POSIX + interfaces. You would have to work with NuttX as with those other + tiny RTOSs: As a scheduler and a callable hardare abstraction layer + (HAL). + + - You cannot use any of the NuttX upper half device drivers since they + depend on the pseudo-file system and device nodes. You can, of + course, continue to use the lower half drivers either directly. Or, + perhaps, you could write some custom minnsh upper half drivers that + do not depend on a file system and expose a HAL interface. + + There is a special version of readline() the NSH uses when there is no + file system. It uses a special up_putc() to write data to the console + and a special function up_getc() to read data from the console. + + - The current up_getc() implementationsa are a kludge. They are + analogous to the up_putc() implementations: They directly poll the + hardware for serial availability, locking up all lower priority tasks + in the entire system while they poll. So a version of NSH that uses + up_getc() essentially blocks the system until a character is received. + + This, of course, could be fixed by creating a special, upper half + implementation of the interrupt-driven serial lower half (like + stm32_serial) that just supports single character console I/O + (perhaps called up_putc and up_getc?). The NSH could wait for serial + input without blocking the system. But then that would increase the + footprint too. + + So although the minnsh configurations are a good starting point for + making things small, they not are really very practical. Why might + you want a NuttX minnsh solution? Perhaps you have software that runs + on a family of chips including some very tiny MCUs. Then perhaps having + the RTOS compatibility would justify the loss of functionality? + + You can re-enable the file system and (true) serial console with + these settings: + + Enable the file system: + CONFIG_NFILE_DESCRIPTORS=5 + CONFIG_NFILE_STREAMS=5 + + Enable the console device: + CONFIG_DEV_CONSOLE=y + + Disable most new NSH commands. Some like 'ls' are really mandatory + with a file system: + CONFIG_NSH_DISABLE_xxx=y + + Enable the upper half serial driver: + CONFIG_SERIAL=y + CONFIG_STANDARD_SERIAL=y + + Enable the USART1 serial driver: + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_USART1_SERIAL_CONSOLE=y + + CONFIG_USART1_2STOP=0 + CONFIG_USART1_BAUD=115200 + CONFIG_USART1_BITS=8 + CONFIG_USART1_PARITY=0 + CONFIG_USART1_RXBUFSIZE=16 + CONFIG_USART1_TXBUFSIZE=16 + + With these changes, NSH should behave better and we preserve the device + driver interface. But this result in a total size increase of about + 7KB: That is about 5KB of additional OS support for the file system and + serial console PLUS about 2KB for the 'ls' command logic (including OS + support for opendir(), readdir(), closedir(), stat(), and probably other + things). + nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. The diff --git a/configs/lpcxpresso-lpc1115/README.txt b/configs/lpcxpresso-lpc1115/README.txt index 3a0beb1e7f..bfe29dc6d5 100644 --- a/configs/lpcxpresso-lpc1115/README.txt +++ b/configs/lpcxpresso-lpc1115/README.txt @@ -687,6 +687,86 @@ Where is one of the following: configuration. This configuration has far fewer features than the nsh configuration but is also a fraction of the size. + This minnsh configuration is a "proof-of-concept" and not very usable in + its current state. This configuration was created by disabling + everything possible INCLUDING file system support. Without file system + support, NuttX is pretty much crippled. Here are some of the + consequences of disabling the file system: + + - All features that depend on the file system are lost: device drivers, + mountpoints, message queues, named semaphores. + + - Without device drivers, you cannot interact with the RTOS using POSIX + interfaces. You would have to work with NuttX as with those other + tiny RTOSs: As a scheduler and a callable hardare abstraction layer + (HAL). + + - You cannot use any of the NuttX upper half device drivers since they + depend on the pseudo-file system and device nodes. You can, of + course, continue to use the lower half drivers either directly. Or, + perhaps, you could write some custom minnsh upper half drivers that + do not depend on a file system and expose a HAL interface. + + There is a special version of readline() the NSH uses when there is no + file system. It uses a special up_putc() to write data to the console + and a special function up_getc() to read data from the console. + + - The current up_getc() implementationsa are a kludge. They are + analogous to the up_putc() implementations: They directly poll the + hardware for serial availability, locking up all lower priority tasks + in the entire system while they poll. So a version of NSH that uses + up_getc() essentially blocks the system until a character is received. + + This, of course, could be fixed by creating a special, upper half + implementation of the interrupt-driven serial lower half (like + stm32_serial) that just supports single character console I/O + (perhaps called up_putc and up_getc?). The NSH could wait for serial + input without blocking the system. But then that would increase the + footprint too. + + So although the minnsh configurations are a good starting point for + making things small, they not are really very practical. Why might + you want a NuttX minnsh solution? Perhaps you have software that runs + on a family of chips including some very tiny MCUs. Then perhaps having + the RTOS compatibility would justify the loss of functionality? + + You can re-enable the file system and (true) serial console with + these settings: + + Enable the file system: + CONFIG_NFILE_DESCRIPTORS=5 + CONFIG_NFILE_STREAMS=5 + + Enable the console device: + CONFIG_DEV_CONSOLE=y + + Disable most new NSH commands. Some like 'ls' are really mandatory + with a file system: + CONFIG_NSH_DISABLE_xxx=y + + Enable the upper half serial driver: + CONFIG_SERIAL=y + CONFIG_STANDARD_SERIAL=y + + Enable the USART1 serial driver: + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_USART1_SERIAL_CONSOLE=y + + CONFIG_USART1_2STOP=0 + CONFIG_USART1_BAUD=115200 + CONFIG_USART1_BITS=8 + CONFIG_USART1_PARITY=0 + CONFIG_USART1_RXBUFSIZE=16 + CONFIG_USART1_TXBUFSIZE=16 + + With these changes, NSH should behave better and we preserve the device + driver interface. But this result in a total size increase of about + 7KB: That is about 5KB of additional OS support for the file system and + serial console PLUS about 2KB for the 'ls' command logic (including OS + support for opendir(), readdir(), closedir(), stat(), and probably other + things). + STATUS: 2015-6-10 The nuttx.bin minnsh firmware file size: diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 4ddee1fb07..4f8ff5849f 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -492,7 +492,7 @@ Where is one of the following: 2016-06-07: As another experiment, I tried enabling just (1) the file system, (2) the console device, and (3) the upper half serial driver in the minnsh configuration. With these changes, NSH should behave better - nd we preserve the device driver interface. I made the following + and we preserve the device driver interface. I made the following configuration changes: Enable the file system: @@ -525,13 +525,28 @@ Where is one of the following: The resulting code was bigger as expected: $ arm-none-eabi-size nuttx - text data bss dec hex filename - 20093 88 876 21057 5241 nuttx + text data bss dec hex filename + 19853 88 876 20817 5151 nuttx I am sure that other things that could be disabled were also drawn into - the build, so perhaps this could be reduced. But as a ballpark - estimate, it looks like the cost of basic file system and serial console - driver support is around 7+KB. + the build, so perhaps this could be reduced. This amounts to a size + increase of around 7KB. + + One major part of this size increase is due to the addition of the NSH + 'ls' command. Now, if I disable the 'ls' command, I get: + + $ arm-none-eabi-size nuttx + text data bss dec hex filename + 17804 80 864 18748 493c nuttx + + Or an increase of only 5.1 KB. This, of course, not only excludes the + 'ls' command logic, but also the things that were drawn into the link + when 'ls' was enabled: opendir(), readdir(), closedir(), stat(), and + probably other things. + + So I think we can say that the cost of the file system and true serial + console device was about 5 KB (primarily OS support) and the cost of + the NSH 'ls' command (including OS support) is about 2KB. nsh: --- From 44da2c0add3492cefcb7a3681e489210e43a710b Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 8 Jun 2016 07:52:19 -0600 Subject: [PATCH 11/18] Refactored configs/nucleo-144 sub-directories to support additional nucleo-144 board. Add support for the Nucleo-F767ZI board. --- ChangeLog | 3 + configs/Kconfig | 11 +- configs/README.txt | 9 +- configs/nucleo-144/Kconfig | 215 ++++ configs/nucleo-144/README.txt | 251 +++- configs/nucleo-144/f746-evalos/Make.defs | 114 ++ .../{evalos => f746-evalos}/defconfig | 0 .../{evalos => f746-evalos}/setenv.sh | 2 +- .../nucleo-144/{nsh => f746-nsh}/Make.defs | 7 +- .../nucleo-144/{nsh => f746-nsh}/defconfig | 147 ++- .../nucleo-144/{nsh => f746-nsh}/setenv.sh | 2 +- configs/nucleo-144/f767-evalos/Make.defs | 114 ++ configs/nucleo-144/f767-evalos/defconfig | 1047 +++++++++++++++++ configs/nucleo-144/f767-evalos/setenv.sh | 78 ++ .../nucleo-144/{evalos => f767-nsh}/Make.defs | 9 +- configs/nucleo-144/f767-nsh/defconfig | 1021 ++++++++++++++++ configs/nucleo-144/f767-nsh/setenv.sh | 77 ++ configs/nucleo-144/include/board.h | 176 +-- .../scripts/{flash.ld => f746-flash.ld} | 25 +- configs/nucleo-144/scripts/f767-flash.ld | 146 +++ configs/nucleo-144/src/Makefile | 11 +- configs/nucleo-144/src/nucleo-144.h | 145 ++- configs/nucleo-144/src/stm32_appinitialize.c | 51 +- configs/nucleo-144/src/stm32_autoleds.c | 132 ++- configs/nucleo-144/src/stm32_boot.c | 22 +- configs/nucleo-144/src/stm32_buttons.c | 12 +- configs/nucleo-144/src/stm32_dma_alloc.c | 117 ++ configs/nucleo-144/src/stm32_sdio.c | 176 +++ configs/nucleo-144/src/stm32_spi.c | 216 +++- configs/nucleo-144/src/stm32_userleds.c | 30 +- 30 files changed, 4077 insertions(+), 289 deletions(-) create mode 100644 configs/nucleo-144/f746-evalos/Make.defs rename configs/nucleo-144/{evalos => f746-evalos}/defconfig (100%) rename configs/nucleo-144/{evalos => f746-evalos}/setenv.sh (98%) rename configs/nucleo-144/{nsh => f746-nsh}/Make.defs (96%) rename configs/nucleo-144/{nsh => f746-nsh}/defconfig (82%) rename configs/nucleo-144/{nsh => f746-nsh}/setenv.sh (98%) create mode 100644 configs/nucleo-144/f767-evalos/Make.defs create mode 100644 configs/nucleo-144/f767-evalos/defconfig create mode 100644 configs/nucleo-144/f767-evalos/setenv.sh rename configs/nucleo-144/{evalos => f767-nsh}/Make.defs (96%) create mode 100644 configs/nucleo-144/f767-nsh/defconfig create mode 100644 configs/nucleo-144/f767-nsh/setenv.sh rename configs/nucleo-144/scripts/{flash.ld => f746-flash.ld} (83%) create mode 100644 configs/nucleo-144/scripts/f767-flash.ld create mode 100644 configs/nucleo-144/src/stm32_dma_alloc.c create mode 100644 configs/nucleo-144/src/stm32_sdio.c diff --git a/ChangeLog b/ChangeLog index bbd62c3cc0..b3ea24e379 100755 --- a/ChangeLog +++ b/ChangeLog @@ -11919,3 +11919,6 @@ * include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to _sa_handler_t. They type void does not work with the IAR toolchain. From Aleksandr Vyhovanec (2016-06-07). + * Refactoring configs/nucleo-144 sub-directories to support additional + nucleo-144 board. Add support for the Nucleo-F767ZI board. From David + Sidrane (2016-06-08). diff --git a/configs/Kconfig b/configs/Kconfig index c8169d0086..e4d6ec4e5f 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -649,14 +649,17 @@ config ARCH_BOARD_PIRELLI_DPL10 config ARCH_BOARD_NUCLEO_144 bool "STMicro NUCLEO-144" - depends on ARCH_CHIP_STM32F746 + depends on ARCH_CHIP_STM32F746 || ARCH_CHIP_STM32F767 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS ---help--- - STMicro Nucleo-144 development board featuring the STM32F746ZGT6U - MCU. The STM32F746ZGT6U is a 216MHz Cortex-M7 operation with 1024Kb Flash - memory and 300Kb SRAM. + STMicro Nucleo-144 development board family. Included support for (1) the + Nucleo-F767ZG board featuring the STM32F746ZGT6U MCU. The STM32F746ZGT6U + is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM. + And (2) the Nucleo-F746ZG board featuring the STM32F767ZIT6 MCU. The + STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory + and 512Kb SRAM. config ARCH_BOARD_NUCLEO_F303RE bool "STM32F303 Nucleo F303RE" diff --git a/configs/README.txt b/configs/README.txt index 9b1c8486ba..45f06d0fa0 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -393,9 +393,12 @@ configs/ntosd-dm320 NuttX 0.2.1 release. configs/nucleo-144 - STMicro Nucleo-144 development board featuring the STM32F746ZGT6U MCU. The - STM32F746ZGT6U is a 216MHz Cortex-M7 operation with 1024Kb Flash memory - and 300Kb SRAM. + STMicro Nucleo-144 development board family. Included support for (1) the + Nucleo-F767ZG board featuring the STM32F746ZGT6U MCU. The STM32F746ZGT6U + is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM. + And (2) the Nucleo-F746ZG board featuring the STM32F767ZIT6 MCU. The + STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory + and 512Kb SRAM. configs/nucleo-f4x1re STMicro ST Nucleo F401RE and F411RE boards. See diff --git a/configs/nucleo-144/Kconfig b/configs/nucleo-144/Kconfig index 57585efaff..96427a9a5e 100644 --- a/configs/nucleo-144/Kconfig +++ b/configs/nucleo-144/Kconfig @@ -5,4 +5,219 @@ if ARCH_BOARD_NUCLEO_144 +choice + prompt "Select Console wiring." + default NUCLEO_ARDUINO + ---help--- + Select where you will connect the console. + + Virtual COM Port: + + Advantage: Use the ST-Link as a console. No Extra wiring + neded. + + Disdvantage: Not the best choice for initanl bring up. + + ARDUINO Connector: + + Advantage: You have a shield so it is + easy. + + Disdvantage: You loose the use of the + other functions on PC6, PC7 + + STM32F7 + ARDUIONO FUNCTION GPIO + -- ----- --------- ---- + DO RX USART6_RX PG9 + D1 TX USART6_TX PG14 + -- ----- --------- --- + + OR + + Morpho Connector: + + STM32F7 + MORPHO FUNCTION GPIO + -------- --------- ----- + CN12-64 USART8_RX PE0 + CN11-61 USART8_TX PE1 + -------- --------- ----- + +config NUCLEO_CONSOLE_ARDUINO + bool "ARDUINO Connector" + select STM32F7_USART6 + select USART6_SERIALDRIVER + select USART6_SERIAL_CONSOLE + +config NUCLEO_CONSOLE_VIRTUAL + bool "Virtual Comport" + select STM32F7_USART3 + select USART3_SERIALDRIVER + select USART3_SERIAL_CONSOLE + +config NUCLEO_CONSOLE_MORPHO + bool "Morpho Connector" + select STM32F7_UART8 + select UART8_SERIALDRIVER + select UART8_SERIAL_CONSOLE + +config NUCLEO_CONSOLE_NONE + bool "No Console" + +endchoice # "Select Console wiring" + +config NUCLEO_SPI_TEST + bool "Enable SPI test" + default n + ---help--- + Enable Spi test - initalize and configure SPI to send + NUCLEO_SPI_TEST_MESSAGE text. The text is sent on the + selected SPI Buses with the configured parameters. + Note the CS lines will not be asserted. + +if NUCLEO_SPI_TEST + +config NUCLEO_SPI_TEST_MESSAGE + string "Text to Send on SPI Bus(es)" + default "Hello World" + depends on NUCLEO_SPI_TEST + ---help--- + Text to sent on SPI bus(es) + +config NUCLEO_SPI1_TEST + bool "Test SPI bus 1" + default n + depends on NUCLEO_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 1 + +if NUCLEO_SPI1_TEST + +config NUCLEO_SPI1_TEST_FREQ + int "SPI 1 Clock Freq in Hz" + default 1000000 + depends on NUCLEO_SPI1_TEST + ---help--- + Sets SPI 1 Clock Freq + +config NUCLEO_SPI1_TEST_BITS + int "SPI 1 number of bits" + default 8 + depends on NUCLEO_SPI1_TEST + ---help--- + Sets SPI 1 bit length + +choice + prompt "SPI BUS 1 Clock Mode" + default NUCLEO_SPI1_TEST_MODE3 + ---help--- + Sets SPI 1 clock mode + +config NUCLEO_SPI1_TEST_MODE0 + bool "CPOL=0 CHPHA=0" + +config NUCLEO_SPI1_TEST_MODE1 + bool "CPOL=0 CHPHA=1" + +config NUCLEO_SPI1_TEST_MODE2 + bool "CPOL=1 CHPHA=0" + +config NUCLEO_SPI1_TEST_MODE3 + bool "CPOL=1 CHPHA=1" + +endchoice # "SPI BUS 1 Clock Mode" + +endif # NUCLEO_SPI1_TEST + +config NUCLEO_SPI2_TEST + bool "Test SPI bus 2" + default n + depends on NUCLEO_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 2 + +if NUCLEO_SPI2_TEST + +config NUCLEO_SPI2_TEST_FREQ + int "SPI 2 Clock Freq in Hz" + default 12000000 + depends on NUCLEO_SPI2_TEST + ---help--- + Sets SPI 2 Clock Freq + +config NUCLEO_SPI2_TEST_BITS + int "SPI 2 number of bits" + default 8 + depends on NUCLEO_SPI2_TEST + ---help--- + Sets SPI 2 bit length + +choice + prompt "SPI BUS 2 Clock Mode" + default NUCLEO_SPI2_TEST_MODE3 + ---help--- + Sets SPI 2 clock mode + +config NUCLEO_SPI2_TEST_MODE0 + bool "CPOL=0 CHPHA=0" + +config NUCLEO_SPI2_TEST_MODE1 + bool "CPOL=0 CHPHA=1" + +config NUCLEO_SPI2_TEST_MODE2 + bool "CPOL=1 CHPHA=0" + +config NUCLEO_SPI2_TEST_MODE3 + bool "CPOL=1 CHPHA=1" + +endchoice # "SPI BUS 2 Clock Mode" + +endif # NUCLEO_SPI2_TEST + +config NUCLEO_SPI3_TEST + bool "Test SPI bus 3" + default n + depends on NUCLEO_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 3 + +if NUCLEO_SPI3_TEST + +config NUCLEO_SPI3_TEST_FREQ + int "SPI 3 Clock Freq in Hz" + default 40000000 + depends on NUCLEO_SPI3_TEST + ---help--- + Sets SPI 3 Clock Freq + +config NUCLEO_SPI3_TEST_BITS + int "SPI 3 number of bits" + default 8 + depends on NUCLEO_SPI3_TEST + ---help--- + Sets SPI 3 bit length + +choice + prompt "SPI BUS 3 Clock Mode" + default NUCLEO_SPI3_TEST_MODE3 + ---help--- + Sets SPI 3 clock mode + +config NUCLEO_SPI3_TEST_MODE0 + bool "CPOL=0 CHPHA=0" + +config NUCLEO_SPI3_TEST_MODE1 + bool "CPOL=0 CHPHA=1" + +config NUCLEO_SPI3_TEST_MODE2 + bool "CPOL=1 CHPHA=0" + +config NUCLEO_SPI3_TEST_MODE3 + bool "CPOL=1 CHPHA=1" + +endchoice # "SPI BUS 3 Clock Mode" + +endif # NUCLEO_SPI3_TEST +endif # NUCLEO_SPI_TEST endif # ARCH_BOARD_NUCLEO_144 diff --git a/configs/nucleo-144/README.txt b/configs/nucleo-144/README.txt index e99cd427de..1a5d6f4b3b 100644 --- a/configs/nucleo-144/README.txt +++ b/configs/nucleo-144/README.txt @@ -11,6 +11,7 @@ Contents - Nucleo-144 Boards - Nucleo F746ZG + - Nucleo F767ZI - Development Environment - IDEs - Basic configuaration & build steps @@ -18,7 +19,11 @@ Contents - Button - LED - U[S]ARTs and Serial Consoles + - SPI + - SDIO - MMC - Configurations + f7xx-nsh + f7xx-evalos Nucleo-144 Boards: ================= @@ -63,7 +68,7 @@ Common Board Features: Nucleo F746ZG ============= -At present only the ST Nucleo F746ZG board from ST Micro is supported. See +ST Nucleo F746ZG board from ST Micro is supported. See http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-f746zg.html @@ -80,7 +85,7 @@ NUCLEO-F746ZG Features: + 16KB of instruction TCM RAM + 4KB of backup SRAM ADC: 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode - DMA: 16-stream DMA controllers with FIFOs and burst support + DMA: 2 X 16-stream DMA controllers with FIFOs and burst support Timers: Up to 18 timers: up to thirteen 16-bit (1x 16-bit lowpower), two 32-bit timers, 2x watchdogs, SysTick GPIO: 114 I/O ports with interrupt capability @@ -105,9 +110,58 @@ NUCLEO-F746ZG Features: TRG: True random number generator RTC -See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG form additional +See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG for additional information about this board. +Nucleo F767ZI +============= + +ST Nucleo F7467ZI board from ST Micro is supported. See + +http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-f767zi.html + +The Nucleo F767ZI order part number is NUCLEO-F767ZI. It is one member of +the STM32 Nucleo-144 board family. + +NUCLEO-F767ZI Features: +---------------------- + + Microprocessor: STM32F767ZIT6 Core: ARM 32-bit Cortex®-M7 CPU with DPFPU, + L1-cache: 16KB data cache and 16KB instruction cache, up to + 216 MHz, MPU, and DSP instructions. + Memory: 2048 KB Flash 512KB of SRAM (including 128KB of data TCM RAM) + + 16KB of instruction TCM RAM + 4KB of backup SRAM + ADC: 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in + triple interleaved mode + DMA: 2 X 16-stream DMA controllers with FIFOs and burst support + Timers: Up to 18 timers: up to thirteen 16-bit (1x 16-bit lowpower), + two 32-bit timers, 2x watchdogs, SysTick + GPIO: 114 I/O ports with interrupt capability + LCD: LCD-TFT Controllerwith (DMA2D), Parallel interface + I2C: 4 × I2C interfaces (SMBus/PMBus) + U[S]ARTs: 4 USARTs, 4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, + modem control) + SPI/12Ss: 6/3 (simplex) (up to 50 Mbit/s), 3 with muxed simplex I2S + for audio class accuracy via internal audio PLL or external + clock + QSPI: Dual mode Quad-SPI + SAIs: 2 Serial Audio Interfaces + CAN: 3 X CAN interface + SDMMC interface + SPDIFRX interface + USB: USB 2.0 full/High-speed device/host/OTG controller with on-chip + PHY + 10/100 Ethernet: MAC with dedicated DMA: supports IEEE 1588v2 hardware, + MII/RMII + Camera Interface: 8/14 Bit + CRC calculation unit + TRG: True random number generator + RTC subsecond accuracy, hardware calendar + +As of this writting the NUCLEO-F767ZI is not available on developer.mbed.org +However, See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG for additional +useful information. + Development Environment ======================= @@ -154,8 +208,8 @@ Basic configuration & build steps Hardware ======== - GPIO - there are 144 I/O lines on the STM32F746ZGT6 with various pins pined out - on the Nucleo F746ZG. + GPIO - there are 144 I/O lines on the STM32F7xxZxT6 with various pins pined out + on the Nucleo 144. See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG/ for slick graphic pinouts. @@ -168,19 +222,47 @@ Hardware Our main concern is establishing a console and LED utilization for debugging. Because so many pins can be multiplexed with so many functions, - the above mentioned graphic is super helpful in indentifying a serial port - that will not rob us of another IO feature. Namely Serial Port 8 (UART8) - with TX on PE1 and RX on PE0. Of course if your design has used those - pins you can choose another IO configuration to bring out Serial Port 8 - or choose a completely different U[S]ART to use as the console. - In that Case, You will need to edit the include/board.h to select different - U[S]ART and / or pin selections. + the above mentioned graphic may be helpful in indentifying a serial port. - Serial - ------ + There are 4 choices that can be made from the menuconfig: - SERIAL_RX PE_0 - SERIAL_TX PE_1 + CONFIG_NUCLEO_CONSOLE_ARDUINO or CONFIG_NUCLEO_CONSOLE_MORPHO or + CONFIG_NUCLEO_CONSOLE_VIRTUAL or CONFIG_NUCLEO_CONSOLE_NONE + + The CONFIG_NUCLEO_CONSOLE_NONE makes no preset for the console. YOu shuld still visit + the U[S]ART selection and Device Drivers to disable any U[S]ART reamaing. + + The CONFIG_NUCLEO_CONSOLE_ARDUINO configurations assume that you are using a + standard Arduio RS-232 shield with the serial interface with RX on pin D0 and + TX on pin D1 from USART6: + + -------- --------------- + STM32F7 + ARDUIONO FUNCTION GPIO + -- ----- --------- ----- + DO RX USART6_RX PG9 + D1 TX USART6_TX PG14 + -- ----- --------- ----- + + The CONFIG_NUCLEO_CONSOLE_MORPHO configurations uses Serial Port 8 (USART8) + with TX on PE1 and RX on PE0. + Serial + ------ + SERIAL_RX PE_0 + SERIAL_TX PE_1 + + The CONFIG_NUCLEO_CONSOLE_VIRTUAL configurations uses Serial Port 3 (USART3) + with TX on PD8 and RX on PD9. + Serial + ------ + SERIAL_RX PD9 + SERIAL_TX PD8 + + These signals are internalaly connected to the on board ST-Link + + Of course if your design has used those pins you can choose a completely + different U[S]ART to use as the console. In that Case, you will need to edit + the include/board.h to select different U[S]ART and / or pin selections. Buttons ------- @@ -202,32 +284,36 @@ Hardware include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS related events as follows when the LEDs are available: - SYMBOL Meaning RED GREEN BLUE - ------------------- ----------------------- ----------- + SYMBOL Meaning RED GREEN BLUE + ------------------- ----------------------- --- ----- ---- - LED_STARTED 0 OFF OFF OFF - LED_HEAPALLOCATE 0 OFF OFF OFF - LED_IRQSENABLED 0 OFF OFF OFF - LED_STACKCREATED 1 OFF ON OFF - LED_INIRQ 2 NC NC ON (momentary) - LED_SIGNAL 2 NC NC ON (momentary) - LED_ASSERTION 3 ON NC NC (momentary) - LED_PANIC 4 ON OFF OFF (flashing 2Hz) + LED_STARTED NuttX has been started OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + LED_IRQSENABLED Interrupts enabled OFF ON OFF + LED_STACKCREATED Idle stack created OFF ON ON + LED_INIRQ In an interrupt NC NC ON (momentary) + LED_SIGNAL In a signal handler NC ON OFF (momentary) + LED_ASSERTION An assertion failed ON NC ON (momentary) + LED_PANIC The system has crashed ON OFF OFF (flashing 2Hz) + LED_IDLE MCU is is sleep mode ON OFF OFF -OFF - means that the OS is still initializing. Initialization is very fast so - if you see this at all, it probably means that the system is hanging up - somewhere in the initialization phases. -GREEN - This means that the OS completed initialization. +OFF - means that the OS is still initializing. Initialization is very fast + so if you see this at all, it probably means that the system is + hanging up somewhere in the initialization phases. -BLUE - Whenever and interrupt or signal handler is entered, the BLUE LED is - illuminated and extinguished when the interrupt or signal handler exits. +GREEN - This means that the OS completed initialization. -RED - If a recovered assertion occurs, the RED LED will be illuminated - briefly while the assertion is handled. You will probably never see this. +BLUE - Whenever and interrupt or signal handler is entered, the BLUE LED is + illuminated and extinguished when the interrupt or signal handler + exits. + +VIOLET - If a recovered assertion occurs, the RED and blue LED will be + illuminated briefly while the assertion is handled. You will + probably never see this. Flashing RED - In the event of a fatal crash, all other LEDs will be -extinguished and RED LED will FLASH at a 2Hz rate. + extinguished and RED LED will FLASH at a 2Hz rate. Thus if the GREEN LED is lit, NuttX has successfully booted and is, @@ -238,30 +324,67 @@ extinguished and RED LED will FLASH at a 2Hz rate. Serial Consoles =============== - USART8 + USART6 (CONFIG_NUCLEO_CONSOLE_ARDUINO) ------ - Pins and Connectors: - GPIO Connector NAME - RXD: PE0 CN11 pin 64, PE0 - CN10 pin 33, D34 - - TXD: PE1 CN11 pin 61, PE1 + STM32F7 + ARDUIONO FUNCTION GPIO + -- ----- --------- ----- + DO RX USART6_RX PG9 + D1 TX USART6_TX PG14 + -- ----- --------- ----- You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Nucleo 144 FTDI TTL-232R-3V3 - ----------- ------------ - TXD - CN11 pin 64 - RXD - Pin 5 (Yellow) - RXD - CN11 pin 61 - TXD - Pin 4 (Orange) - GND CN11 pin 63 GND Pin 1 (Black) + ------------- ------------------- + TXD - D1-TXD - RXD - Pin 5 (Yellow) + RXD - D0-RXD - TXD - Pin 4 (Orange) + GND GND - GND Pin 1 (Black) + ------------- ------------------- + + *Note you will be reverse RX/TX + + Use make menuconfig to configure USART6 as the console: + + CONFIG_STM32F7_USART6=y + CONFIG_USARTs_SERIALDRIVER=y + CONFIG_USARTS_SERIAL_CONSOLE=y + CONFIG_USART6_RXBUFSIZE=256 + CONFIG_USART6_TXBUFSIZE=256 + CONFIG_USART6_BAUD=115200 + CONFIG_USART6_BITS=8 + CONFIG_USART6_PARITY=0 + CONFIG_USART6_2STOP=0 + + USART8 (CONFIG_NUCLEO_CONSOLE_MORPHO) + ------ + + Pins and Connectors: + FUNC GPIO Connector + Pin NAME + ---- --- ------- ---- + TXD: PE1 CN11-61, PE1 + RXD: PE0 CN12-64, PE0 + CN10-33, D34 + ---- --- ------- ---- + + + You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL + + Nucleo 144 FTDI TTL-232R-3V3 + ------------- ------------------- + TXD - CN11-61 - RXD - Pin 5 (Yellow) + RXD - CN12-64 - TXD - Pin 4 (Orange) + GND CN12-63 - GND Pin 1 (Black) + ------------- ------------------- *Note you will be reverse RX/TX Use make menuconfig to configure USART8 as the console: CONFIG_STM32F7_UART8=y - CONFIG_USART8_SERIALDRIVER=y - CONFIG_USART8_SERIAL_CONSOLE=y + CONFIG_UART8_SERIALDRIVER=y + CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 CONFIG_UART8_TXBUFSIZE=256 CONFIG_UART8_BAUD=115200 @@ -269,7 +392,7 @@ Serial Consoles CONFIG_UART8_PARITY=0 CONFIG_UART8_2STOP=0 - Virtual COM Port + Virtual COM Port (CONFIG_NUCLEO_CONSOLE_VIRTUAL) ---------------- Yet another option is to use USART3 and the USB virtual COM port. This option may be more convenient for long term development, but is painful @@ -290,14 +413,38 @@ Serial Consoles As shipped, SB4 and SB7 are open and SB5 and SB6 closed, so the virtual COM port is enabled. + +SPI +--- + Since this board is so generic, having a quick way to vet the SPI + configuration seams in order. So the board provides a quick test + that can be selected vi CONFIG_NUCLEO_SPI_TEST that will initalise + the selected buses (SPI1-SPI3) and send some text on the bus at + application initalization time board_app_initialize. + +SDIO +---- + To test the SD performace one can use a SparkFun microSD Sniffer + from https://www.sparkfun.com/products/9419 or similar board + and connect it as follows: + + VCC V3.3 CN11 16 + GND GND CN11-8 + CMD PD2 CN11-4 + CLK PC12 CN11-3 + DAT0 - PC8 CN12-2 + DAT1 - PC9 CN12-1 + DAT2 PC10 CN11-1 + CD PC11 CN11-2 + Configurations ============== -nsh: +f7xx-nsh: ---- Configures the NuttShell (nsh) located at apps/examples/nsh for the Nucleo-144 boards. The Configuration enables the serial interfaces - on UART6. Support for builtin applications is enabled, but in the base + on USART6. Support for builtin applications is enabled, but in the base configuration no builtin applications are selected (see NOTES below). NOTES: @@ -333,7 +480,7 @@ nsh: device configured for UART8 (see instruction above under "Serial Consoles). -evalos: +f7xx-evalos: ------- This configuration is designed to test the features of the board. - Configures the NuttShell (nsh) located at apps/examples/nsh for the diff --git a/configs/nucleo-144/f746-evalos/Make.defs b/configs/nucleo-144/f746-evalos/Make.defs new file mode 100644 index 0000000000..62c52e12f4 --- /dev/null +++ b/configs/nucleo-144/f746-evalos/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/nucleo-144/f746-evalos/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# Mark Olsson +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f746-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/nucleo-144/evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig similarity index 100% rename from configs/nucleo-144/evalos/defconfig rename to configs/nucleo-144/f746-evalos/defconfig diff --git a/configs/nucleo-144/evalos/setenv.sh b/configs/nucleo-144/f746-evalos/setenv.sh similarity index 98% rename from configs/nucleo-144/evalos/setenv.sh rename to configs/nucleo-144/f746-evalos/setenv.sh index 0f767948bf..84db5f90ee 100644 --- a/configs/nucleo-144/evalos/setenv.sh +++ b/configs/nucleo-144/f746-evalos/setenv.sh @@ -1,5 +1,5 @@ #!/bin/bash -# configs/nucleo-144/evalos/setenv.sh +# configs/nucleo-144/f746-evalos/setenv.sh # # Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt diff --git a/configs/nucleo-144/nsh/Make.defs b/configs/nucleo-144/f746-nsh/Make.defs similarity index 96% rename from configs/nucleo-144/nsh/Make.defs rename to configs/nucleo-144/f746-nsh/Make.defs index 45b3f5f4ae..758b9eadb8 100644 --- a/configs/nucleo-144/nsh/Make.defs +++ b/configs/nucleo-144/f746-nsh/Make.defs @@ -1,8 +1,9 @@ ############################################################################ -# configs/nucleo-144/nsh/Make.defs +# configs/nucleo-144/f746-nsh/Make.defs # # Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Authors: Gregory Nutt +# David Sidrane # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -37,7 +38,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs -LDSCRIPT = flash.ld +LDSCRIPT = f746-flash.ld ifeq ($(WINTOOL),y) # Windows-native toolchains diff --git a/configs/nucleo-144/nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig similarity index 82% rename from configs/nucleo-144/nsh/defconfig rename to configs/nucleo-144/f746-nsh/defconfig index cb59abca25..b8bcde84fe 100644 --- a/configs/nucleo-144/nsh/defconfig +++ b/configs/nucleo-144/f746-nsh/defconfig @@ -24,7 +24,7 @@ CONFIG_BUILD_FLAT=y # Binary Output Formats # # CONFIG_RRLOAD_BINARY is not set -CONFIG_INTELHEX_BINARY=y +# CONFIG_INTELHEX_BINARY is not set # CONFIG_MOTOROLA_SREC is not set CONFIG_RAW_BINARY=y # CONFIG_UBOOT_UIMAGE is not set @@ -45,7 +45,7 @@ CONFIG_RAW_BINARY=y # CONFIG_DEBUG is not set CONFIG_ARCH_HAVE_HEAPCHECK=y CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set +CONFIG_STACK_COLORATION=y CONFIG_DEBUG_SYMBOLS=y CONFIG_ARCH_HAVE_CUSTOMOPT=y CONFIG_DEBUG_NOOPT=y @@ -124,7 +124,7 @@ CONFIG_ARCH_HAVE_CMNVECTOR=y CONFIG_ARMV7M_CMNVECTOR=y # CONFIG_ARMV7M_LAZYFPU is not set CONFIG_ARCH_HAVE_FPU=y -CONFIG_ARCH_HAVE_DPFPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set # CONFIG_ARCH_FPU is not set # CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y @@ -151,22 +151,118 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set +# CONFIG_USART6_RS485 is not set +CONFIG_SERIAL_DISABLE_REORDERING=y # # STM32 F7 Configuration Options # -# CONFIG_ARCH_CHIP_STM32F745 is not set -CONFIG_ARCH_CHIP_STM32F746=y -# CONFIG_ARCH_CHIP_STM32F756 is not set +# CONFIG_ARCH_CHIP_STM32F745VG is not set +# CONFIG_ARCH_CHIP_STM32F745VE is not set +# CONFIG_ARCH_CHIP_STM32F745IG is not set +# CONFIG_ARCH_CHIP_STM32F745IE is not set +# CONFIG_ARCH_CHIP_STM32F745ZE is not set +# CONFIG_ARCH_CHIP_STM32F745ZG is not set +# CONFIG_ARCH_CHIP_STM32F746BG is not set +# CONFIG_ARCH_CHIP_STM32F746VG is not set +# CONFIG_ARCH_CHIP_STM32F746VE is not set +# CONFIG_ARCH_CHIP_STM32F746BE is not set +CONFIG_ARCH_CHIP_STM32F746ZG=y +# CONFIG_ARCH_CHIP_STM32F746IE is not set +# CONFIG_ARCH_CHIP_STM32F746NG is not set +# CONFIG_ARCH_CHIP_STM32F746NE is not set +# CONFIG_ARCH_CHIP_STM32F746ZE is not set +# CONFIG_ARCH_CHIP_STM32F746IG is not set +# CONFIG_ARCH_CHIP_STM32F756NG is not set +# CONFIG_ARCH_CHIP_STM32F756BG is not set +# CONFIG_ARCH_CHIP_STM32F756IG is not set +# CONFIG_ARCH_CHIP_STM32F756VG is not set +# CONFIG_ARCH_CHIP_STM32F756ZG is not set +# CONFIG_ARCH_CHIP_STM32F765NI is not set +# CONFIG_ARCH_CHIP_STM32F765VI is not set +# CONFIG_ARCH_CHIP_STM32F765VG is not set +# CONFIG_ARCH_CHIP_STM32F765BI is not set +# CONFIG_ARCH_CHIP_STM32F765NG is not set +# CONFIG_ARCH_CHIP_STM32F765ZG is not set +# CONFIG_ARCH_CHIP_STM32F765ZI is not set +# CONFIG_ARCH_CHIP_STM32F765IG is not set +# CONFIG_ARCH_CHIP_STM32F765BG is not set +# CONFIG_ARCH_CHIP_STM32F765II is not set +# CONFIG_ARCH_CHIP_STM32F767NG is not set +# CONFIG_ARCH_CHIP_STM32F767IG is not set +# CONFIG_ARCH_CHIP_STM32F767VG is not set +# CONFIG_ARCH_CHIP_STM32F767ZG is not set +# CONFIG_ARCH_CHIP_STM32F767NI is not set +# CONFIG_ARCH_CHIP_STM32F767VI is not set +# CONFIG_ARCH_CHIP_STM32F767BG is not set +# CONFIG_ARCH_CHIP_STM32F767ZI is not set +# CONFIG_ARCH_CHIP_STM32F767II is not set +# CONFIG_ARCH_CHIP_STM32F769BI is not set +# CONFIG_ARCH_CHIP_STM32F769II is not set +# CONFIG_ARCH_CHIP_STM32F769BG is not set +# CONFIG_ARCH_CHIP_STM32F769NI is not set +# CONFIG_ARCH_CHIP_STM32F769AI is not set +# CONFIG_ARCH_CHIP_STM32F769NG is not set +# CONFIG_ARCH_CHIP_STM32F769IG is not set +# CONFIG_ARCH_CHIP_STM32F777ZI is not set +# CONFIG_ARCH_CHIP_STM32F777VI is not set +# CONFIG_ARCH_CHIP_STM32F777NI is not set +# CONFIG_ARCH_CHIP_STM32F777BI is not set +# CONFIG_ARCH_CHIP_STM32F777II is not set +# CONFIG_ARCH_CHIP_STM32F778AI is not set +# CONFIG_ARCH_CHIP_STM32F779II is not set +# CONFIG_ARCH_CHIP_STM32F779NI is not set +# CONFIG_ARCH_CHIP_STM32F779BI is not set +# CONFIG_ARCH_CHIP_STM32F779AI is not set CONFIG_STM32F7_STM32F74XX=y # CONFIG_STM32F7_STM32F75XX is not set -# CONFIG_STM32F7_FLASH_512KB is not set -CONFIG_STM32F7_FLASH_1024KB=y +# CONFIG_STM32F7_STM32F76XX is not set +# CONFIG_STM32F7_STM32F77XX is not set +# CONFIG_STM32F7_IO_CONFIG_V is not set +# CONFIG_STM32F7_IO_CONFIG_I is not set +CONFIG_STM32F7_IO_CONFIG_Z=y +# CONFIG_STM32F7_IO_CONFIG_N is not set +# CONFIG_STM32F7_IO_CONFIG_B is not set +# CONFIG_STM32F7_IO_CONFIG_A is not set +# CONFIG_STM32F7_STM32F745XX is not set +CONFIG_STM32F7_STM32F746XX=y +# CONFIG_STM32F7_STM32F756XX is not set +# CONFIG_STM32F7_STM32F765XX is not set +# CONFIG_STM32F7_STM32F767XX is not set +# CONFIG_STM32F7_STM32F768XX is not set +# CONFIG_STM32F7_STM32F768AX is not set +# CONFIG_STM32F7_STM32F769XX is not set +# CONFIG_STM32F7_STM32F769AX is not set +# CONFIG_STM32F7_STM32F777XX is not set +# CONFIG_STM32F7_STM32F778XX is not set +# CONFIG_STM32F7_STM32F778AX is not set +# CONFIG_STM32F7_STM32F779XX is not set +# CONFIG_STM32F7_STM32F779AX is not set +# CONFIG_STM32F7_FLASH_CONFIG_E is not set +# CONFIG_STM32F7_FLASH_CONFIG_I is not set +CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y +# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set # # STM32 Peripheral Support # CONFIG_STM32F7_HAVE_LTDC=y +CONFIG_STM32F7_HAVE_FSMC=y +CONFIG_STM32F7_HAVE_ETHRNET=y +CONFIG_STM32F7_HAVE_RNG=y +CONFIG_STM32F7_HAVE_SPI5=y +CONFIG_STM32F7_HAVE_SPI6=y +# CONFIG_STM32F7_HAVE_SDMMC2 is not set +# CONFIG_STM32F7_HAVE_CAN3 is not set +CONFIG_STM32F7_HAVE_DCMI=y +# CONFIG_STM32F7_HAVE_DSIHOST is not set +CONFIG_STM32F7_HAVE_DMA2D=y +# CONFIG_STM32F7_HAVE_JPEG is not set +# CONFIG_STM32F7_HAVE_CRYP is not set +# CONFIG_STM32F7_HAVE_HASH is not set +# CONFIG_STM32F7_HAVE_DFSDM1 is not set # CONFIG_STM32F7_ADC is not set # CONFIG_STM32F7_CAN is not set # CONFIG_STM32F7_DAC is not set @@ -183,12 +279,12 @@ CONFIG_STM32F7_USART=y # CONFIG_STM32F7_CAN2 is not set # CONFIG_STM32F7_CEC is not set # CONFIG_STM32F7_CRC is not set -# CONFIG_STM32F7_CRYP is not set # CONFIG_STM32F7_DMA1 is not set # CONFIG_STM32F7_DMA2 is not set # CONFIG_STM32F7_DAC1 is not set # CONFIG_STM32F7_DAC2 is not set # CONFIG_STM32F7_DCMI is not set +# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_ETHMAC is not set # CONFIG_STM32F7_FSMC is not set # CONFIG_STM32F7_I2C1 is not set @@ -196,12 +292,11 @@ CONFIG_STM32F7_USART=y # CONFIG_STM32F7_I2C3 is not set # CONFIG_STM32F7_LPTIM1 is not set # CONFIG_STM32F7_LTDC is not set -# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_OTGFS is not set # CONFIG_STM32F7_OTGHS is not set # CONFIG_STM32F7_QUADSPI is not set -# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_RNG is not set +# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set # CONFIG_STM32F7_SDMMC1 is not set # CONFIG_STM32F7_SPDIFRX is not set @@ -236,6 +331,13 @@ CONFIG_STM32F7_USART6=y # CONFIG_STM32F7_UART8 is not set # CONFIG_STM32F7_IWDG is not set # CONFIG_STM32F7_WWDG is not set + +# +# U[S]ART Configuration +# +CONFIG_STM32F7_FLOWCONTROL_BROKEN=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set # @@ -299,7 +401,6 @@ CONFIG_RAM_SIZE=245760 # # Board Selection # -# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set CONFIG_ARCH_BOARD_NUCLEO_144=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="nucleo-144" @@ -318,6 +419,11 @@ CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +CONFIG_NUCLEO_CONSOLE_ARDUINO=y +# CONFIG_NUCLEO_CONSOLE_VIRTUAL is not set +# CONFIG_NUCLEO_CONSOLE_MORPHO is not set +# CONFIG_NUCLEO_CONSOLE_NONE is not set +# CONFIG_NUCLEO_SPI_TEST is not set # CONFIG_LIB_BOARDCTL is not set # @@ -337,9 +443,9 @@ CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set # CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=6 +CONFIG_START_YEAR=2015 +CONFIG_START_MONTH=11 +CONFIG_START_DAY=30 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=4 CONFIG_WDOG_INTRESERVE=0 @@ -464,7 +570,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set # # LED Support @@ -506,10 +617,6 @@ CONFIG_USART6_SERIALDRIVER=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set - -# -# USART Configuration -# CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set @@ -777,6 +884,7 @@ CONFIG_EXAMPLES_NSH=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -903,5 +1011,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_STACKMONITOR is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-144/nsh/setenv.sh b/configs/nucleo-144/f746-nsh/setenv.sh similarity index 98% rename from configs/nucleo-144/nsh/setenv.sh rename to configs/nucleo-144/f746-nsh/setenv.sh index 8498950aed..6a5fa6c801 100644 --- a/configs/nucleo-144/nsh/setenv.sh +++ b/configs/nucleo-144/f746-nsh/setenv.sh @@ -1,5 +1,5 @@ #!/bin/bash -# configs/nucleo-144/nsh/setenv.sh +# configs/nucleo-144/f746-nsh/setenv.sh # # Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt diff --git a/configs/nucleo-144/f767-evalos/Make.defs b/configs/nucleo-144/f767-evalos/Make.defs new file mode 100644 index 0000000000..3e25864217 --- /dev/null +++ b/configs/nucleo-144/f767-evalos/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/nucleo-144/f767-evalos/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# Mark Olsson +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f767-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig new file mode 100644 index 0000000000..e4165fa20d --- /dev/null +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -0,0 +1,1047 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +CONFIG_ARCH_HAVE_STACKCHECK=y +CONFIG_STACK_COLORATION=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +CONFIG_ARCH_CHIP_STM32F7=y +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM4 is not set +CONFIG_ARCH_CORTEXM7=y +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32f7" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +CONFIG_ARMV7M_CMNVECTOR=y +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +CONFIG_ARCH_HAVE_DPFPU=y +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_HAVE_ICACHE=y +CONFIG_ARMV7M_HAVE_DCACHE=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_HAVE_ITCM=y +CONFIG_ARMV7M_HAVE_DTCM=y +# CONFIG_ARMV7M_ITCM is not set +CONFIG_ARMV7M_DTCM=y +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_USART3_RS485 is not set +CONFIG_SERIAL_DISABLE_REORDERING=y + +# +# STM32 F7 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F745VG is not set +# CONFIG_ARCH_CHIP_STM32F745VE is not set +# CONFIG_ARCH_CHIP_STM32F745IG is not set +# CONFIG_ARCH_CHIP_STM32F745IE is not set +# CONFIG_ARCH_CHIP_STM32F745ZE is not set +# CONFIG_ARCH_CHIP_STM32F745ZG is not set +# CONFIG_ARCH_CHIP_STM32F746BG is not set +# CONFIG_ARCH_CHIP_STM32F746VG is not set +# CONFIG_ARCH_CHIP_STM32F746VE is not set +# CONFIG_ARCH_CHIP_STM32F746BE is not set +# CONFIG_ARCH_CHIP_STM32F746ZG is not set +# CONFIG_ARCH_CHIP_STM32F746IE is not set +# CONFIG_ARCH_CHIP_STM32F746NG is not set +# CONFIG_ARCH_CHIP_STM32F746NE is not set +# CONFIG_ARCH_CHIP_STM32F746ZE is not set +# CONFIG_ARCH_CHIP_STM32F746IG is not set +# CONFIG_ARCH_CHIP_STM32F756NG is not set +# CONFIG_ARCH_CHIP_STM32F756BG is not set +# CONFIG_ARCH_CHIP_STM32F756IG is not set +# CONFIG_ARCH_CHIP_STM32F756VG is not set +# CONFIG_ARCH_CHIP_STM32F756ZG is not set +# CONFIG_ARCH_CHIP_STM32F765NI is not set +# CONFIG_ARCH_CHIP_STM32F765VI is not set +# CONFIG_ARCH_CHIP_STM32F765VG is not set +# CONFIG_ARCH_CHIP_STM32F765BI is not set +# CONFIG_ARCH_CHIP_STM32F765NG is not set +# CONFIG_ARCH_CHIP_STM32F765ZG is not set +# CONFIG_ARCH_CHIP_STM32F765ZI is not set +# CONFIG_ARCH_CHIP_STM32F765IG is not set +# CONFIG_ARCH_CHIP_STM32F765BG is not set +# CONFIG_ARCH_CHIP_STM32F765II is not set +# CONFIG_ARCH_CHIP_STM32F767NG is not set +# CONFIG_ARCH_CHIP_STM32F767IG is not set +# CONFIG_ARCH_CHIP_STM32F767VG is not set +# CONFIG_ARCH_CHIP_STM32F767ZG is not set +# CONFIG_ARCH_CHIP_STM32F767NI is not set +# CONFIG_ARCH_CHIP_STM32F767VI is not set +# CONFIG_ARCH_CHIP_STM32F767BG is not set +CONFIG_ARCH_CHIP_STM32F767ZI=y +# CONFIG_ARCH_CHIP_STM32F767II is not set +# CONFIG_ARCH_CHIP_STM32F769BI is not set +# CONFIG_ARCH_CHIP_STM32F769II is not set +# CONFIG_ARCH_CHIP_STM32F769BG is not set +# CONFIG_ARCH_CHIP_STM32F769NI is not set +# CONFIG_ARCH_CHIP_STM32F769AI is not set +# CONFIG_ARCH_CHIP_STM32F769NG is not set +# CONFIG_ARCH_CHIP_STM32F769IG is not set +# CONFIG_ARCH_CHIP_STM32F777ZI is not set +# CONFIG_ARCH_CHIP_STM32F777VI is not set +# CONFIG_ARCH_CHIP_STM32F777NI is not set +# CONFIG_ARCH_CHIP_STM32F777BI is not set +# CONFIG_ARCH_CHIP_STM32F777II is not set +# CONFIG_ARCH_CHIP_STM32F778AI is not set +# CONFIG_ARCH_CHIP_STM32F779II is not set +# CONFIG_ARCH_CHIP_STM32F779NI is not set +# CONFIG_ARCH_CHIP_STM32F779BI is not set +# CONFIG_ARCH_CHIP_STM32F779AI is not set +# CONFIG_STM32F7_STM32F74XX is not set +# CONFIG_STM32F7_STM32F75XX is not set +CONFIG_STM32F7_STM32F76XX=y +# CONFIG_STM32F7_STM32F77XX is not set +# CONFIG_STM32F7_IO_CONFIG_V is not set +# CONFIG_STM32F7_IO_CONFIG_I is not set +CONFIG_STM32F7_IO_CONFIG_Z=y +# CONFIG_STM32F7_IO_CONFIG_N is not set +# CONFIG_STM32F7_IO_CONFIG_B is not set +# CONFIG_STM32F7_IO_CONFIG_A is not set +# CONFIG_STM32F7_STM32F745XX is not set +# CONFIG_STM32F7_STM32F746XX is not set +# CONFIG_STM32F7_STM32F756XX is not set +# CONFIG_STM32F7_STM32F765XX is not set +CONFIG_STM32F7_STM32F767XX=y +# CONFIG_STM32F7_STM32F768XX is not set +# CONFIG_STM32F7_STM32F768AX is not set +# CONFIG_STM32F7_STM32F769XX is not set +# CONFIG_STM32F7_STM32F769AX is not set +# CONFIG_STM32F7_STM32F777XX is not set +# CONFIG_STM32F7_STM32F778XX is not set +# CONFIG_STM32F7_STM32F778AX is not set +# CONFIG_STM32F7_STM32F779XX is not set +# CONFIG_STM32F7_STM32F779AX is not set +# CONFIG_STM32F7_FLASH_CONFIG_E is not set +CONFIG_STM32F7_FLASH_CONFIG_I=y +CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y +# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32F7_HAVE_LTDC=y +CONFIG_STM32F7_HAVE_FSMC=y +CONFIG_STM32F7_HAVE_ETHRNET=y +CONFIG_STM32F7_HAVE_RNG=y +CONFIG_STM32F7_HAVE_SPI5=y +CONFIG_STM32F7_HAVE_SPI6=y +CONFIG_STM32F7_HAVE_SDMMC2=y +CONFIG_STM32F7_HAVE_CAN3=y +CONFIG_STM32F7_HAVE_DCMI=y +# CONFIG_STM32F7_HAVE_DSIHOST is not set +CONFIG_STM32F7_HAVE_DMA2D=y +CONFIG_STM32F7_HAVE_JPEG=y +# CONFIG_STM32F7_HAVE_CRYP is not set +# CONFIG_STM32F7_HAVE_HASH is not set +CONFIG_STM32F7_HAVE_DFSDM1=y +# CONFIG_STM32F7_ADC is not set +# CONFIG_STM32F7_CAN is not set +# CONFIG_STM32F7_DAC is not set +# CONFIG_STM32F7_DMA is not set +# CONFIG_STM32F7_I2C is not set +# CONFIG_STM32F7_SAI is not set +# CONFIG_STM32F7_SPI is not set +CONFIG_STM32F7_USART=y +# CONFIG_STM32F7_ADC1 is not set +# CONFIG_STM32F7_ADC2 is not set +# CONFIG_STM32F7_ADC3 is not set +# CONFIG_STM32F7_BKPSRAM is not set +# CONFIG_STM32F7_CAN1 is not set +# CONFIG_STM32F7_CAN2 is not set +# CONFIG_STM32F7_CAN3 is not set +# CONFIG_STM32F7_CEC is not set +# CONFIG_STM32F7_CRC is not set +# CONFIG_STM32F7_DFSDM1 is not set +# CONFIG_STM32F7_DMA1 is not set +# CONFIG_STM32F7_DMA2 is not set +# CONFIG_STM32F7_DAC1 is not set +# CONFIG_STM32F7_DAC2 is not set +# CONFIG_STM32F7_DCMI is not set +# CONFIG_STM32F7_DMA2D is not set +# CONFIG_STM32F7_JPEG is not set +# CONFIG_STM32F7_ETHMAC is not set +# CONFIG_STM32F7_FSMC is not set +# CONFIG_STM32F7_I2C1 is not set +# CONFIG_STM32F7_I2C2 is not set +# CONFIG_STM32F7_I2C3 is not set +# CONFIG_STM32F7_LPTIM1 is not set +# CONFIG_STM32F7_LTDC is not set +# CONFIG_STM32F7_OTGFS is not set +# CONFIG_STM32F7_OTGHS is not set +# CONFIG_STM32F7_QUADSPI is not set +# CONFIG_STM32F7_RNG is not set +# CONFIG_STM32F7_SAI1 is not set +# CONFIG_STM32F7_SAI2 is not set +# CONFIG_STM32F7_SDMMC1 is not set +# CONFIG_STM32F7_SDMMC2 is not set +# CONFIG_STM32F7_SPDIFRX is not set +# CONFIG_STM32F7_SPI1 is not set +# CONFIG_STM32F7_SPI2 is not set +# CONFIG_STM32F7_SPI3 is not set +# CONFIG_STM32F7_SPI4 is not set +# CONFIG_STM32F7_SPI5 is not set +# CONFIG_STM32F7_SPI6 is not set +# CONFIG_STM32F7_TIM1 is not set +# CONFIG_STM32F7_TIM2 is not set +# CONFIG_STM32F7_TIM3 is not set +# CONFIG_STM32F7_TIM4 is not set +# CONFIG_STM32F7_TIM5 is not set +# CONFIG_STM32F7_TIM6 is not set +# CONFIG_STM32F7_TIM7 is not set +# CONFIG_STM32F7_TIM8 is not set +# CONFIG_STM32F7_TIM9 is not set +# CONFIG_STM32F7_TIM10 is not set +# CONFIG_STM32F7_TIM11 is not set +# CONFIG_STM32F7_TIM12 is not set +# CONFIG_STM32F7_TIM13 is not set +# CONFIG_STM32F7_TIM14 is not set +# CONFIG_STM32F7_TIM15 is not set +# CONFIG_STM32F7_USART1 is not set +# CONFIG_STM32F7_USART2 is not set +CONFIG_STM32F7_USART3=y +# CONFIG_STM32F7_UART4 is not set +# CONFIG_STM32F7_UART5 is not set +# CONFIG_STM32F7_USART6 is not set +# CONFIG_STM32F7_UART7 is not set +# CONFIG_STM32F7_UART8 is not set +# CONFIG_STM32F7_IWDG is not set +# CONFIG_STM32F7_WWDG is not set + +# +# U[S]ART Configuration +# +CONFIG_STM32F7_FLOWCONTROL_BROKEN=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=43103 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20010000 +CONFIG_RAM_SIZE=245760 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NUCLEO_144=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nucleo-144" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +# CONFIG_ARCH_LEDS is not set +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# +# CONFIG_NUCLEO_CONSOLE_ARDUINO is not set +CONFIG_NUCLEO_CONSOLE_VIRTUAL=y +# CONFIG_NUCLEO_CONSOLE_MORPHO is not set +# CONFIG_NUCLEO_CONSOLE_NONE is not set +# CONFIG_NUCLEO_SPI_TEST is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2015 +CONFIG_START_MONTH=11 +CONFIG_START_DAY=30 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_SEM_PREALLOCHOLDERS=16 +CONFIG_SEM_NNESTPRIO=16 + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=100000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPNTHREADS=1 +CONFIG_SCHED_LPWORKPRIORITY=50 +CONFIG_SCHED_LPWORKPRIOMAX=176 +CONFIG_SCHED_LPWORKPERIOD=50000 +CONFIG_SCHED_LPWORKSTACKSIZE=2048 + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CRCGENERATION is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +CONFIG_USART3_SERIALDRIVER=y +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART3_SERIAL_CONSOLE=y +# CONFIG_UART8_SERIAL_CONSOLE is not set +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART3 Configuration +# +CONFIG_USART3_RXBUFSIZE=256 +CONFIG_USART3_TXBUFSIZE=256 +CONFIG_USART3_BAUD=115200 +CONFIG_USART3_BITS=8 +CONFIG_USART3_PARITY=0 +CONFIG_USART3_2STOP=0 +# CONFIG_USART3_IFLOWCONTROL is not set +# CONFIG_USART3_OFLOWCONTROL is not set +# CONFIG_USART3_DMA is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_DRIVERS_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_CONSOLE is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_AIO is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set +# CONFIG_SYSLOG_TIMESTAMP is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_HELLOXX_CXXINITIALIZE=y +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_LEDS_PRIORITY=100 +CONFIG_EXAMPLES_LEDS_STACKSIZE=2048 +CONFIG_EXAMPLES_LEDS_DEVPATH="/dev/userleds" +CONFIG_EXAMPLES_LEDS_LEDSET=0x0f +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_READLINE_MAX_BUILTINS=64 +CONFIG_READLINE_MAX_EXTCMDS=64 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LINELEN=80 +CONFIG_READLINE_CMD_HISTORY_LEN=16 +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_STACKMONITOR is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-144/f767-evalos/setenv.sh b/configs/nucleo-144/f767-evalos/setenv.sh new file mode 100644 index 0000000000..cf10804e84 --- /dev/null +++ b/configs/nucleo-144/f767-evalos/setenv.sh @@ -0,0 +1,78 @@ +#!/bin/bash +# configs/nucleo-144/f767-evalos/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Author: Mark Olsson +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/nucleo-144/evalos/Make.defs b/configs/nucleo-144/f767-nsh/Make.defs similarity index 96% rename from configs/nucleo-144/evalos/Make.defs rename to configs/nucleo-144/f767-nsh/Make.defs index 210c5ff074..9b667c97ef 100644 --- a/configs/nucleo-144/evalos/Make.defs +++ b/configs/nucleo-144/f767-nsh/Make.defs @@ -1,9 +1,9 @@ ############################################################################ -# configs/nucleo-144/evalos/Make.defs +# configs/nucleo-144/f767-nsh/Make.defs # # Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# Author: Mark Olsson +# Authors: Gregory Nutt +# David Sidrane # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -38,7 +38,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs -LDSCRIPT = flash.ld +LDSCRIPT = f767-flash.ld ifeq ($(WINTOOL),y) # Windows-native toolchains @@ -111,3 +111,4 @@ HOSTCC = gcc HOSTINCLUDES = -I. HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe HOSTLDFLAGS = + diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig new file mode 100644 index 0000000000..8e7fae13a4 --- /dev/null +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -0,0 +1,1021 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +CONFIG_ARCH_HAVE_STACKCHECK=y +CONFIG_STACK_COLORATION=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +CONFIG_ARCH_CHIP_STM32F7=y +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM4 is not set +CONFIG_ARCH_CORTEXM7=y +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32f7" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +CONFIG_ARMV7M_CMNVECTOR=y +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +CONFIG_ARCH_HAVE_DPFPU=y +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +CONFIG_ARMV7M_HAVE_ICACHE=y +CONFIG_ARMV7M_HAVE_DCACHE=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_HAVE_ITCM=y +CONFIG_ARMV7M_HAVE_DTCM=y +# CONFIG_ARMV7M_ITCM is not set +CONFIG_ARMV7M_DTCM=y +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set +# CONFIG_USART6_RS485 is not set +CONFIG_SERIAL_DISABLE_REORDERING=y + +# +# STM32 F7 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32F745VG is not set +# CONFIG_ARCH_CHIP_STM32F745VE is not set +# CONFIG_ARCH_CHIP_STM32F745IG is not set +# CONFIG_ARCH_CHIP_STM32F745IE is not set +# CONFIG_ARCH_CHIP_STM32F745ZE is not set +# CONFIG_ARCH_CHIP_STM32F745ZG is not set +# CONFIG_ARCH_CHIP_STM32F746BG is not set +# CONFIG_ARCH_CHIP_STM32F746VG is not set +# CONFIG_ARCH_CHIP_STM32F746VE is not set +# CONFIG_ARCH_CHIP_STM32F746BE is not set +# CONFIG_ARCH_CHIP_STM32F746ZG is not set +# CONFIG_ARCH_CHIP_STM32F746IE is not set +# CONFIG_ARCH_CHIP_STM32F746NG is not set +# CONFIG_ARCH_CHIP_STM32F746NE is not set +# CONFIG_ARCH_CHIP_STM32F746ZE is not set +# CONFIG_ARCH_CHIP_STM32F746IG is not set +# CONFIG_ARCH_CHIP_STM32F756NG is not set +# CONFIG_ARCH_CHIP_STM32F756BG is not set +# CONFIG_ARCH_CHIP_STM32F756IG is not set +# CONFIG_ARCH_CHIP_STM32F756VG is not set +# CONFIG_ARCH_CHIP_STM32F756ZG is not set +# CONFIG_ARCH_CHIP_STM32F765NI is not set +# CONFIG_ARCH_CHIP_STM32F765VI is not set +# CONFIG_ARCH_CHIP_STM32F765VG is not set +# CONFIG_ARCH_CHIP_STM32F765BI is not set +# CONFIG_ARCH_CHIP_STM32F765NG is not set +# CONFIG_ARCH_CHIP_STM32F765ZG is not set +# CONFIG_ARCH_CHIP_STM32F765ZI is not set +# CONFIG_ARCH_CHIP_STM32F765IG is not set +# CONFIG_ARCH_CHIP_STM32F765BG is not set +# CONFIG_ARCH_CHIP_STM32F765II is not set +# CONFIG_ARCH_CHIP_STM32F767NG is not set +# CONFIG_ARCH_CHIP_STM32F767IG is not set +# CONFIG_ARCH_CHIP_STM32F767VG is not set +# CONFIG_ARCH_CHIP_STM32F767ZG is not set +# CONFIG_ARCH_CHIP_STM32F767NI is not set +# CONFIG_ARCH_CHIP_STM32F767VI is not set +# CONFIG_ARCH_CHIP_STM32F767BG is not set +CONFIG_ARCH_CHIP_STM32F767ZI=y +# CONFIG_ARCH_CHIP_STM32F767II is not set +# CONFIG_ARCH_CHIP_STM32F769BI is not set +# CONFIG_ARCH_CHIP_STM32F769II is not set +# CONFIG_ARCH_CHIP_STM32F769BG is not set +# CONFIG_ARCH_CHIP_STM32F769NI is not set +# CONFIG_ARCH_CHIP_STM32F769AI is not set +# CONFIG_ARCH_CHIP_STM32F769NG is not set +# CONFIG_ARCH_CHIP_STM32F769IG is not set +# CONFIG_ARCH_CHIP_STM32F777ZI is not set +# CONFIG_ARCH_CHIP_STM32F777VI is not set +# CONFIG_ARCH_CHIP_STM32F777NI is not set +# CONFIG_ARCH_CHIP_STM32F777BI is not set +# CONFIG_ARCH_CHIP_STM32F777II is not set +# CONFIG_ARCH_CHIP_STM32F778AI is not set +# CONFIG_ARCH_CHIP_STM32F779II is not set +# CONFIG_ARCH_CHIP_STM32F779NI is not set +# CONFIG_ARCH_CHIP_STM32F779BI is not set +# CONFIG_ARCH_CHIP_STM32F779AI is not set +# CONFIG_STM32F7_STM32F74XX is not set +# CONFIG_STM32F7_STM32F75XX is not set +CONFIG_STM32F7_STM32F76XX=y +# CONFIG_STM32F7_STM32F77XX is not set +# CONFIG_STM32F7_IO_CONFIG_V is not set +# CONFIG_STM32F7_IO_CONFIG_I is not set +CONFIG_STM32F7_IO_CONFIG_Z=y +# CONFIG_STM32F7_IO_CONFIG_N is not set +# CONFIG_STM32F7_IO_CONFIG_B is not set +# CONFIG_STM32F7_IO_CONFIG_A is not set +# CONFIG_STM32F7_STM32F745XX is not set +# CONFIG_STM32F7_STM32F746XX is not set +# CONFIG_STM32F7_STM32F756XX is not set +# CONFIG_STM32F7_STM32F765XX is not set +CONFIG_STM32F7_STM32F767XX=y +# CONFIG_STM32F7_STM32F768XX is not set +# CONFIG_STM32F7_STM32F768AX is not set +# CONFIG_STM32F7_STM32F769XX is not set +# CONFIG_STM32F7_STM32F769AX is not set +# CONFIG_STM32F7_STM32F777XX is not set +# CONFIG_STM32F7_STM32F778XX is not set +# CONFIG_STM32F7_STM32F778AX is not set +# CONFIG_STM32F7_STM32F779XX is not set +# CONFIG_STM32F7_STM32F779AX is not set +# CONFIG_STM32F7_FLASH_CONFIG_E is not set +CONFIG_STM32F7_FLASH_CONFIG_I=y +CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y +# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32F7_HAVE_LTDC=y +CONFIG_STM32F7_HAVE_FSMC=y +CONFIG_STM32F7_HAVE_ETHRNET=y +CONFIG_STM32F7_HAVE_RNG=y +CONFIG_STM32F7_HAVE_SPI5=y +CONFIG_STM32F7_HAVE_SPI6=y +CONFIG_STM32F7_HAVE_SDMMC2=y +CONFIG_STM32F7_HAVE_CAN3=y +CONFIG_STM32F7_HAVE_DCMI=y +# CONFIG_STM32F7_HAVE_DSIHOST is not set +CONFIG_STM32F7_HAVE_DMA2D=y +CONFIG_STM32F7_HAVE_JPEG=y +# CONFIG_STM32F7_HAVE_CRYP is not set +# CONFIG_STM32F7_HAVE_HASH is not set +CONFIG_STM32F7_HAVE_DFSDM1=y +# CONFIG_STM32F7_ADC is not set +# CONFIG_STM32F7_CAN is not set +# CONFIG_STM32F7_DAC is not set +# CONFIG_STM32F7_DMA is not set +# CONFIG_STM32F7_I2C is not set +# CONFIG_STM32F7_SAI is not set +# CONFIG_STM32F7_SPI is not set +CONFIG_STM32F7_USART=y +# CONFIG_STM32F7_ADC1 is not set +# CONFIG_STM32F7_ADC2 is not set +# CONFIG_STM32F7_ADC3 is not set +# CONFIG_STM32F7_BKPSRAM is not set +# CONFIG_STM32F7_CAN1 is not set +# CONFIG_STM32F7_CAN2 is not set +# CONFIG_STM32F7_CAN3 is not set +# CONFIG_STM32F7_CEC is not set +# CONFIG_STM32F7_CRC is not set +# CONFIG_STM32F7_DFSDM1 is not set +# CONFIG_STM32F7_DMA1 is not set +# CONFIG_STM32F7_DMA2 is not set +# CONFIG_STM32F7_DAC1 is not set +# CONFIG_STM32F7_DAC2 is not set +# CONFIG_STM32F7_DCMI is not set +# CONFIG_STM32F7_DMA2D is not set +# CONFIG_STM32F7_JPEG is not set +# CONFIG_STM32F7_ETHMAC is not set +# CONFIG_STM32F7_FSMC is not set +# CONFIG_STM32F7_I2C1 is not set +# CONFIG_STM32F7_I2C2 is not set +# CONFIG_STM32F7_I2C3 is not set +# CONFIG_STM32F7_LPTIM1 is not set +# CONFIG_STM32F7_LTDC is not set +# CONFIG_STM32F7_OTGFS is not set +# CONFIG_STM32F7_OTGHS is not set +# CONFIG_STM32F7_QUADSPI is not set +# CONFIG_STM32F7_RNG is not set +# CONFIG_STM32F7_SAI1 is not set +# CONFIG_STM32F7_SAI2 is not set +# CONFIG_STM32F7_SDMMC1 is not set +# CONFIG_STM32F7_SDMMC2 is not set +# CONFIG_STM32F7_SPDIFRX is not set +# CONFIG_STM32F7_SPI1 is not set +# CONFIG_STM32F7_SPI2 is not set +# CONFIG_STM32F7_SPI3 is not set +# CONFIG_STM32F7_SPI4 is not set +# CONFIG_STM32F7_SPI5 is not set +# CONFIG_STM32F7_SPI6 is not set +# CONFIG_STM32F7_TIM1 is not set +# CONFIG_STM32F7_TIM2 is not set +# CONFIG_STM32F7_TIM3 is not set +# CONFIG_STM32F7_TIM4 is not set +# CONFIG_STM32F7_TIM5 is not set +# CONFIG_STM32F7_TIM6 is not set +# CONFIG_STM32F7_TIM7 is not set +# CONFIG_STM32F7_TIM8 is not set +# CONFIG_STM32F7_TIM9 is not set +# CONFIG_STM32F7_TIM10 is not set +# CONFIG_STM32F7_TIM11 is not set +# CONFIG_STM32F7_TIM12 is not set +# CONFIG_STM32F7_TIM13 is not set +# CONFIG_STM32F7_TIM14 is not set +# CONFIG_STM32F7_TIM15 is not set +# CONFIG_STM32F7_USART1 is not set +# CONFIG_STM32F7_USART2 is not set +# CONFIG_STM32F7_USART3 is not set +# CONFIG_STM32F7_UART4 is not set +# CONFIG_STM32F7_UART5 is not set +CONFIG_STM32F7_USART6=y +# CONFIG_STM32F7_UART7 is not set +# CONFIG_STM32F7_UART8 is not set +# CONFIG_STM32F7_IWDG is not set +# CONFIG_STM32F7_WWDG is not set + +# +# U[S]ART Configuration +# +CONFIG_STM32F7_FLOWCONTROL_BROKEN=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=43103 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20010000 +CONFIG_RAM_SIZE=245760 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NUCLEO_144=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nucleo-144" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# +CONFIG_NUCLEO_CONSOLE_ARDUINO=y +# CONFIG_NUCLEO_CONSOLE_VIRTUAL is not set +# CONFIG_NUCLEO_CONSOLE_MORPHO is not set +# CONFIG_NUCLEO_CONSOLE_NONE is not set +# CONFIG_NUCLEO_SPI_TEST is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2015 +CONFIG_START_MONTH=11 +CONFIG_START_DAY=30 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CRCGENERATION is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +CONFIG_USART6_SERIALDRIVER=y +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART6_SERIAL_CONSOLE=y +# CONFIG_UART8_SERIAL_CONSOLE is not set +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART6 Configuration +# +CONFIG_USART6_RXBUFSIZE=256 +CONFIG_USART6_TXBUFSIZE=256 +CONFIG_USART6_BAUD=115200 +CONFIG_USART6_BITS=8 +CONFIG_USART6_PARITY=0 +CONFIG_USART6_2STOP=0 +# CONFIG_USART6_IFLOWCONTROL is not set +# CONFIG_USART6_OFLOWCONTROL is not set +# CONFIG_USART6_DMA is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_DRIVERS_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_CONSOLE is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set +# CONFIG_SYSLOG_TIMESTAMP is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_STACKMONITOR is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-144/f767-nsh/setenv.sh b/configs/nucleo-144/f767-nsh/setenv.sh new file mode 100644 index 0000000000..e6eabd1f70 --- /dev/null +++ b/configs/nucleo-144/f767-nsh/setenv.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# configs/nucleo-144/f767-nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index 63eb5df084..d309e13938 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -2,8 +2,9 @@ * configs/nucleo-144/include/board.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Author: Mark Olsson + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -59,17 +60,17 @@ ************************************************************************************/ /* Clocking *************************************************************************/ -/* The STM32F7 Discovery board provides the following clock sources: +/* The Nucleo-144 board provides the following clock sources: * - * X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board) - * X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY. - * X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC + * MCO: 8 MHz from MCO output of ST-LINK is used as input clock + * X2: 32.768 KHz crystal for LSE + * X3: HSE crystal oscillator (not provided) * * So we have these clock source available within the STM32 * * HSI: 16 MHz RC factory-trimmed * LSI: 32 KHz RC - * HSE: On-board crystal frequency is 25MHz + * HSE: 8 MHz from MCO output of ST-LINK * LSE: 32.768 kHz */ @@ -106,56 +107,53 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_USBOTHFS) /* Highest SYSCLK with USB OTG FS clock = 48 MHz * - * PLL_VCO = (8,000,000 / 8) * 384 = 384 MHz - * SYSCLK = 384 MHz / 2 = 192 MHz - * USB OTG FS, SDMMC and RNG Clock = 384 MHz / 8 = 48MHz - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 384) -#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) - -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG) -/* Highest SYSCLK with USB OTG FS clock <= 48MHz - * - * PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz + * PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz * SYSCLK = 432 MHz / 2 = 216 MHz - * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz + * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz */ -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216) #define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9) -#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432) +#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 216) #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9) -#else -/* Highest SYSCLK - * - * PLL_VCO = (8,000,000 / 8) * 432 = 432 MHz - * SYSCLK = 432 MHz / 2 = 216 MHz - */ +/* Configure factors for PLLSAI clock */ -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10) +#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) +#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) -#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 432) -#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#endif +/* Configure Dedicated Clock Configuration Register */ + +#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1) +#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI +#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI +#define STM32_RCC_DCKCFGR_TIMPRE 0 +#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL +#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL + +/* Configure factors for PLLI2S clock */ + +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) + +/* Configure Dedicated Clock Configuration Register 2 */ + +#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB +#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI +#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI +#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ +#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL /* Several prescalers allow the configuration of the two AHB buses, the * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum @@ -215,12 +213,9 @@ #define BOARD_FLASH_WAITSTATES 7 /* LED definitions ******************************************************************/ -/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the - * reset button, that can be controlled by software (LD2 is a power indicator, LD3-6 - * indicate USB status, LD7 is controlled by the ST-Link). - * - * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface. - * One end of LD1 is grounded so a high output on PI1 will illuminate the LED. +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue + * LED and LD3 a Red LED, that can be controlled by software. The following + * definitions assume the default Solder Bridges are installed. * * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. * The following definitions are used to access individual LEDs. @@ -233,9 +228,9 @@ #define BOARD_LED3 2 #define BOARD_NLEDS 3 -#define BOARD_LD1 BOARD_LED1 -#define BOARD_LD2 BOARD_LED2 -#define BOARD_LD3 BOARD_LED3 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 /* LED bits for use with board_userled_all() */ @@ -247,33 +242,29 @@ * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related * events as follows: * - * SYMBOL Meaning LD1 - * ------------------- ----------------------- ------ - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt N/C - * LED_SIGNAL In a signal handler N/C - * LED_ASSERTION An assertion failed N/C - * LED_PANIC The system has crashed FLASH * - * Thus is LD1 is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LD1 is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ----*/ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. */ -#define LED_STARTED 0 /* LD1=OFF */ -#define LED_HEAPALLOCATE 0 /* LD1=OFF */ -#define LED_IRQSENABLED 0 /* LD1=OFF */ -#define LED_STACKCREATED 1 /* LD1=ON */ -#define LED_INIRQ 2 /* LD1=no change */ -#define LED_SIGNAL 2 /* LD1=no change */ -#define LED_ASSERTION 2 /* LD1=no change */ -#define LED_PANIC 3 /* LD1=flashing */ - /* Button definitions ***************************************************************/ -/* The STM32F7 Discovery supports one button: Pushbutton B1, labelled "User", is +/* The STM32F7 Discovery supports one button: Pushbutton B1, labeled "User", is * connected to GPIO PI11. A high value will be sensed when the button is depressed. */ @@ -283,6 +274,7 @@ /* Alternate function pin selections ************************************************/ +#if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO) /* USART6: * * These configurations assume that you are using a standard Arduio RS-232 shield @@ -292,16 +284,32 @@ * STM32F7 * ARDUIONO FUNCTION GPIO * -- ----- --------- ----- - * DO RX USART6_RX PC7 - * D1 TX USART6_TX PC6 + * DO RX USART6_RX PG9 + * D1 TX USART6_TX PG14 * -- ----- --------- ----- */ - #define GPIO_USART6_RX GPIO_USART6_RX_1 - #define GPIO_USART6_TX GPIO_USART6_TX_1 + # define GPIO_USART6_RX GPIO_USART6_RX_2 + # define GPIO_USART6_TX GPIO_USART6_TX_2 +#endif + +/* USART3: + * Use USART3 and the USB virtual COM port +*/ +#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL) + # define GPIO_USART3_RX GPIO_USART3_RX_3 + # define GPIO_USART3_TX GPIO_USART3_TX_3 +#endif + +/* USART8: + * + * This configurations assume that you are connecting to the Morpho connector + * with the serial interface with the adaptor's RX on pin CN11 pin 64 and + * TX on pin CN11 pin 61 + * + * USART8: has noit remap + */ - #define GPIO_USART3_RX GPIO_USART3_RX_3 - #define GPIO_USART3_TX GPIO_USART3_TX_3 /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins: * diff --git a/configs/nucleo-144/scripts/flash.ld b/configs/nucleo-144/scripts/f746-flash.ld similarity index 83% rename from configs/nucleo-144/scripts/flash.ld rename to configs/nucleo-144/scripts/f746-flash.ld index 90e589ed8a..bc8b07e4fa 100644 --- a/configs/nucleo-144/scripts/flash.ld +++ b/configs/nucleo-144/scripts/f746-flash.ld @@ -1,10 +1,9 @@ /**************************************************************************** - * configs/nucleo-144/scripts/flash.ld + * configs/nucleo-144/scripts/f746-flash.ld * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Modified 11/4/2013 for STM32F429 support * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -35,14 +34,14 @@ * ****************************************************************************/ -/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can - * be accessed from either the AXIM interface at address 0x0800:0000 or from - * the ITCM interface at address 0x0020:0000. +/* The STM32F746ZGT6 has 1024 KiB of main FLASH memory. This FLASH memory + * can be accessed from either the AXIM interface at address 0x0800:0000 or + * from the ITCM interface at address 0x0020:0000. * * Additional information, including the option bytes, is available at at * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). * - * In the STM32F746NGH6, two different boot spaces can be selected through + * In the STM32F746ZGT6, two different boot spaces can be selected through * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and * BOOT_ADD1 option bytes: * @@ -51,16 +50,16 @@ * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. * ST programmed value: System bootloader at 0x0010:0000 * - * NuttX does not modify these option byes. On the unmodified STM32F746G - * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot - * to address 0x0020:0000 in ITCM FLASH. + * NuttX does not modify these option byes. On the unmodified NUCLEO-144 + * board, the BOOT0 pin is at ground so by default, the STM32F746ZGT6 will + * boot from address 0x0020:0000 in ITCM FLASH. * - * The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM). + * The STM32F746ZGT6 also has 320 KiB of data SRAM (in addition to ITCM SRAM). * SRAM is split up into three blocks: * - * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000 - * 2) 240Kb of SRAM1 beginning at address 0x2001:0000 - * 3) 16Kb of SRAM2 beginning at address 0x2004:c000 + * 1) 64 KiB of DTCM SRM beginning at address 0x2000:0000 + * 2) 240 KiB of SRAM1 beginning at address 0x2001:0000 + * 3) 16 KiB of SRAM2 beginning at address 0x2004:c000 * * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 * where the code expects to begin execution by jumping to the entry point in diff --git a/configs/nucleo-144/scripts/f767-flash.ld b/configs/nucleo-144/scripts/f767-flash.ld new file mode 100644 index 0000000000..6654a139fe --- /dev/null +++ b/configs/nucleo-144/scripts/f767-flash.ld @@ -0,0 +1,146 @@ +/**************************************************************************** + * configs/nucleo-144/scripts/f767-flash.ld + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F767ZIT6 has 2048 KiB of main FLASH memory. This FLASH memory + * can be accessed from either the AXIM interface at address 0x0800:0000 or + * from the ITCM interface at address 0x0020:0000. + * + * Additional information, including the option bytes, is available at at + * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * + * In the STM32F767ZIT6, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash on ITCM at 0x0020:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x0010:0000 + * + * NuttX does not modify these option byes. On the unmodified NUCLEO-144 + * board, the BOOT0 pin is at ground so by default, the STM32F767ZIT6 will + * boot from address 0x0020:0000 in ITCM FLASH. + * + * The STM32F767ZIT6 also has 512 KiB of data SRAM (in addition to ITCM SRAM). + * SRAM is split up into three blocks: + * + * 1) 128 KiB of DTCM SRM beginning at address 0x2000:0000 + * 2) 368 KiB of SRAM1 beginning at address 0x2002:0000 + * 3) 16 KiB of SRAM2 beginning at address 0x2007:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 2048K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + sram1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K + sram2 (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram1 AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram1 + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/nucleo-144/src/Makefile b/configs/nucleo-144/src/Makefile index 2f742b273b..e179c34a7b 100644 --- a/configs/nucleo-144/src/Makefile +++ b/configs/nucleo-144/src/Makefile @@ -3,6 +3,7 @@ # # Copyright (C) 2015 Gregory Nutt. All rights reserved. # Author: Gregory Nutt +# David Sidrane # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -36,7 +37,7 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c stm32_spi.c +CSRCS = stm32_boot.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c @@ -52,4 +53,12 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(HAVE_SDIO),y) +CSRCS += stm32_sdio.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h index a5766c4497..3e35c0821a 100644 --- a/configs/nucleo-144/src/nucleo-144.h +++ b/configs/nucleo-144/src/nucleo-144.h @@ -1,9 +1,10 @@ -/**************************************************************************************************** +/************************************************************************************ * configs/nucleo-144/src/nucleo-144.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Author: Mark Olsson + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -32,22 +33,25 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************************/ + ************************************************************************************/ #ifndef __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H #define __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H -/**************************************************************************************************** +/************************************************************************************ * Included Files - ****************************************************************************************************/ + ************************************************************************************/ #include #include #include -/**************************************************************************************************** +/************************************************************************************ * Pre-processor Definitions - ****************************************************************************************************/ + ************************************************************************************/ + +/* Configuration ********************************************************************/ + /* procfs File System */ #ifdef CONFIG_FS_PROCFS @@ -58,49 +62,128 @@ # endif #endif -/* STM32F736G Discovery GPIOs ***********************************************************************/ -/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the reset button, that - * can be controlled by software (LD2 is a power indicator, LD3-6 indicate USB status, LD7 is - * controlled by the ST-Link). +/* Nucleo-144 GPIO Pin Definitions **************************************************/ +/* LED * - * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface. One end of LD1 is - * grounded so a high output on PI1 will illuminate the LED. + * The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a + * Blue LED and LD3 a Red LED, that can be controlled by software. The following definitions assume + * the default Solder Bridges are installed. */ -#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTB | GPIO_PIN0) -#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTB | GPIO_PIN7) -#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTB | GPIO_PIN14) +#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTB | GPIO_PIN0) +#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTB | GPIO_PIN7) +#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTB | GPIO_PIN14) + +#define GPIO_LED_GREEN GPIO_LD1 +#define GPIO_LED_BLUE GPIO_LD2 +#define GPIO_LED_RED GPIO_LD3 #define LED_DRIVER_PATH "/dev/userleds" -/* Pushbutton B1, labelled "User", is connected to GPIO PC13. A high value will be sensed when the - * button is depressed. Note that the EXTI interrupt is configured. +/* BUTTONS + * + * The Blue pushbutton B1, labeled "User", is connected to GPIO PC13. A high value + * will be sensed when the button is depressed. + * Note: + * 1) That the EXTI is included in the definition to enable an interrupt on this + * IO. + * 2) The following definitions assume the default Solder Bridges are installed. */ -#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) +#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) -/**************************************************************************************************** +/* SPI *************************************************************************** + * + */ +#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET) + +#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN15) +#define GPIO_SPI1_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13) +#define GPIO_SPI1_CS2 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13) +#define GPIO_SPI1_CS3 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN14) +#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTD | GPIO_PIN7) +#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN15) +#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN2) +#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN3) +#define GPIO_SPI3_CS0 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN4) +#define GPIO_SPI3_CS1 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN5) +#define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) +#define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) + +/* Logical SPI Chip Selects used to index */ + +#define NUCLEO_SPI_BUS1_CS0 0 +#define NUCLEO_SPI_BUS1_CS1 1 +#define NUCLEO_SPI_BUS1_CS2 2 +#define NUCLEO_SPI_BUS1_CS3 3 +#define NUCLEO_SPI_BUS2_CS0 4 +#define NUCLEO_SPI_BUS2_CS1 5 +#define NUCLEO_SPI_BUS2_CS2 6 +#define NUCLEO_SPI_BUS2_CS3 7 +#define NUCLEO_SPI_BUS3_CS0 8 +#define NUCLEO_SPI_BUS3_CS1 9 +#define NUCLEO_SPI_BUS3_CS2 10 +#define NUCLEO_SPI_BUS3_CS3 11 + +#if defined(CONFIG_STM32_SDIO) +#define GPIO_SDIO_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTB | GPIO_PIN15) +#endif + +/************************************************************************************ * Public data - ****************************************************************************************************/ + ************************************************************************************/ #ifndef __ASSEMBLY__ -/**************************************************************************************************** +/************************************************************************************ * Public Functions - ****************************************************************************************************/ + ************************************************************************************/ -/**************************************************************************************************** +/************************************************************************************ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f746g-disco board. + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. * - ****************************************************************************************************/ + ************************************************************************************/ -void weak_function stm32_spidev_initialize(void); +#if defined(CONFIG_SPI) +void stm32_spidev_initialize(void); +#endif + +/************************************************************************************ + * Name: stm32_spidev_bus_test + * + * Description: + * Called to create the defined SPI buses and test them by initializing them + * and sending the NUCLEO_SPI_TEST (no chip select). + * + ************************************************************************************/ + +#if defined(NUCLEO_SPI_TEST) +int stm32_spidev_bus_test(void); +#endif + +/************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ************************************************************************************/ + +void stm32_dma_alloc_init(void); + +#if defined (CONFIG_FAT_DMAMEMORY) +int stm32_dma_alloc_init(void); +#endif #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */ diff --git a/configs/nucleo-144/src/stm32_appinitialize.c b/configs/nucleo-144/src/stm32_appinitialize.c index e1b318684c..df411ad94e 100644 --- a/configs/nucleo-144/src/stm32_appinitialize.c +++ b/configs/nucleo-144/src/stm32_appinitialize.c @@ -2,8 +2,9 @@ * config/nucleo-144/src/stm32_appinitilaize.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Author: Mark Olsson + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -39,6 +40,8 @@ ****************************************************************************/ #include + +#include #include #include "nucleo-144.h" @@ -75,9 +78,20 @@ int board_app_initialize(uintptr_t arg) { -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) int ret; +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) /* Register the LED driver */ ret = userled_lower_initialize(LED_DRIVER_PATH); @@ -87,5 +101,36 @@ int board_app_initialize(uintptr_t arg) } #endif +#if defined(CONFIG_FAT_DMAMEMORY) + if (stm32_dma_alloc_init() < 0) + { + syslog(LOG_ERR, "DMA alloc FAILED"); + } +#endif + +#if defined(CONFIG_NUCLEO_SPI_TEST) + /* Create SPI interfaces */ + + ret = stm32_spidev_bus_init(); + if (ret != OK) + { + fdbg("ERROR: Failed to initialize SPI interfaces: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_MMCSD) + /* Configure SDIO */ + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + fdbg("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/nucleo-144/src/stm32_autoleds.c b/configs/nucleo-144/src/stm32_autoleds.c index e9114391af..e78621c904 100644 --- a/configs/nucleo-144/src/stm32_autoleds.c +++ b/configs/nucleo-144/src/stm32_autoleds.c @@ -2,7 +2,8 @@ * configs/nucleo-144/src/stm32_autoleds.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,10 +44,10 @@ #include #include +#include #include "stm32_gpio.h" #include "nucleo-144.h" - #ifdef CONFIG_ARCH_LEDS /**************************************************************************** @@ -65,6 +66,34 @@ # define ledvdbg(x...) #endif +#define ArraySize(x) (sizeof((x)) / sizeof((x)[0])) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -75,9 +104,14 @@ void board_autoled_initialize(void) { + int i; + /* Configure the LD1 GPIO for output. Initial state is OFF */ - stm32_configgpio(GPIO_LD1); + for (i = 0; i < ArraySize(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } } /**************************************************************************** @@ -86,28 +120,47 @@ void board_autoled_initialize(void) void board_autoled_on(int led) { - bool ledstate = false; - switch (led) { - case 0: /* LED_STARTED: NuttX has been started STATUS LED=OFF */ - /* LED_HEAPALLOCATE: Heap has been allocated STATUS LED=OFF */ - /* LED_IRQSENABLED: Interrupts enabled STATUS LED=OFF */ - break; /* Leave ledstate == true to turn OFF */ - default: - case 2: /* LED_INIRQ: In an interrupt STATUS LED=N/C */ - /* LED_SIGNAL: In a signal handler STATUS LED=N/C */ - /* LED_ASSERTION: An assertion failed STATUS LED=N/C */ - return; /* Return to leave STATUS LED unchanged */ - - case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */ - case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */ - ledstate = true; /* Set ledstate == false to turn ON */ break; - } - stm32_gpiowrite(GPIO_LD1, ledstate); + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } } /**************************************************************************** @@ -118,26 +171,29 @@ void board_autoled_off(int led) { switch (led) { - /* These should not happen and are ignored */ - default: - case 0: /* LED_STARTED: NuttX has been started STATUS LED=OFF */ - /* LED_HEAPALLOCATE: Heap has been allocated STATUS LED=OFF */ - /* LED_IRQSENABLED: Interrupts enabled STATUS LED=OFF */ - case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */ - - /* These result in no-change */ - - case 2: /* LED_INIRQ: In an interrupt STATUS LED=N/C */ - /* LED_SIGNAL: In a signal handler STATUS LED=N/C */ - /* LED_ASSERTION: An assertion failed STATUS LED=N/C */ - return; /* Return to leave STATUS LED unchanged */ - - /* Turn STATUS LED off set driving the output high */ - - case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */ - stm32_gpiowrite(GPIO_LD1, false); break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; } } diff --git a/configs/nucleo-144/src/stm32_boot.c b/configs/nucleo-144/src/stm32_boot.c index 210c0982a3..87286e934d 100644 --- a/configs/nucleo-144/src/stm32_boot.c +++ b/configs/nucleo-144/src/stm32_boot.c @@ -2,7 +2,8 @@ * configs/nucleo-144/src/stm32_boot.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -63,24 +64,17 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ board_autoled_initialize(); #endif + +#if defined(CONFIG__SPI) + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif } /************************************************************************************ diff --git a/configs/nucleo-144/src/stm32_buttons.c b/configs/nucleo-144/src/stm32_buttons.c index 54a7dafbfb..c2d16e50b1 100644 --- a/configs/nucleo-144/src/stm32_buttons.c +++ b/configs/nucleo-144/src/stm32_buttons.c @@ -2,7 +2,8 @@ * configs/nucleo-144/src/stm32_buttons.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -102,7 +103,14 @@ uint8_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS xcpt_t board_button_irq(int id, xcpt_t irqhandler) { -#warning Missing logic + xcpt_t oldhandler = NULL; + + if (id == BUTTON_USER) + { + oldhandler = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler); + } + + return oldhandler; } #endif #endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/nucleo-144/src/stm32_dma_alloc.c b/configs/nucleo-144/src/stm32_dma_alloc.c new file mode 100644 index 0000000000..7ce0af1790 --- /dev/null +++ b/configs/nucleo-144/src/stm32_dma_alloc.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * configs/nucleo-144/stc/stm32_dma_alloc.c + * + * Copyright (C) 2016 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include +#include + +#include "nucleo-144.h" + +#if defined(CONFIG_FAT_DMAMEMORY) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if !defined(CONFIG_GRAN) +# error microSD DMA support requires CONFIG_GRAN +#endif + +#define BOARD_DMA_ALLOC_POOL_SIZE (8*512) + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static GRAN_HANDLE dma_allocator; + +/* The DMA heap size constrains the total number of things that can be + * ready to do DMA at a time. + * + * For example, FAT DMA depends on one sector-sized buffer per filesystem plus + * one sector-sized buffer per file. + * + * We use a fundamental alignment / granule size of 64B; this is sufficient + * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits). + */ + +static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * All boards may optionally provide this API to instantiate a pool of + * memory for uses with FAST FS DMA operations. + * + ************************************************************************************/ + +int stm32_dma_alloc_init(void) +{ + dma_allocator = gran_initialize(g_dma_heap, + sizeof(g_dma_heap), + 7, /* 128B granule - must be > alignment (XXX bug?) */ + 6); /* 64B alignment */ + + if (dma_allocator == NULL) + { + return -ENOMEM; + } + + return OK; +} + +/* DMA-aware allocator stubs for the FAT filesystem. */ + +void *fat_dma_alloc(size_t size) +{ + return gran_alloc(dma_allocator, size); +} + +void fat_dma_free(FAR void *memory, size_t size) +{ + gran_free(dma_allocator, memory, size); +} + +#endif /* CONFIG_FAT_DMAMEMORY */ diff --git a/configs/nucleo-144/src/stm32_sdio.c b/configs/nucleo-144/src/stm32_sdio.c new file mode 100644 index 0000000000..21c5d2eafd --- /dev/null +++ b/configs/nucleo-144/src/stm32_sdio.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * config/nucleo-144/src/stm32_sdio.c + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-144.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(CONFIG_STM32_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static FAR struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted = 0xff; /* Impossible value */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, FAR void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Card detect */ + + bool cd_status; + + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ + + fvdbg("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + fdbg("Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + fvdbg("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + fdbg("Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + fvdbg("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + cd_status = !stm32_gpioread(GPIO_SDIO_NCD); + fvdbg("Card detect : %d\n", cd_status); + + sdio_mediachange(g_sdio_dev, cd_status); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/configs/nucleo-144/src/stm32_spi.c b/configs/nucleo-144/src/stm32_spi.c index e31a63a11d..906815d532 100644 --- a/configs/nucleo-144/src/stm32_spi.c +++ b/configs/nucleo-144/src/stm32_spi.c @@ -3,6 +3,7 @@ * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -49,13 +50,12 @@ #include "up_arch.h" #include "chip.h" +#include "stm32_gpio.h" #include "stm32_spi.h" #include "nucleo-144.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_SPI) /************************************************************************************ * Pre-processor Definitions @@ -74,6 +74,108 @@ # define spivdbg(x...) #endif +#define ArraySize(x) (sizeof((x)) / sizeof((x)[0])) + +#if defined(CONFIG_NUCLEO_SPI1_TEST) +# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) +# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) +# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" +# endif +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Indexed by NUCLEO_SPI_BUSx_CSx */ + +static const uint32_t g_spigpio[] = +{ +#if defined(GPIO_SPI1_CS0) + GPIO_SPI1_CS0, +#endif +#if defined(GPIO_SPI1_CS1) + GPIO_SPI1_CS1, +#endif +#if defined(GPIO_SPI1_CS2) + GPIO_SPI1_CS2, +#endif +#if defined(GPIO_SPI1_CS3) + GPIO_SPI1_CS3, +#endif +#if defined(GPIO_SPI2_CS0) + GPIO_SPI2_CS0, +#endif +#if defined(GPIO_SPI2_CS1) + GPIO_SPI2_CS1, +#endif +#if defined(GPIO_SPI2_CS2) + GPIO_SPI2_CS2, +#endif +#if defined(GPIO_SPI2_CS3) + GPIO_SPI2_CS3, +#endif +#if defined(GPIO_SPI3_CS0) + GPIO_SPI3_CS0, +#endif +#if defined(GPIO_SPI3_CS1) + GPIO_SPI3_CS1, +#endif +#if defined(GPIO_SPI3_CS2) + GPIO_SPI3_CS2, +#endif +#if defined(GPIO_SPI3_CS3) + GPIO_SPI3_CS3, +#endif +}; + +#if defined(CONFIG_NUCLEO_SPI_TEST) +# if defined(CONFIG_STM32F7_SPI1) +struct spi_dev_s *spi1; +# endif +# if defined(CONFIG_STM32F7_SPI2) +struct spi_dev_s *spi2; +# endif +# if defined(CONFIG_STM32F7_SPI3) +struct spi_dev_s *spi3; +# endif +#endif + /************************************************************************************ * Public Functions ************************************************************************************/ @@ -82,12 +184,20 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f746g-disco board. + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. * ************************************************************************************/ void weak_function stm32_spidev_initialize(void) { + int i; + + /* Configure SPI CS GPIO for output */ + + for (i = 0; i < ArraySize(g_spigpio); i++) + { + stm32_configgpio(g_spigpio[i]); + } } /**************************************************************************** @@ -119,6 +229,7 @@ void weak_function stm32_spidev_initialize(void) void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[i], !selected); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -131,6 +242,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[i], !selected); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -143,6 +255,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[i], !selected); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -152,9 +265,14 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #endif #ifdef CONFIG_STM32F7_SPI4 +# ifndef NUCLEO_SPI_BUS4_CS0 +# error "NUCLEO_SPI_BUS4_CSn Are not defined" +# endif + void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[i], !selected); } uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -164,9 +282,30 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #endif #ifdef CONFIG_STM32F7_SPI5 +# ifndef NUCLEO_SPI_BUS5_CS0 +# error "NUCLEO_SPI_BUS4_CSn Are not defined" +# endif + void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[i], !selected); +} + +uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32F7_SPI6 +# ifndef NUCLEO_SPI_BUS6_CS +# error "NUCLEO_SPI_BUS4_CSn Are not defined" +# endif +void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[i], !selected); } uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -234,5 +373,72 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) } #endif +#ifdef CONFIG_STM32F7_SPI6 +int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd) +{ + return -ENODEV; +} +#endif + #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ + +#if defined(CONFIG_NUCLEO_SPI_TEST) +int stm32_spidev_bus_init(void) +{ + /* Configure and test SPI-*/ + + uint8_t *tx = CONFIG_NUCLEO_SPI_TEST_MESSAGE; + +#if defined(CONFIG_NUCLEO_SPI1_TEST) + spi1 = stm32_spibus_initialize(1); + + if (!spi1) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ + + SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); + SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); + SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); + SPI_EXCHANGE(spi1, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) + spi2 = stm32_spibus_initialize(2); + + if (!spi2) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI1 to NUCLEO_SPI2_FREQ and mode */ + + SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI1_TEST_FREQ); + SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); + SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); + SPI_EXCHANGE(spi2, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) + spi3 = stm32_spibus_initialize(3); + + if (!spi3) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI1 to NUCLEO_SPI3_FREQ and mode */ + + SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); + SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); + SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); + SPI_EXCHANGE(spi3, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif +} +#endif /* NUCLEO_SPI_TEST */ +#endif /* defined(CONFIG_SPI) */ diff --git a/configs/nucleo-144/src/stm32_userleds.c b/configs/nucleo-144/src/stm32_userleds.c index 4ec9f20947..a2e4577f15 100644 --- a/configs/nucleo-144/src/stm32_userleds.c +++ b/configs/nucleo-144/src/stm32_userleds.c @@ -2,8 +2,9 @@ * configs/nucleo-144/src/stm32_userleds.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Author: Mark Olsson + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,6 +44,7 @@ #include #include +#include #include #include "stm32_gpio.h" @@ -66,15 +68,21 @@ # define ledvdbg(x...) #endif +#define ArraySize(x) (sizeof((x)) / sizeof((x)[0])) + /**************************************************************************** * Private Data ****************************************************************************/ -/* This array maps an LED number to GPIO pin configuration */ +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ -static const uint32_t g_ledcfg[3] = +static const uint32_t g_ledcfg[BOARD_NLEDS] = { - GPIO_LD1, GPIO_LD2, GPIO_LD3 + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, }; /**************************************************************************** @@ -98,7 +106,7 @@ void board_userled_initialize(void) /* Configure LED1-3 GPIOs for output */ - for (i = 0; i < 3; i++) + for (i = 0; i < ArraySize(g_ledcfg); i++) { stm32_configgpio(g_ledcfg[i]); } @@ -116,10 +124,10 @@ void board_userled_initialize(void) void board_userled(int led, bool ledon) { - if ((unsigned)led < 3) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } + if ((unsigned)led < ArraySize(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } } /**************************************************************************** @@ -139,7 +147,7 @@ void board_userled_all(uint8_t ledset) /* Configure LED1-3 GPIOs for output */ - for (i = 0; i < 3; i++) + for (i = 0; i < ArraySize(g_ledcfg); i++) { stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } From 061b4e2aaac5de86fb13ac939689b41d51b7d324 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 8 Jun 2016 07:54:48 -0600 Subject: [PATCH 12/18] Refresh Configuration --- configs/nucleo-144/f746-evalos/defconfig | 181 ++++++++++++++++++----- 1 file changed, 145 insertions(+), 36 deletions(-) diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index 9944952cac..4c63ce773c 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -24,7 +24,7 @@ CONFIG_BUILD_FLAT=y # Binary Output Formats # # CONFIG_RRLOAD_BINARY is not set -CONFIG_INTELHEX_BINARY=y +# CONFIG_INTELHEX_BINARY is not set # CONFIG_MOTOROLA_SREC is not set CONFIG_RAW_BINARY=y # CONFIG_UBOOT_UIMAGE is not set @@ -45,7 +45,7 @@ CONFIG_RAW_BINARY=y # CONFIG_DEBUG is not set CONFIG_ARCH_HAVE_HEAPCHECK=y CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set +CONFIG_STACK_COLORATION=y CONFIG_DEBUG_SYMBOLS=y CONFIG_ARCH_HAVE_CUSTOMOPT=y CONFIG_DEBUG_NOOPT=y @@ -124,7 +124,7 @@ CONFIG_ARCH_HAVE_CMNVECTOR=y CONFIG_ARMV7M_CMNVECTOR=y # CONFIG_ARMV7M_LAZYFPU is not set CONFIG_ARCH_HAVE_FPU=y -CONFIG_ARCH_HAVE_DPFPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set # CONFIG_ARCH_FPU is not set # CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y @@ -152,23 +152,117 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set # CONFIG_USART3_RS485 is not set -# CONFIG_SERIAL_DISABLE_REORDERING is not set +CONFIG_SERIAL_DISABLE_REORDERING=y # # STM32 F7 Configuration Options # -# CONFIG_ARCH_CHIP_STM32F745 is not set -CONFIG_ARCH_CHIP_STM32F746=y -# CONFIG_ARCH_CHIP_STM32F756 is not set +# CONFIG_ARCH_CHIP_STM32F745VG is not set +# CONFIG_ARCH_CHIP_STM32F745VE is not set +# CONFIG_ARCH_CHIP_STM32F745IG is not set +# CONFIG_ARCH_CHIP_STM32F745IE is not set +# CONFIG_ARCH_CHIP_STM32F745ZE is not set +# CONFIG_ARCH_CHIP_STM32F745ZG is not set +# CONFIG_ARCH_CHIP_STM32F746BG is not set +# CONFIG_ARCH_CHIP_STM32F746VG is not set +# CONFIG_ARCH_CHIP_STM32F746VE is not set +# CONFIG_ARCH_CHIP_STM32F746BE is not set +CONFIG_ARCH_CHIP_STM32F746ZG=y +# CONFIG_ARCH_CHIP_STM32F746IE is not set +# CONFIG_ARCH_CHIP_STM32F746NG is not set +# CONFIG_ARCH_CHIP_STM32F746NE is not set +# CONFIG_ARCH_CHIP_STM32F746ZE is not set +# CONFIG_ARCH_CHIP_STM32F746IG is not set +# CONFIG_ARCH_CHIP_STM32F756NG is not set +# CONFIG_ARCH_CHIP_STM32F756BG is not set +# CONFIG_ARCH_CHIP_STM32F756IG is not set +# CONFIG_ARCH_CHIP_STM32F756VG is not set +# CONFIG_ARCH_CHIP_STM32F756ZG is not set +# CONFIG_ARCH_CHIP_STM32F765NI is not set +# CONFIG_ARCH_CHIP_STM32F765VI is not set +# CONFIG_ARCH_CHIP_STM32F765VG is not set +# CONFIG_ARCH_CHIP_STM32F765BI is not set +# CONFIG_ARCH_CHIP_STM32F765NG is not set +# CONFIG_ARCH_CHIP_STM32F765ZG is not set +# CONFIG_ARCH_CHIP_STM32F765ZI is not set +# CONFIG_ARCH_CHIP_STM32F765IG is not set +# CONFIG_ARCH_CHIP_STM32F765BG is not set +# CONFIG_ARCH_CHIP_STM32F765II is not set +# CONFIG_ARCH_CHIP_STM32F767NG is not set +# CONFIG_ARCH_CHIP_STM32F767IG is not set +# CONFIG_ARCH_CHIP_STM32F767VG is not set +# CONFIG_ARCH_CHIP_STM32F767ZG is not set +# CONFIG_ARCH_CHIP_STM32F767NI is not set +# CONFIG_ARCH_CHIP_STM32F767VI is not set +# CONFIG_ARCH_CHIP_STM32F767BG is not set +# CONFIG_ARCH_CHIP_STM32F767ZI is not set +# CONFIG_ARCH_CHIP_STM32F767II is not set +# CONFIG_ARCH_CHIP_STM32F769BI is not set +# CONFIG_ARCH_CHIP_STM32F769II is not set +# CONFIG_ARCH_CHIP_STM32F769BG is not set +# CONFIG_ARCH_CHIP_STM32F769NI is not set +# CONFIG_ARCH_CHIP_STM32F769AI is not set +# CONFIG_ARCH_CHIP_STM32F769NG is not set +# CONFIG_ARCH_CHIP_STM32F769IG is not set +# CONFIG_ARCH_CHIP_STM32F777ZI is not set +# CONFIG_ARCH_CHIP_STM32F777VI is not set +# CONFIG_ARCH_CHIP_STM32F777NI is not set +# CONFIG_ARCH_CHIP_STM32F777BI is not set +# CONFIG_ARCH_CHIP_STM32F777II is not set +# CONFIG_ARCH_CHIP_STM32F778AI is not set +# CONFIG_ARCH_CHIP_STM32F779II is not set +# CONFIG_ARCH_CHIP_STM32F779NI is not set +# CONFIG_ARCH_CHIP_STM32F779BI is not set +# CONFIG_ARCH_CHIP_STM32F779AI is not set CONFIG_STM32F7_STM32F74XX=y # CONFIG_STM32F7_STM32F75XX is not set -# CONFIG_STM32F7_FLASH_512KB is not set -CONFIG_STM32F7_FLASH_1024KB=y +# CONFIG_STM32F7_STM32F76XX is not set +# CONFIG_STM32F7_STM32F77XX is not set +# CONFIG_STM32F7_IO_CONFIG_V is not set +# CONFIG_STM32F7_IO_CONFIG_I is not set +CONFIG_STM32F7_IO_CONFIG_Z=y +# CONFIG_STM32F7_IO_CONFIG_N is not set +# CONFIG_STM32F7_IO_CONFIG_B is not set +# CONFIG_STM32F7_IO_CONFIG_A is not set +# CONFIG_STM32F7_STM32F745XX is not set +CONFIG_STM32F7_STM32F746XX=y +# CONFIG_STM32F7_STM32F756XX is not set +# CONFIG_STM32F7_STM32F765XX is not set +# CONFIG_STM32F7_STM32F767XX is not set +# CONFIG_STM32F7_STM32F768XX is not set +# CONFIG_STM32F7_STM32F768AX is not set +# CONFIG_STM32F7_STM32F769XX is not set +# CONFIG_STM32F7_STM32F769AX is not set +# CONFIG_STM32F7_STM32F777XX is not set +# CONFIG_STM32F7_STM32F778XX is not set +# CONFIG_STM32F7_STM32F778AX is not set +# CONFIG_STM32F7_STM32F779XX is not set +# CONFIG_STM32F7_STM32F779AX is not set +# CONFIG_STM32F7_FLASH_CONFIG_E is not set +# CONFIG_STM32F7_FLASH_CONFIG_I is not set +CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y +# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set # # STM32 Peripheral Support # CONFIG_STM32F7_HAVE_LTDC=y +CONFIG_STM32F7_HAVE_FSMC=y +CONFIG_STM32F7_HAVE_ETHRNET=y +CONFIG_STM32F7_HAVE_RNG=y +CONFIG_STM32F7_HAVE_SPI5=y +CONFIG_STM32F7_HAVE_SPI6=y +# CONFIG_STM32F7_HAVE_SDMMC2 is not set +# CONFIG_STM32F7_HAVE_CAN3 is not set +CONFIG_STM32F7_HAVE_DCMI=y +# CONFIG_STM32F7_HAVE_DSIHOST is not set +CONFIG_STM32F7_HAVE_DMA2D=y +# CONFIG_STM32F7_HAVE_JPEG is not set +# CONFIG_STM32F7_HAVE_CRYP is not set +# CONFIG_STM32F7_HAVE_HASH is not set +# CONFIG_STM32F7_HAVE_DFSDM1 is not set # CONFIG_STM32F7_ADC is not set # CONFIG_STM32F7_CAN is not set # CONFIG_STM32F7_DAC is not set @@ -185,12 +279,12 @@ CONFIG_STM32F7_USART=y # CONFIG_STM32F7_CAN2 is not set # CONFIG_STM32F7_CEC is not set # CONFIG_STM32F7_CRC is not set -# CONFIG_STM32F7_CRYP is not set # CONFIG_STM32F7_DMA1 is not set # CONFIG_STM32F7_DMA2 is not set # CONFIG_STM32F7_DAC1 is not set # CONFIG_STM32F7_DAC2 is not set # CONFIG_STM32F7_DCMI is not set +# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_ETHMAC is not set # CONFIG_STM32F7_FSMC is not set # CONFIG_STM32F7_I2C1 is not set @@ -198,12 +292,11 @@ CONFIG_STM32F7_USART=y # CONFIG_STM32F7_I2C3 is not set # CONFIG_STM32F7_LPTIM1 is not set # CONFIG_STM32F7_LTDC is not set -# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_OTGFS is not set # CONFIG_STM32F7_OTGHS is not set # CONFIG_STM32F7_QUADSPI is not set -# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_RNG is not set +# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set # CONFIG_STM32F7_SDMMC1 is not set # CONFIG_STM32F7_SPDIFRX is not set @@ -242,8 +335,9 @@ CONFIG_STM32F7_USART3=y # # U[S]ART Configuration # -# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set -# CONFIG_STM32F7_USART_BREAKS is not set +CONFIG_STM32F7_FLOWCONTROL_BROKEN=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set # @@ -308,7 +402,6 @@ CONFIG_RAM_SIZE=245760 # Board Selection # CONFIG_ARCH_BOARD_NUCLEO_144=y -# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="nucleo-144" @@ -326,6 +419,11 @@ CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_NUCLEO_CONSOLE_ARDUINO is not set +CONFIG_NUCLEO_CONSOLE_VIRTUAL=y +# CONFIG_NUCLEO_CONSOLE_MORPHO is not set +# CONFIG_NUCLEO_CONSOLE_NONE is not set +# CONFIG_NUCLEO_SPI_TEST is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -337,12 +435,7 @@ CONFIG_LIB_BOARDCTL=y # # RTOS Features # -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_OS_API is not set # # Clocks and Timers @@ -351,9 +444,9 @@ CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set # CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=12 -CONFIG_START_DAY=6 +CONFIG_START_YEAR=2015 +CONFIG_START_MONTH=11 +CONFIG_START_DAY=30 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=4 CONFIG_WDOG_INTRESERVE=0 @@ -395,7 +488,9 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_SEM_PREALLOCHOLDERS=16 +CONFIG_SEM_NNESTPRIO=16 # # RTOS hooks @@ -404,6 +499,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -412,6 +508,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -423,9 +520,17 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=100000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPNTHREADS=1 +CONFIG_SCHED_LPWORKPRIORITY=50 +CONFIG_SCHED_LPWORKPRIOMAX=176 +CONFIG_SCHED_LPWORKPERIOD=50000 +CONFIG_SCHED_LPWORKSTACKSIZE=2048 # # Stack and heap information @@ -478,7 +583,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set # # LED Support @@ -521,10 +631,6 @@ CONFIG_USART3_SERIALDRIVER=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set - -# -# USART Configuration -# CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set @@ -585,6 +691,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set # CONFIG_FS_READABLE is not set # CONFIG_FS_WRITABLE is not set +# CONFIG_FS_AIO is not set # CONFIG_FS_NAMED_SEMAPHORES is not set CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set @@ -695,10 +802,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -803,6 +906,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -903,6 +1007,10 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # @@ -929,5 +1037,6 @@ CONFIG_READLINE_CMD_HISTORY_LINELEN=80 CONFIG_READLINE_CMD_HISTORY_LEN=16 # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_STACKMONITOR is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_ZMODEM is not set From 86b29dc64c013e67531f4e0452739a0fb893bae5 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 8 Jun 2016 08:02:32 -0600 Subject: [PATCH 13/18] Updated configs/Kconfig --- configs/Kconfig | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/configs/Kconfig b/configs/Kconfig index e4d6ec4e5f..98d4b30b2d 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -649,17 +649,27 @@ config ARCH_BOARD_PIRELLI_DPL10 config ARCH_BOARD_NUCLEO_144 bool "STMicro NUCLEO-144" - depends on ARCH_CHIP_STM32F746 || ARCH_CHIP_STM32F767 + depends on ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS ---help--- - STMicro Nucleo-144 development board family. Included support for (1) the - Nucleo-F767ZG board featuring the STM32F746ZGT6U MCU. The STM32F746ZGT6U - is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM. - And (2) the Nucleo-F746ZG board featuring the STM32F767ZIT6 MCU. The - STM32F767ZIT6 is a 216MHz Cortex-M7 operation with 2048Kb Flash memory - and 512Kb SRAM. + STMicro Nucleo-144 development board featuring STMicroelectronics + F2, F3, F4 and F7 MCU families. The board is a "Hardware pattern" + that can be populated with the 144 pin package of the following MCUs: + + Target STM32 Order code + STM32F207ZGT6 NUCLEO-F207ZG + STM32F303ZET6 NUCLEO-F303ZE + STM32F429ZIT6 NUCLEO-F429ZI + STM32F446ZET6 NUCLEO-F446ZE + + Supported in this release are: + + NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU - 1024KiB + Flash memory and 320KiB SRAM. + NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU - + 2048KiB Flash memory and 512KiB SRAM. config ARCH_BOARD_NUCLEO_F303RE bool "STM32F303 Nucleo F303RE" From d8ea955d6942ce6a22e7b2eb9acba62e489f5ff2 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 8 Jun 2016 08:26:26 -0600 Subject: [PATCH 14/18] Added STM32FF76xxx and STM32FF7xx families --- ChangeLog | 2 + arch/arm/include/stm32f7/chip.h | 297 +++- arch/arm/include/stm32f7/irq.h | 2 + arch/arm/include/stm32f7/stm32f76xx77xx_irq.h | 215 +++ arch/arm/src/stm32f7/Kconfig | 1043 ++++++++++++- arch/arm/src/stm32f7/chip/stm32_dma.h | 5 +- arch/arm/src/stm32f7/chip/stm32_ethernet.h | 8 +- arch/arm/src/stm32f7/chip/stm32_exti.h | 8 +- arch/arm/src/stm32f7/chip/stm32_flash.h | 5 +- arch/arm/src/stm32f7/chip/stm32_gpio.h | 5 +- arch/arm/src/stm32f7/chip/stm32_memorymap.h | 5 +- arch/arm/src/stm32f7/chip/stm32_pinmap.h | 7 +- arch/arm/src/stm32f7/chip/stm32_pwr.h | 5 +- arch/arm/src/stm32f7/chip/stm32_rcc.h | 6 +- arch/arm/src/stm32f7/chip/stm32_syscfg.h | 5 +- arch/arm/src/stm32f7/chip/stm32_uart.h | 9 +- .../arm/src/stm32f7/chip/stm32f74xx75xx_dma.h | 18 +- .../src/stm32f7/chip/stm32f74xx75xx_flash.h | 86 +- .../src/stm32f7/chip/stm32f74xx75xx_gpio.h | 16 - .../stm32f7/chip/stm32f74xx75xx_memorymap.h | 7 +- .../src/stm32f7/chip/stm32f74xx75xx_pinmap.h | 5 +- .../arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h | 6 +- ...f74xx75xx_uart.h => stm32f74xx77xx_uart.h} | 14 +- .../arm/src/stm32f7/chip/stm32f76xx77xx_dma.h | 593 ++++++++ .../src/stm32f7/chip/stm32f76xx77xx_flash.h | 219 +++ .../src/stm32f7/chip/stm32f76xx77xx_gpio.h | 404 +++++ .../stm32f7/chip/stm32f76xx77xx_memorymap.h | 214 +++ .../src/stm32f7/chip/stm32f76xx77xx_pinmap.h | 1343 +++++++++++++++++ .../arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h | 159 ++ .../arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h | 737 +++++++++ .../src/stm32f7/chip/stm32f76xx77xx_syscfg.h | 180 +++ arch/arm/src/stm32f7/stm32_dma.c | 3 +- arch/arm/src/stm32f7/stm32_dumpgpio.c | 3 +- arch/arm/src/stm32f7/stm32_exti_gpio.c | 3 +- arch/arm/src/stm32f7/stm32_gpio.c | 3 +- arch/arm/src/stm32f7/stm32_rcc.c | 5 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 886 +++++++++++ 37 files changed, 6335 insertions(+), 196 deletions(-) create mode 100644 arch/arm/include/stm32f7/stm32f76xx77xx_irq.h rename arch/arm/src/stm32f7/chip/{stm32f74xx75xx_uart.h => stm32f74xx77xx_uart.h} (98%) create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h create mode 100644 arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c diff --git a/ChangeLog b/ChangeLog index b3ea24e379..791c59947d 100755 --- a/ChangeLog +++ b/ChangeLog @@ -11919,6 +11919,8 @@ * include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to _sa_handler_t. They type void does not work with the IAR toolchain. From Aleksandr Vyhovanec (2016-06-07). + * arch/arm/src/stm32f7 and include/stm32f7: Added STM32FF76xxx and + STM32FF7xx families. From David Sidrane (2016-06-08). * Refactoring configs/nucleo-144 sub-directories to support additional nucleo-144 board. Add support for the Nucleo-F767ZI board. From David Sidrane (2016-06-08). diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 372bd1143f..d30937541e 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/stm32f7/chip.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,99 +45,272 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members: +/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx, + * STM32F769xx, STM32F777xx and STM32F779xx Differences between family members: * - * ----------- ---------------- ----- -------- ------------ -------- - * PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT? - * ----------- ---------------- ----- -------- ------------ -------- - * STM32F745Vx LQFP100 82 4/3 16 No - * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No - * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No - * STM32F745Bx LQFP208 168 6/3 24 No - * STM32F745Nx TFBGA216 68 6/3 24 No + * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ + * SPI ADC LCD + * PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1 + * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ + * STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 * - * STM32F746Vx LQFP100 82 4/3 16 Yes - * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes - * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes - * STM32F746Bx LQFP208 168 6/3 24 Yes - * STM32F746Nx TFBGA216 168 6/3 24 Yes + * STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4 + * STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU * - * STM32F756Vx LQFP100 82 4/3 16 Yes - * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes - * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes - * STM32F756Bx LQFP208 168 6/3 24 Yes - * STM32F756Nx TFBGA216 168 6/3 24 Yes - * ----------- ---------------- ----- -------- ------------ -------- + * STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4 + * + * STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16 + * + * STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * + * STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16 + * + * STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16 + * + * STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16 + * + * STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * + * STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16 + * + * STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + * STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16 + + * STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16 + * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH + * Parts STM32F74xxI have 2048Kb of FLASH + * + * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden + * with CONFIG_STM32F7_FLASH_OVERRIDE_x * - * The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB - * selection. */ - -#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \ - defined(CONFIG_ARCH_CHIP_STM32F756) - -#if defined(CONFIG_ARCH_CHIP_STM32F745) -# define STM32F7_STM32F745XX 1 /* STM32F745xx family */ -# undef STM32F7_STM32F746XX /* Not STM32F746xx family */ -# undef STM32F7_STM32F756XX /* Not STM32F756xx family */ - -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F746) - -# undef STM32F7_STM32F745XX /* Not STM32F745xx family */ -# define STM32F7_STM32F746XX 1 /* STM32F746xx family */ -# undef STM32F7_STM32F756XX /* Not STM32F756xx family */ - -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ - -#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */ - -# undef STM32F7_STM32F745XX /* Not STM32F745xx family */ -# undef STM32F7_STM32F746XX /* Not STM32F746xx family */ -# define STM32F7_STM32F756XX 1 /* STM32F756xx family */ - -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F745VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F745IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746BE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F746NE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F746IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765VI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \ + defined(CONFIG_ARCH_CHIP_STM32F765IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F765II) || \ + defined(CONFIG_ARCH_CHIP_STM32F767NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767VG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F767VI) || \ + defined(CONFIG_ARCH_CHIP_STM32F767BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \ + defined(CONFIG_ARCH_CHIP_STM32F767II) || \ + defined(CONFIG_ARCH_CHIP_STM32F769BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F769II) || \ + defined(CONFIG_ARCH_CHIP_STM32F769BG) || \ + defined(CONFIG_ARCH_CHIP_STM32F769NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F769AI) || \ + defined(CONFIG_ARCH_CHIP_STM32F769NG) || \ + defined(CONFIG_ARCH_CHIP_STM32F769IG) || \ + defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777VI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F777II) || \ + defined(CONFIG_ARCH_CHIP_STM32F778AI) || \ + defined(CONFIG_ARCH_CHIP_STM32F779II) || \ + defined(CONFIG_ARCH_CHIP_STM32F779NI) || \ + defined(CONFIG_ARCH_CHIP_STM32F779BI) || \ + defined(CONFIG_ARCH_CHIP_STM32F779AI) +#else +# error STM32 F7 chip not identified #endif -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */ -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */ +/* Size SRAM */ + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# if defined(CONFIG_ARMV7M_HAVE_DTCM) +# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# else +# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# endif +# if defined(CONFIG_ARMV7M_HAVE_ITCM) +# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# else +# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# endif +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X) +# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# if defined(CONFIG_ARMV7M_HAVE_DTCM) +# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# else +# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# endif +# if defined(CONFIG_ARMV7M_HAVE_ITCM) +# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# else +# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# endif +#else +# error STM32 F7 chip Family not identified +#endif + +/* Common to all Family members */ -# define STM32F7_NFSMC 1 /* Have FSMC memory controller */ -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ # define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ # define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ # define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ # define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ # define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ # define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */ # define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ # define STM32F7_NI2C 4 /* I2C1-4 */ # define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ # define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NCAN 2 /* CAN1-2 */ # define STM32F7_NSAI 2 /* SAI1-2 */ # define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NSDMMC 1 /* SDMMC interface */ -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ # define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ # define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ # define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */ # define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ # define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32F7_NCRC 1 /* CRC */ +/* TBD FPU Configuration */ + +#if defined(CONFIG_ARCH_HAVE_FPU) #else -# error STM32 F7 chip not identified +#endif + +#if defined(CONFIG_ARCH_HAVE_DPFPU) +#else +#endif + +/* Diversification based on Family and package */ + +#if defined(CONFIG_STM32F7_HAVE_FSMC) +# define STM32F7_NFSMC 1 /* Have FSMC memory controller */ +#else +# define STM32F7_NFSMC 0 /* No FSMC memory controller */ +#endif +#if defined(CONFIG_STM32F7_HAVE_ETHRNET) +# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +#else +# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +#endif +#if defined(CONFIG_STM32F7_HAVE_RNG) +# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +#else +# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +#endif +#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) +# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */ +#else +# define STM32F7_NSPI 4 /* SPI1-4 V series */ +#endif +#if defined(CONFIG_STM32F7_HAVE_SDMMC2) +# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +#else +# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +#endif +#if defined(CONFIG_STM32F7_HAVE_CAN3) +# define STM32F7_NCAN 3 /* CAN1-3 */ +#else +# define STM32F7_NCAN 2 /* CAN1-2 */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DCMI) +# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +#else +# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DSIHOST) +# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +#else +# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +#endif +#if defined (CONFIG_STM32F7_HAVE_LTDC) +# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +#else +# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DMA2D) +# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +#else +# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +#endif +#if defined(CONFIG_STM32F7_HAVE_JPEG) +#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#else +#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#endif +#if defined(CONFIG_STM32F7_HAVE_CRYP) +#define STM32F7_NCRYP 1 /* One CRYP engine */ +#else +#define STM32F7_NCRYP 0 /* No CRYP engine */ +#endif +#if defined(CONFIG_STM32F7_HAVE_HASH) +#define STM32F7_NHASH 1 /* One HASH engine */ +#else +#define STM32F7_NHASH 0 /* No HASH engine */ +#endif +#if defined(CONFIG_STM32F7_HAVE_DFSDM) +#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#else +#define STM32F7_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *************************************************************/ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index 5a5c710803..205d06b644 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -78,6 +78,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include #else # error "Unsupported STM32 F7 chip" #endif diff --git a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h new file mode 100644 index 0000000000..6c0461f9ef --- /dev/null +++ b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h @@ -0,0 +1,215 @@ +/**************************************************************************************************** + * arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through arch/irq.h */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the + * NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found in the file + * nuttx/arch/arm/include/stm32f7/irq.h which includes this file + * + * External interrupts (vectors >= 16) + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ +#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ +#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */ +#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ +#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */ +#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */ +#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */ +#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */ +#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */ +#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */ +#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */ +#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */ +#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */ +#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */ +#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */ +#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */ +#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */ +#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */ +#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */ +#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */ +#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */ +#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */ +#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */ +#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */ +#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */ +#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */ + +#define NR_INTERRUPTS 110 +#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS) + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index e3a8d2b42c..e77c028ec0 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -12,59 +12,915 @@ choice default ARCH_CHIP_STM32F746 depends on ARCH_CHIP_STM32F7 -config ARCH_CHIP_STM32F745 - bool "STM32F745xx" - select STM32F7_STM32F74XX +config ARCH_CHIP_STM32F745VG + bool "STM32F745VG" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V ---help--- - STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM -config ARCH_CHIP_STM32F746 - bool "STM32F746xx" - select STM32F7_STM32F74XX - select STM32F7_HAVE_LTDC +config ARCH_CHIP_STM32F745VE + bool "STM32F745VE" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_V ---help--- - STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + STM32 F7 Cortex M7, 512 320K FLASH, 320K (240+16+64) Kb SRAM -config ARCH_CHIP_STM32F756 - bool "STM32F756xx" - select STM32F7_STM32F75XX - select STM32F7_HAVE_LTDC +config ARCH_CHIP_STM32F745IG + bool "STM32F745IG" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I ---help--- - STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F745IE + bool "STM32F745IE" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F745ZE + bool "STM32F745ZE" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F745ZG + bool "STM32F745ZG" + select STM32F7_STM32F745XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746BG + bool "STM32F746BG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746VG + bool "STM32F746VG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746VE + bool "STM32F746VE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746BE + bool "STM32F746BE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746ZG + bool "STM32F746ZG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746IE + bool "STM32F746IE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746NG + bool "STM32F746NG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746NE + bool "STM32F746NE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746ZE + bool "STM32F746ZE" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F746IG + bool "STM32F746IG" + select STM32F7_STM32F746XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756NG + bool "STM32F756NG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756BG + bool "STM32F756BG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756IG + bool "STM32F756IG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756VG + bool "STM32F756VG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F756ZG + bool "STM32F756ZG" + select STM32F7_STM32F756XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM + +config ARCH_CHIP_STM32F765NI + bool "STM32F765NI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765VI + bool "STM32F765VI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765VG + bool "STM32F765VG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765BI + bool "STM32F765BI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765NG + bool "STM32F765NG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765ZG + bool "STM32F765ZG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765ZI + bool "STM32F765ZI" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765IG + bool "STM32F765IG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765BG + bool "STM32F765BG" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F765II + bool "STM32F765II" + select STM32F7_STM32F765XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767NG + bool "STM32F767NG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767IG + bool "STM32F767IG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767VG + bool "STM32F767VG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767ZG + bool "STM32F767ZG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767NI + bool "STM32F767NI" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767VI + bool "STM32F767VI" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767BG + bool "STM32F767BG" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767ZI + bool "STM32F767ZI" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F767II + bool "STM32F767II" + select STM32F7_STM32F767XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769BI + bool "STM32F769BI" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769II + bool "STM32F769II" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769BG + bool "STM32F769BG" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769NI + bool "STM32F769NI" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769AI + bool "STM32F769AI" + select STM32F7_STM32F769AX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_A + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769NG + bool "STM32F769NG" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F769IG + bool "STM32F769IG" + select STM32F7_STM32F769XX + select STM32F7_FLASH_CONFIG_G + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777ZI + bool "STM32F777ZI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777VI + bool "STM32F777VI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777NI + bool "STM32F777NI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777BI + bool "STM32F777BI" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F777II + bool "STM32F777II" + select STM32F7_STM32F777XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F778AI + bool "STM32F778AI" + select STM32F7_STM32F778AX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_A + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779II + bool "STM32F779II" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779NI + bool "STM32F779NI" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_N + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779BI + bool "STM32F779BI" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_B + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM + +config ARCH_CHIP_STM32F779AI + bool "STM32F779AI" + select STM32F7_STM32F779XX + select STM32F7_FLASH_CONFIG_I + select STM32F7_IO_CONFIG_A + ---help--- + STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM endchoice # STM32 F7 Chip Selection config STM32F7_STM32F74XX bool default n - select ARCH_HAVE_FPU - select ARCH_HAVE_DPFPU # REVISIT - select ARMV7M_HAVE_ICACHE - select ARMV7M_HAVE_DCACHE - select ARMV7M_HAVE_ITCM - select ARMV7M_HAVE_DTCM + +config STM32F7_STM32F74XX + bool + default n config STM32F7_STM32F75XX bool default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F76XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_STM32F77XX + bool + default n + +config STM32F7_IO_CONFIG_V + bool + default n + +config STM32F7_IO_CONFIG_I + bool + default n + +config STM32F7_IO_CONFIG_Z + bool + default n + +config STM32F7_IO_CONFIG_N + bool + default n + +config STM32F7_IO_CONFIG_B + bool + default n + +config STM32F7_IO_CONFIG_A + bool + default n + +config STM32F7_STM32F745XX + bool + default n + select STM32F7_STM32F74XX select ARCH_HAVE_FPU - select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DMA2D + +config STM32F7_STM32F746XX + bool + default n + select STM32F7_STM32F74XX + select ARCH_HAVE_FPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + +config STM32F7_STM32F756XX + bool + default n + select STM32F7_STM32F75XX + select ARCH_HAVE_FPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + +config STM32F7_STM32F765XX + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG # data sheet says yes, Product matix says no + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F767XX + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F768XX # Revisit Wehn parts released + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F768AX # Revisit When parts released + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 + select STM32F7_HAVE_SPI6 + select STM32F7_HAVE_SDMMC2 + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F769XX + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F769AX # Revisit When parts released + bool + default n + select STM32F7_STM32F76XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 + select STM32F7_HAVE_SPI6 + select STM32F7_HAVE_SDMMC2 + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F777XX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F778XX # Revisit when parts released + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F778AX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 + select STM32F7_HAVE_SPI6 + select STM32F7_HAVE_SDMMC2 + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F779XX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_ETHRNET + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_STM32F779AX + bool + default n + select STM32F7_STM32F77XX + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FSMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32F7_HAVE_CAN3 + select STM32F7_HAVE_DCMI + select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32F7_HAVE_LTDC + select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_JPEG + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_HASH + select STM32F7_HAVE_DFSDM1 + +config STM32F7_FLASH_CONFIG_E + bool + default n + +config STM32F7_FLASH_CONFIG_I + bool + default n + +config STM32F7_FLASH_CONFIG_I + bool + default n choice - prompt "Embedded FLASH size" - default STM32F7_FLASH_1024KB + prompt "Overrdide Flash Size Designator" + depends on ARCH_CHIP_STM32F7 + default STM32F7_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32F7 series parts numbering (sans the package type) ends with a letter + that designates the FLASH size. -config STM32F7_FLASH_512KB - bool "512 KB" + Designator Size in KiB + E 512 + G 1024 + I 2048 -config STM32F7_FLASH_1024KB - bool "1024 KB" + This configuration option defaults to using the configuration based on that designator + or the default smaller size if there is no last character designator is present in the + STM32 Chip Selection. -endchoice # Embedded FLASH size + Examples: + If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of + the part with a 2048 KiB Flash is released in the future one could simply select + the 'I' designator here. + + If an STM32F7xxx Series parts is chosen the default Flash configuration will be set + herein and can be changed. + +config STM32F7_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32F7_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32F7_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32F7_FLASH_OVERRIDE_I + bool "I 2048KiB" + +endchoice # "Overrdide Flash Size Designator" menu "STM32 Peripheral Support" @@ -75,6 +931,67 @@ config STM32F7_HAVE_LTDC bool default n +config STM32F7_HAVE_FSMC + bool + default n + + +config STM32F7_HAVE_ETHRNET + bool + default n + +config STM32F7_HAVE_RNG + bool + default n + +config STM32F7_HAVE_SPI5 + bool + default n + +config STM32F7_HAVE_SPI6 + bool + default n + +config STM32F7_HAVE_SDMMC2 + bool + default n + +config STM32F7_HAVE_CAN3 + bool + default n + +config STM32F7_HAVE_DCMI + bool + default n + +config STM32F7_HAVE_DSIHOST + bool + default n + +config STM32F7_HAVE_LTDC + bool + default n + +config STM32F7_HAVE_DMA2D + bool + default n + +config STM32F7_HAVE_JPEG + bool + default n + +config STM32F7_HAVE_CRYP + bool + default n + +config STM32F7_HAVE_HASH + bool + default n + +config STM32F7_HAVE_DFSDM1 + bool + default n + # These "hidden" settings are the OR of individual peripheral selections # indicating that the general capabilitiy is required. @@ -143,6 +1060,13 @@ config STM32F7_CAN2 select CAN select STM32F7_CAN +config STM32F7_CAN3 + bool "CAN3" + default n + select CAN + select STM32F7_CAN + depends on STM32F7_HAVE_CAN3 + config STM32F7_CEC bool "CEC" default n @@ -154,8 +1078,15 @@ config STM32F7_CRC config STM32F7_CRYP bool "CRYP" + depends on STM32F7_HAVE_CRYP default n +config STM32F7_DFSDM1 + bool "DFSDM1" + default n + depends on STM32F7_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 + config STM32F7_DMA1 bool "DMA1" default n @@ -181,17 +1112,54 @@ config STM32F7_DAC2 config STM32F7_DCMI bool "DCMI" default n + depends on STM32F7_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32F7_DSIHOST + bool "DSIHOST" + default n + depends on STM32F7_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI + compliant displays. + +config STM32F7_DMA2D + bool "DMA2D" + default n + depends on STM32F7_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32 F7 devices. + +config STM32F7_JPEG + bool "JPEG" + default n + depends on STM32F7_HAVE_JPEG + ---help--- + The JPEG codec provides an fast and simple hardware compressor and + decompressor of JPEG images with full management of JPEG headers. config STM32F7_ETHMAC bool "Ethernet MAC" default n + depends on STM32F7_HAVE_ETHRNET select NETDEVICES select ARCH_HAVE_PHY config STM32F7_FSMC bool "FSMC" + depends on STM32F7_HAVE_FSMC default n +config STM32F7_HASH + bool "HASH" + default n + depends on STM32F7_HAVE_HASH + select ARCH_HAVE_HASH + config STM32F7_I2C1 bool "I2C1" default n @@ -225,13 +1193,6 @@ config STM32F7_LTDC video interface (HSYNC, VSYNC, etc.) for controlling TFT LCD displays. -config STM32F7_DMA2D - bool "DMA2D" - default n - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32 F7 devices. - config STM32F7_OTGFS bool "OTG FS" default n @@ -246,10 +1207,10 @@ config STM32F7_QUADSPI bool "QuadSPI" default n -config STM32F7_SAI1 config STM32F7_RNG bool "RNG" default n + depends on STM32F7_HAVE_RNG select ARCH_HAVE_RNG config STM32F7_SAI1 @@ -267,6 +1228,12 @@ config STM32F7_SDMMC1 default n select ARCH_HAVE_SDIO +config STM32F7_SDMMC2 + bool "SDMMC2" + default n + depends on STM32F7_HAVE_SDMMC2 + select ARCH_HAVE_SDIO + config STM32F7_SPDIFRX bool "SPDIFRX" default n @@ -298,12 +1265,14 @@ config STM32F7_SPI4 config STM32F7_SPI5 bool "SPI5" default n + depends on STM32F7_HAVE_SPI5 select SPI select STM32F7_SPI config STM32F7_SPI6 bool "SPI6" default n + depends on STM32F7_HAVE_SPI6 select SPI select STM32F7_SPI @@ -685,7 +1654,7 @@ config STM32F7_SERIALBRK_BSDCOMPAT endmenu # U[S]ART Configuration config STM32F7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" + bool "Custom clock configuration" default n ---help--- Enables special, board-specific STM32 clock configuration. diff --git a/arch/arm/src/stm32f7/chip/stm32_dma.h b/arch/arm/src/stm32f7/chip/stm32_dma.h index 63db15ec9f..64fa967bca 100644 --- a/arch/arm/src/stm32f7/chip/stm32_dma.h +++ b/arch/arm/src/stm32f7/chip/stm32_dma.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_dma.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_dma.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_dma.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_ethernet.h b/arch/arm/src/stm32f7/chip/stm32_ethernet.h index e5fc6982d2..962cb6d922 100644 --- a/arch/arm/src/stm32f7/chip/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/chip/stm32_ethernet.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_ethernet.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -46,7 +47,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************************************** * Pre-processor Definitions @@ -805,6 +807,6 @@ struct eth_rxdesc_s ****************************************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_exti.h b/arch/arm/src/stm32f7/chip/stm32_exti.h index 1bf43de793..288f51b228 100644 --- a/arch/arm/src/stm32f7/chip/stm32_exti.h +++ b/arch/arm/src/stm32f7/chip/stm32_exti.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_exti.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -47,7 +48,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /************************************************************************************ * Pre-processor Definitions @@ -127,5 +129,5 @@ #define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_IMR_MASK STM32_EXTI_MASK -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_flash.h b/arch/arm/src/stm32f7/chip/stm32_flash.h index 965191bdcf..d20bdfe4d3 100644 --- a/arch/arm/src/stm32f7/chip/stm32_flash.h +++ b/arch/arm/src/stm32f7/chip/stm32_flash.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_flash.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_flash.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_flash.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_gpio.h b/arch/arm/src/stm32f7/chip/stm32_gpio.h index 5b89574b0f..06431bb787 100644 --- a/arch/arm/src/stm32f7/chip/stm32_gpio.h +++ b/arch/arm/src/stm32f7/chip/stm32_gpio.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_gpio.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_gpio.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_gpio.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_memorymap.h b/arch/arm/src/stm32f7/chip/stm32_memorymap.h index f3ef8a1d53..eba94016fd 100644 --- a/arch/arm/src/stm32f7/chip/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32_memorymap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_memorymap.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_memorymap.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_memorymap.h" #else # error "Unsupported STM32 F7 memory map" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_pinmap.h b/arch/arm/src/stm32f7/chip/stm32_pinmap.h index 59903d8d03..034e32166e 100644 --- a/arch/arm/src/stm32f7/chip/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32_pinmap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_pinmap.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,8 +46,10 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_pinmap.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_pinmap.h" #else -# error "Unsupported STM32 F7 memory map" +# error "Unsupported STM32 F7 Pin map" #endif #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_pwr.h b/arch/arm/src/stm32f7/chip/stm32_pwr.h index 427fab1f3f..e9415d800a 100644 --- a/arch/arm/src/stm32f7/chip/stm32_pwr.h +++ b/arch/arm/src/stm32f7/chip/stm32_pwr.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_pwr.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_pwr.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_pwr.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_rcc.h b/arch/arm/src/stm32f7/chip/stm32_rcc.h index 13468a5560..1bbbca2ec8 100644 --- a/arch/arm/src/stm32f7/chip/stm32_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32_rcc.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_rcc.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +45,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_rcc.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_rcc.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_syscfg.h b/arch/arm/src/stm32f7/chip/stm32_syscfg.h index 37c82ec50c..5b1f4c1a3d 100644 --- a/arch/arm/src/stm32f7/chip/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/chip/stm32_syscfg.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_syscfg.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_syscfg.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_syscfg.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/chip/stm32_uart.h index 0d48eaa399..a260cca6ca 100644 --- a/arch/arm/src/stm32f7/chip/stm32_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32_uart.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_uart.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,8 +43,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# include "chip/stm32f74xx75xx_uart.h" +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f74xx77xx_uart.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h index a9acb05787..6b7fed23c1 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h @@ -412,16 +412,16 @@ #define DMAMAP_SPDIFRX_CS STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN0) #define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) -#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) -#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) #define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) #define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) -#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) -#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) -#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) +#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_I2C1_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) #define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) -#define DMAMAP_I2C_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) +#define DMAMAP_I2C4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) #define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) #define DMAMAP_I2C4_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) #define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) @@ -429,7 +429,7 @@ #define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) #define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) -#define DMAMAP_I2C3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) #define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) #define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) #define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) @@ -468,8 +468,8 @@ #define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) #define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) -#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) -#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_I2C2_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) #define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) #define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) #define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h index 69f4e217fc..74c2759fc9 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -40,44 +41,62 @@ * Pre-processor Definitions ************************************************************************************/ -/* Flash size is not known from the chip configuration: +/* Flash size is known from the chip selection: + * + * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip + * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH * - * The user has to tell us the FLASH size by setting CONFIG_STM32F7_FLASH_SIZE + * N.B. Only Single bank mode is supported */ -#if defined(CONFIG_STM32F7_FLASH_512KB) - -# define STM32_FLASH_NPAGES 2 -# define STM32_FLASH_SIZE (512*1024) - -#elif defined(CONFIG_STM32F7_FLASH_1024KB) - -# define STM32_FLASH_NPAGES 4 -# define STM32_FLASH_SIZE (1024*1024) - -#else -# warning Assuming FLASH size 1024KB - -# define STM32_FLASH_NPAGES 4 -# define STM32_FLASH_SIZE (1024*1024) +#define _K(x) ((x)*1024) +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_F) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E +# warning "Flash size not defined defaulting to 512KiB (E)" #endif -/* The STM32F745xx/46xx have mixed page sizes: - * - * Sectors: 0-3: 32 KB - * Sector 4 128 KB - * Sectors: 5-7: 256 KB - * - * We use the largest page size and set the number of pages equal to the - * FLASH size assuming that fixed, largest pages size. - */ +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) -#define STM32_FLASH_PAGESIZE (256*1024) +# undef CONFIG_STM32F7_FLASH_CONFIG_E +# undef CONFIG_STM32F7_FLASH_CONFIG_G +# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) + +# define CONFIG_STM32F7_FLASH_CONFIG_E + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) + +# define CONFIG_STM32F7_FLASH_CONFIG_G + +# endif +#endif + +#if defined(CONFIG_STM32_FLASH_CONFIG_E) + +# define STM32_FLASH_NPAGES 6 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256)} + +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) + +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256), _K(256), _K(256)} + +#endif /* Register Offsets *****************************************************************/ @@ -133,8 +152,8 @@ #define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ #define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ #define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ -#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) -# define FLASH_CR_SNB(n) ((uint32_t)(n) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ +#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) +# define FLASH_CR_SNB(n) ((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */ #define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ #define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) # define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ @@ -145,7 +164,6 @@ #define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ #define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ #define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ -#define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ /* Flash Option Control Register (OPTCR) */ @@ -159,15 +177,15 @@ # define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ #define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ #define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) -# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 5: WWDG_SW */ +# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ # define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */ # define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ # define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ #define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ #define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) # define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */ -#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) +#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-23: Not write protect */ +#define FLASH_OPTCR_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) # define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT) #define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */ #define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h index c996f7d105..b8818f6e49 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h @@ -61,7 +61,6 @@ #define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ #define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ #define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses ***************************************************************/ @@ -76,7 +75,6 @@ # define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 1 @@ -90,7 +88,6 @@ # define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 2 @@ -104,7 +101,6 @@ # define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 3 @@ -118,7 +114,6 @@ # define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 4 @@ -132,7 +127,6 @@ # define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 5 @@ -146,7 +140,6 @@ # define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 6 @@ -160,7 +153,6 @@ # define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 7 @@ -174,7 +166,6 @@ # define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 8 @@ -188,7 +179,6 @@ # define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 9 @@ -202,7 +192,6 @@ # define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOJ_BRR (STM32_GPIOJ_BASE+STM32_GPIO_BRR_OFFSET) #endif #if STM32F7_NGPIO > 10 @@ -216,7 +205,6 @@ # define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET) # define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET) # define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOK_BRR (STM32_GPIOK_BASE+STM32_GPIO_BRR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -411,9 +399,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -/* GPIO port bit reset register */ - -#define GPIO_BRR(n) (1 << (n)) - #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h index 82a5d2242b..20f3b73390 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm3fr2/chip/stm32f74xxx75xxx_memorymap.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -59,9 +60,8 @@ #define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */ # define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ # define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ -#define STM32_AHB3_BASE 0xa0000000 /* 0xa0000000-0xa0001fff: 256Mb AHB3 peripheral block */ #define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */ -#define STM32_FSMC_BASE6 0xc0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */ +#define STM32_FSMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */ #define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ #define STM32_REGION_MASK 0xf0000000 @@ -97,6 +97,7 @@ #define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ #define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */ #define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ /* APB1 Base Addresses **************************************************************/ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h index 64b68653d1..4e0410bc16 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h * * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -50,7 +51,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* Alternate Pin Functions. All members of the STM32F40xxx family share the same +/* Alternate Pin Functions. All members of the STM32F74|5xxx family share the same * pin multiplexing (although they may differ in the pins physically available). * * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h index e7c58b19ff..547b555a92 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h @@ -1,8 +1,9 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32_pwr.h + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -103,6 +104,7 @@ #define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */ #define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */ #define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#define PWR_CSR1_EIWUP (1 << 8) /* Bit 8: Enable internal wakeup */ #define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */ #define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ #define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_uart.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h similarity index 98% rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_uart.h rename to arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h index 50d5f949f5..cc838f9753 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h @@ -1,8 +1,9 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32f74xxf75xx_uart.h + * arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H -#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H +#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H +#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H /************************************************************************************ * Included Files @@ -42,7 +43,8 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /************************************************************************************ * Pre-processor Definitions @@ -366,4 +368,4 @@ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ -#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX75XX_UART_H */ +#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h new file mode 100644 index 0000000000..82ab312cb3 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h @@ -0,0 +1,593 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Davod Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* 8 DMA streams */ + +#define DMA_STREAM0 (0) +#define DMA_STREAM1 (1) +#define DMA_STREAM2 (2) +#define DMA_STREAM3 (3) +#define DMA_STREAM4 (4) +#define DMA_STREAM5 (5) +#define DMA_STREAM6 (6) +#define DMA_STREAM7 (7) + +/* 16 DMA channels */ + +#define DMA_CHAN0 (0) +#define DMA_CHAN1 (1) +#define DMA_CHAN2 (2) +#define DMA_CHAN3 (3) +#define DMA_CHAN4 (4) +#define DMA_CHAN5 (5) +#define DMA_CHAN6 (6) +#define DMA_CHAN7 (7) +#define DMA_CHAN8 (8) +#define DMA_CHAN9 (9) +#define DMA_CHAN10 (10) +#define DMA_CHAN11 (11) +#define DMA_CHAN12 (12) +#define DMA_CHAN13 (13) +#define DMA_CHAN14 (14) +#define DMA_CHAN15 (15) + +/* Register Offsets *****************************************************************/ + +#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ +#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ +#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ +#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ + +#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) +#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ +#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ +#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ +#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ +#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ +#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ + +#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ +#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ +#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ +#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ +#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ +#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ +#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ + +#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ +#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ +#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ +#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ +#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ +#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ +#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ +#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ + +#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ +#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ +#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ +#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ +#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ +#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ +#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ +#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ + +#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ +#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ +#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ +#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ +#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ +#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ +#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ +#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ + +#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ +#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ +#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ +#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ +#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ +#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ +#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ +#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ + +#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ +#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ +#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ +#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ +#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ +#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ +#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ +#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) + +#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define DMA_STREAM_MASK 0x3f +#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ +#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ +#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ +#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ +#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ + +/* DMA interrupt status register and interrupt flag clear register field definitions */ + +#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ +#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) +#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ +#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) +#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ +#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) +#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ +#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) + +#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ +#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) +#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ +#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) +#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ +#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) +#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ +#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) + +/* DMA stream configuration register */ + +#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ +#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ +#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ +#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ +#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ +#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ +#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ +#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) +# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ +# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ +# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ +#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ +#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ +#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ +#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ +#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) +# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ +#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) +# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ +#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ +#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) +# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ +# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ +# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ +# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ +#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ +#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ +#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ +#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) +# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ +#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) +# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-28: Channel selection */ +#define DMA_SCR_CHSEL_MASK (0xf << DMA_SCR_CHSEL_SHIFT) +# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) + +#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) + +/* DMA stream number of data register */ + +#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) + +/* DMA stream n FIFO control register */ + +#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ +#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) +# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ +# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ +# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ +# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ +#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ +#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ +#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) +# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ +# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ +# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ +# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ +# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ +# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ + /* Bit 6: Reserved */ +#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ + /* Bits 8-31: Reserved */ + +/* DMA Stream mapping. Each DMA stream has a mapping to several possible + * sources/sinks of data. The requests from peripherals assigned to a stream + * are simply OR'ed together before entering the DMA block. This means that only + * one request on a given stream can be enabled at once. + * + * Alternative stream selections are provided with a numeric suffix like _1, _2, etc. + * The DMA driver, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * SPI3_RX connects via DMA STREAM0, then following should be application-specific + * mapping should be used: + * + * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 + */ + +#define STM32_DMA_MAP(d,s,c) ((d) << 7 | (s) << 4 | (c)) +#define STM32_DMA_CONTROLLER(m) (((m) >> 7) & 1) +#define STM32_DMA_STREAM(m) (((m) >> 4) & 7) +#define STM32_DMA_CHANNEL(m) ((m) & 0xf) + +#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SPDIFRX_DT STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN0) +#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_SPDIFRX_CS STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) +#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_I2C1_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_I2C4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) +#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_I2C4_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4) +#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5) +#define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5) +#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5) +#define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_I2C2_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) + +#define DMAMAP_I2C3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN8) +#define DMAMAP_I2C4_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN8) +#define DMAMAP_I2C2_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN8) +#define DMAMAP_I2C4_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN8) + +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN9) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN9) + +#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SAI1_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN0) +#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SAI1_A_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SAI1_B_1 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_SAI1_B_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1) +#define DMAMAP_SAI1_B STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN1) +#define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2) +#define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2) +#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) +#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_SAI2_A STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_SAI2_B STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_SDMMC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_SDMMC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5) +#define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) +#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) + +#define DMAMAP_DFSDM1_FLT0_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT1_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT3_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT0_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT1_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT2_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN8) +#define DMAMAP_DFSDM1_FLT3_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN8) + +#define DMAMAP_JPEG_IN_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN9) +#define DMAMAP_JPEG_OUT_ STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN9) +#define DMAMAP_SPI4_TX_3 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN9) +#define DMAMAP_JPEG_IN_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN9) +#define DMAMAP_JPEG_OUT_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN9) +#define DMAMAP_SPI5_RX_3 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN9) + +#define DMAMAP_SAI1_B_3 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN10) +#define DMAMAP_SAI2_B_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN10) +#define DMAMAP_SAI2_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN10) +#define DMAMAP_SAI1_A_3 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN10) + +#define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) +#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) +#define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h new file mode 100644 index 0000000000..0b6f764c36 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h @@ -0,0 +1,219 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H +#define __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Flash size is known from the chip selection: + * + * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip + * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * + * Parts STM32F74xxE have 512Kb of FLASH + * Parts STM32F74xxG have 1024Kb of FLASH + * + * N.B. Only Single bank mode is supported + */ + +#define _K(x) ((x)*1024) + +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_F) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_F) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E +# warning "Flash size not defined defaulting to 512KiB (E)" +#endif + +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) + +# undef CONFIG_STM32F7_FLASH_CONFIG_E +# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32F7_FLASH_CONFIG_I + +# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) + +# define CONFIG_STM32F7_FLASH_CONFIG_E + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) + +# define CONFIG_STM32F7_FLASH_CONFIG_G + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) + +# define CONFIG_STM32F7_FLASH_CONFIG_I + +# endif +#endif + +#if defined(CONFIG_STM32_FLASH_CONFIG_E) + +# define STM32_FLASH_NPAGES 6 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256)} + +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) + +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256), _K(256), _K(256)} + +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) + +# define STM32_FLASH_NPAGES 12 +# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256)) +# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ + _K(128), _K(256), _K(256), _K(256) \ + _K(256), _K(256), _K(256), _K(256)} +#endif + +/* Register Offsets *****************************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_KEYR_OFFSET 0x0004 +#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +#define STM32_FLASH_SR_OFFSET 0x000c +#define STM32_FLASH_CR_OFFSET 0x0010 +#define STM32_FLASH_OPTCR_OFFSET 0x0014 +#define STM32_FLASH_OPTCR1_OFFSET 0x0018 + +/* Register Addresses ***************************************************************/ + +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) +#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-1: Latency */ +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ +# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */ +# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */ +# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */ +# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */ +# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */ +#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ +#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */ +#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ +#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ +#define FLASH_CR_MER_MER1 (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ +#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ +#define FLASH_CR_SNB_MASK (0x1f << FLASH_CR_SNB_SHIFT) +# define FLASH_CR_SNB(n) ((uint32_t)((n) % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */ +#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ +#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) +# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ +# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */ +# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */ +# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */ +#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ +#define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */ + +/* Flash Option Control Register (OPTCR) */ + +#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ +#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ +#define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ +#define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT) +# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 3 */ +# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */ +# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */ +# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ +#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ +#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) +# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ +# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */ +# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ +# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ +#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ +#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) +# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */ +#define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT) +# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT) +#define FLASH_OPTCR_NDBANK (1 << 28) /* Bit 28: Not dual bank mode */ +#define FLASH_OPTCR_NDBOOT (1 << 29) /* Bit 29: Dual Boot mode */ +#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */ +#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */ + +/* Flash Option Control Register (OPTCR1) */ + +#define FLASH_OPTCR1_BOOTADD0_SHIFT (0) /* Bits 0-15: Boot base address when Boot pin=0 */ +#define FLASH_OPTCR1_BOOTADD0_MASK (0xffff << FLASH_OPTCR1_BOOTADD0_SHIFT) +# define FLASH_OPTCR1_BOOTADD0(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD0_SHIFT) +#define FLASH_OPTCR1_BOOTADD1_SHIFT (16) /* Bits 16-31:Boot base address when Boot pin=1 */ +#define FLASH_OPTCR1_BOOTADD1_MASK (0xffff << FLASH_OPTCR1_BOOTADD1_SHIFT) +# define FLASH_OPTCR1_BOOTADD1(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD1_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32F74XX75XX_FLASH_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h new file mode 100644 index 0000000000..711dc0e124 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h @@ -0,0 +1,404 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xxx77xx_gpio.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ + +/* Register Addresses ***************************************************************/ + +#if STM32F7_NGPIO > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 9 +# define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOJ_PUPDR (STM32_GPIOJ_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOJ_IDR (STM32_GPIOJ_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOJ_ODR (STM32_GPIOJ_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOJ_BSRR (STM32_GPIOJ_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 10 +# define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOK_PUPDR (STM32_GPIOK_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOK_IDR (STM32_GPIOK_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOK_ODR (STM32_GPIOK_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOK_BSRR (STM32_GPIOK_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* GPIO port mode register */ + +#define GPIO_MODER_INPUT (0) /* Input */ +#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ +#define GPIO_MODER_ALT (2) /* Alternate mode */ +#define GPIO_MODER_ANALOG (3) /* Analog mode */ + +#define GPIO_MODER_SHIFT(n) ((n) << 1) +#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) + +#define GPIO_MODER0_SHIFT (0) +#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) +#define GPIO_MODER1_SHIFT (2) +#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) +#define GPIO_MODER2_SHIFT (4) +#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) +#define GPIO_MODER3_SHIFT (6) +#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) +#define GPIO_MODER4_SHIFT (8) +#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) +#define GPIO_MODER5_SHIFT (10) +#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) +#define GPIO_MODER6_SHIFT (12) +#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) +#define GPIO_MODER7_SHIFT (14) +#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) +#define GPIO_MODER8_SHIFT (16) +#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) +#define GPIO_MODER9_SHIFT (18) +#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) +#define GPIO_MODER10_SHIFT (20) +#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) +#define GPIO_MODER11_SHIFT (22) +#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) +#define GPIO_MODER12_SHIFT (24) +#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) +#define GPIO_MODER13_SHIFT (26) +#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) +#define GPIO_MODER14_SHIFT (28) +#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) +#define GPIO_MODER15_SHIFT (30) +#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) + +/* GPIO port output type register */ + +#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ +#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */ + +/* GPIO port output speed register */ + +#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */ +#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */ +#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */ +#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) +#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) + +#define GPIO_OSPEED0_SHIFT (0) +#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) +#define GPIO_OSPEED1_SHIFT (2) +#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) +#define GPIO_OSPEED2_SHIFT (4) +#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) +#define GPIO_OSPEED3_SHIFT (6) +#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) +#define GPIO_OSPEED4_SHIFT (8) +#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) +#define GPIO_OSPEED5_SHIFT (10) +#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) +#define GPIO_OSPEED6_SHIFT (12) +#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) +#define GPIO_OSPEED7_SHIFT (14) +#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) +#define GPIO_OSPEED8_SHIFT (16) +#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) +#define GPIO_OSPEED9_SHIFT (18) +#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) +#define GPIO_OSPEED10_SHIFT (20) +#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) +#define GPIO_OSPEED11_SHIFT (22) +#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) +#define GPIO_OSPEED12_SHIFT (24) +#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) +#define GPIO_OSPEED13_SHIFT (26) +#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) +#define GPIO_OSPEED14_SHIFT (28) +#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) +#define GPIO_OSPEED15_SHIFT (30) +#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) + +/* GPIO port pull-up/pull-down register */ + +#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ +#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ +#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ + +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) +#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) + +#define GPIO_PUPDR0_SHIFT (0) +#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) +#define GPIO_PUPDR1_SHIFT (2) +#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) +#define GPIO_PUPDR2_SHIFT (4) +#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) +#define GPIO_PUPDR3_SHIFT (6) +#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) +#define GPIO_PUPDR4_SHIFT (8) +#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) +#define GPIO_PUPDR5_SHIFT (10) +#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) +#define GPIO_PUPDR6_SHIFT (12) +#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) +#define GPIO_PUPDR7_SHIFT (14) +#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) +#define GPIO_PUPDR8_SHIFT (16) +#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) +#define GPIO_PUPDR9_SHIFT (18) +#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) +#define GPIO_PUPDR10_SHIFT (20) +#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) +#define GPIO_PUPDR11_SHIFT (22) +#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) +#define GPIO_PUPDR12_SHIFT (24) +#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) +#define GPIO_PUPDR13_SHIFT (26) +#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) +#define GPIO_PUPDR14_SHIFT (28) +#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) +#define GPIO_PUPDR15_SHIFT (30) +#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) + +/* GPIO port input data register */ + +#define GPIO_IDR(n) (1 << (n)) + +/* GPIO port output data register */ + +#define GPIO_ODR(n) (1 << (n)) + +/* GPIO port bit set/reset register */ + +#define GPIO_BSRR_SET(n) (1 << (n)) +#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) + +/* GPIO port configuration lock register */ + +#define GPIO_LCKR(n) (1 << (n)) +#define GPIO_LCKK (1 << 16) /* Lock key */ + +/* GPIO alternate function low/high register */ + +#define GPIO_AFR_SHIFT(n) ((n) << 2) +#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) + +#define GPIO_AFRL0_SHIFT (0) +#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) +#define GPIO_AFRL1_SHIFT (4) +#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) +#define GPIO_AFRL2_SHIFT (8) +#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) +#define GPIO_AFRL3_SHIFT (12) +#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) +#define GPIO_AFRL4_SHIFT (16) +#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) +#define GPIO_AFRL5_SHIFT (20) +#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) +#define GPIO_AFRL6_SHIFT (24) +#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) +#define GPIO_AFRL7_SHIFT (28) +#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) + +#define GPIO_AFRH8_SHIFT (0) +#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) +#define GPIO_AFRH9_SHIFT (4) +#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) +#define GPIO_AFRH10_SHIFT (8) +#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) +#define GPIO_AFRH11_SHIFT (12) +#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) +#define GPIO_AFRH12_SHIFT (16) +#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) +#define GPIO_AFRH13_SHIFT (20) +#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) +#define GPIO_AFRH14_SHIFT (24) +#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) +#define GPIO_AFRH15_SHIFT (28) +#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h new file mode 100644 index 0000000000..c4c6177ac6 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h @@ -0,0 +1,214 @@ +/************************************************************************************ + * arch/arm/src/stm3fr2/chip/stm32f76xxx77xxx_memorymap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F40XXX Address Blocks *******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3&4 block */ +# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ +#define STM32_FSMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FSMC */ +#define STM32_FSMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FSMC */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */ +#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */ +#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x003fffff: FLASH memory (ITCM) */ +#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */ +#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x081fffff: FLASH memory (AXIM) */ +#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */ + +/* Information Addresses ************************************************************/ + + +#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */ +#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */ +#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */ + +/* SRAM Base Addresses **************************************************************/ + +#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */ +#define STM32_SRAM1_BASE 0x20020000 /* 0x20020000-0x2007bfff: System SRAM1 */ +#define STM32_SRAM2_BASE 0x2007c000 /* 0x2007c000-0x2007ffff: System SRAM2 */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */ +#define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x5003ffff: AHB2 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */ +#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff: TIM4 */ +#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00-0x40000fff: TIM5 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff: TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff: TIM7 */ +#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff: TIM12 */ +#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 */ +#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */ +#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */ +#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */ +#define STM32_CAN3_BASE 0x40003400 /* 0x40003400-0x400037ff: CAN3 */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */ +#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */ +#define STM32_SPDIFRX_BASE 0x40004000 /* 0x40004000-0x400043ff: SPDIFRX */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff: USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff: USART3 */ +#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff: UART4 */ +#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff: UART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff: I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff: I2C2 */ +#define STM32_I2C3_BASE 0x40005c00 /* 0x40005c00-0x40005fff: I2C3 */ +#define STM32_I2C4_BASE 0x40006000 /* 0x40006000-0x400063ff: I2C4 */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: CAN1 */ +#define STM32_CAN2_BASE 0x40006800 /* 0x40006800-0x40006bff: CAN2 */ +#define STM32_HDMICEC_BASE 0x40006c00 /* 0x40006c00-0x40006fff: HDMI-CEC */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: PWR */ +#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */ +#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */ +#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */ +#define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */ +#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */ +#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */ +#define STM32_SDMMC2_BASE 0x40011c00 /* 0x40011c00-0x40011fff: SDMMC2 */ +#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */ +#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ +#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */ +#define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */ +#define STM32_EXTI_BASE 0x40013c00 /* 0x40013c00-0x40013fff: EXTI */ +#define STM32_TIM9_BASE 0x40014000 /* 0x40014000-0x400143ff: TIM9 */ +#define STM32_TIM10_BASE 0x40014400 /* 0x40014400-0x400147ff: TIM10 */ +#define STM32_TIM11_BASE 0x40014800 /* 0x40014800-0x40014bff: TIM11 */ +#define STM32_SPI5_BASE 0x40015000 /* 0x40015000-0x400153ff: SPI5 */ +#define STM32_SPI6_BASE 0x40015400 /* 0x40015400-0x400157ff: SPI6 */ +#define STM32_SAI1_BASE 0x40015800 /* 0x40015800-0x40015bff: SAI1 */ +#define STM32_SAI2_BASE 0x40015c00 /* 0x40015c00-0x40015fff: SAI2 */ +#define STM32_LCDTFT_BASE 0x40016800 /* 0x40016800-0x40016bff: LCD-TFT */ +#define STM32_DSIHOST_BASE 0x40016c00 /* 0x40016c00-0x400173ff: DSI Host */ +#define STM32_DFSDM1_BASE 0x40017400 /* 0x40017400-0x400174ff: DFSDM1 */ +#define STM32_MDIOS_BASE 0x40017800 /* 0x40017800-0x40017bff: MDIOS */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */ +#define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */ +#define STM32_GPIOC_BASE 0x40020800 /* 0x40020800-0x40020bff: GPIOC */ +#define STM32_GPIOD_BASE 0x40020c00 /* 0x40020c00-0x40020fff: GPIOD */ +#define STM32_GPIOE_BASE 0x40021000 /* 0x40021000-0x400213ff: GPIOE */ +#define STM32_GPIOF_BASE 0x40021400 /* 0x40021400-0x400217ff: GPIOF */ +#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIOG */ +#define STM32_GPIOH_BASE 0x40021c00 /* 0x40021c00-0x40021fff: GPIOH */ +#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIOI */ +#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIOJ */ +#define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022bff: GPIOK */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */ +#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash interface */ +#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: BKPSRAM */ +#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */ +#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */ +#define STM32_ETHMAC_BASE 0x40028000 /* 0x40028000-0x400293ff: ETHERNET MAC */ +#define STM32_DMA2D_BASE 0x4002b000 /* 0x4002b000-0x4002Bbff: Chrom-ART (DMA2D) */ +#define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */ +#define STM32_DCMI_BASE 0x50050000 /* 0x50050000-0x500503ff: DCMI */ +#define STM32_JPEG_BASE 0x50051000 /* 0x50051000-0x500511ff: JPEG */ +#define STM32_CRYP_BASE 0x50060000 /* 0x50060000-0x500603ff: CRYP */ +#define STM32_HASH_BASE 0x50060400 /* 0x50060400-0x500607ff: HASH */ +#define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */ + +/* AHB3 Base Addresses **************************************************************/ + +#define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */ +#define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */ +#define STM32_FMCBANK3_BASE 0x80000000 /* 0x80000000-0x8fffffff: FMC bank 3 */ +#define STM32_FMCBANK4_BASE 0x90000000 /* 0x90000000-0x9fffffff: FMC bank 4 */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */ +#define STM32_QUADSPI_BASE 0xa0001000 /* 0xa0001000-0xa0001fff: QuadSPI Control */ +#define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */ +#define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */ + +/* Cortex-M7 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this + * address range + */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h new file mode 100644 index 0000000000..4c60603c95 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h @@ -0,0 +1,1343 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_gpio.h" + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F76XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Alternate Pin Functions. All members of the STM32F76|7xxx family share the same + * pin multiplexing (although they may differ in the pins physically available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN1_RX connects vis PA11 on some board, then the following definitions should + * appear inthe board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configre PA11 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* ADC */ + +#define GPIO_ADC1_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_ADC2_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_ADC3_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6) +#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7) +#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8) +#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9) +#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10) + +#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3) +#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4) +#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5) + +/* CAN */ + +#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_CAN1_RX_5 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) + +#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) + +#define GPIO_CAN2_RX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_CAN2_RX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_CAN2_TX_1 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_CAN2_TX_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) + +#define GPIO_CAN3_RX_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_CAN3_RX_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_CAN3_TX_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_CAN3_TX_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) + +/* DAC -" Once the DAC channel is enabled, the corresponding GPIO pin + * (PA4 or PA5) is automatically connected to the analog converter output + * (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin + * should first be configured to analog (AIN)". + */ + +#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) + +/* Digital Camera Interface (DCMI) */ + +#define GPIO_DCMI_D0_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9) +#define GPIO_DCMI_D0_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6) +#define GPIO_DCMI_D0_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN9) +#define GPIO_DCMI_D1_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10) +#define GPIO_DCMI_D1_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7) +#define GPIO_DCMI_D1_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN10) +#define GPIO_DCMI_D2_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN8) +#define GPIO_DCMI_D2_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN0) +#define GPIO_DCMI_D2_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10) +#define GPIO_DCMI_D2_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN11) +#define GPIO_DCMI_D3_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9) +#define GPIO_DCMI_D3_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN1) +#define GPIO_DCMI_D3_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11) +#define GPIO_DCMI_D3_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN12) +#define GPIO_DCMI_D4_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11) +#define GPIO_DCMI_D4_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4) +#define GPIO_DCMI_D4_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN14) +#define GPIO_DCMI_D5_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6) +#define GPIO_DCMI_D5_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN3) +#define GPIO_DCMI_D5_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN4) +#define GPIO_DCMI_D6_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8) +#define GPIO_DCMI_D6_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5) +#define GPIO_DCMI_D6_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN6) +#define GPIO_DCMI_D7_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9) +#define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6) +#define GPIO_DCMI_D7_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN7) +#define GPIO_DCMI_D8_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10) +#define GPIO_DCMI_D8_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN6) +#define GPIO_DCMI_D8_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN1) +#define GPIO_DCMI_D9_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12) +#define GPIO_DCMI_D9_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN7) +#define GPIO_DCMI_D9_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN2) +#define GPIO_DCMI_D10_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5) +#define GPIO_DCMI_D10_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6) +#define GPIO_DCMI_D10_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN3) +#define GPIO_DCMI_D11_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN2) +#define GPIO_DCMI_D11_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN10) +#define GPIO_DCMI_D11_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN15) +#define GPIO_DCMI_D12_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN11) +#define GPIO_DCMI_D12_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN6) +#define GPIO_DCMI_D13_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN15) +#define GPIO_DCMI_D13_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN7) +#define GPIO_DCMI_D13_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN0) +#define GPIO_DCMI_HSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DCMI_HSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTH|GPIO_PIN8) +#define GPIO_DCMI_PIXCK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6) +#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7) +#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9) +#define GPIO_DCMI_VSYNC_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN5) + +/* DSI Host */ + +#define DSI_TE_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN11) +#define DSI_TE_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTJ|GPIO_PIN12) + +/* Digital filter for sigma delta modulators */ + +#define GPIO_DFSDM1_CKOUT_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_DFSDM1_CKOUT_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_DFSDM1_CKOUT_3 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_DFSDM1_CKOUT_4 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) +#define GPIO_DFSDM1_CKOUT_5 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_DFSDM1_CKIN0_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) +#define GPIO_DFSDM1_CKIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_DFSDM1_CKIN1_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN2) +#define GPIO_DFSDM1_CKIN1_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_DFSDM1_CKIN1_3 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_DFSDM1_CKIN1_4 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_DFSDM1_CKIN2_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_DFSDM1_CKIN2_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) +#define GPIO_DFSDM1_CKIN2_3 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_DFSDM1_CKIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_DFSDM1_CKIN3_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1) +#define GPIO_DFSDM1_CKIN3_3 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8) +#define GPIO_DFSDM1_CKIN3_4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_DFSDM1_CKIN4_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_DFSDM1_CKIN4_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_DFSDM1_CKIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_DFSDM1_CKIN5_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_DFSDM1_CKIN5_3 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_DFSDM1_CKIN6_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_DFSDM1_CKIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14) +#define GPIO_DFSDM1_CKIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_DFSDM1_CKIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_DFSDM1_CKIN7_3 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_DFSDM1_CKIN7_4 (GPIO_ALT|GPIO_AF6 |GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTS|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN0_1 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN4) +#define GPIO_DFSDM1_DATAIN1_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN1_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_DFSDM1_DATAIN1_3 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_DFSDM1_DATAIN1_4 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_DFSDM1_DATAIN2_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_DFSDM1_DATAIN2_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) +#define GPIO_DFSDM1_DATAIN2_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7) +#define GPIO_DFSDM1_DATAIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_DFSDM1_DATAIN3_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9) +#define GPIO_DFSDM1_DATAIN3_3 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4) +#define GPIO_DFSDM1_DATAIN4_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) +#define GPIO_DFSDM1_DATAIN4_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_DFSDM1_DATAIN4_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10) +#define GPIO_DFSDM1_DATAIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_DFSDM1_DATAIN5_2 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_DFSDM1_DATAIN5_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12) +#define GPIO_DFSDM1_DATAIN6_1 (GPIO_ALT|GPIO_AF3 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_DFSDM1_DATAIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13) +#define GPIO_DFSDM1_DATAIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_DFSDM1_DATAIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_DFSDM1_DATAIN7_3 (GPIO_ALT|GPIO_AF6 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) + +/* Ethernet MAC */ + +#define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3) +#define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2) +#define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) +#define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN7) +#define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10) +#define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) +#define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2) +#define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8) + +#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) +#define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) + +/* Event outputs */ + +#define GPIO_PA0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1) +#define GPIO_PA2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2) +#define GPIO_PA3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3) +#define GPIO_PA4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4) +#define GPIO_PA5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5) +#define GPIO_PA6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6) +#define GPIO_PA7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7) +#define GPIO_PA8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8) +#define GPIO_PA9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9) +#define GPIO_PA10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10) +#define GPIO_PA11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11) +#define GPIO_PA12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12) +#define GPIO_PA13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13) +#define GPIO_PA14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14) +#define GPIO_PA15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_PB0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0) +#define GPIO_PB1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1) +#define GPIO_PB2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2) +#define GPIO_PB3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3) +#define GPIO_PB4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4) +#define GPIO_PB5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5) +#define GPIO_PB6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6) +#define GPIO_PB7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7) +#define GPIO_PB8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8) +#define GPIO_PB9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9) +#define GPIO_PB10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10) +#define GPIO_PB11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11) +#define GPIO_PB12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12) +#define GPIO_PB13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13) +#define GPIO_PB14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14) +#define GPIO_PB15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_PC0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN0) +#define GPIO_PC1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN1) +#define GPIO_PC2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN2) +#define GPIO_PC3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN3) +#define GPIO_PC4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN4) +#define GPIO_PC5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN5) +#define GPIO_PC6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN6) +#define GPIO_PC7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN7) +#define GPIO_PC8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN8) +#define GPIO_PC9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN9) +#define GPIO_PC10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN10) +#define GPIO_PC11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN11) +#define GPIO_PC12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN12) +#define GPIO_PC13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN13) +#define GPIO_PC14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN14) +#define GPIO_PC15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN15) + +#define GPIO_PD0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN0) +#define GPIO_PD1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN1) +#define GPIO_PD2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN2) +#define GPIO_PD3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN3) +#define GPIO_PD4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN4) +#define GPIO_PD5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN5) +#define GPIO_PD6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN6) +#define GPIO_PD7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN7) +#define GPIO_PD8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN8) +#define GPIO_PD9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN9) +#define GPIO_PD10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN10) +#define GPIO_PD11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN11) +#define GPIO_PD12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN12) +#define GPIO_PD13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN13) +#define GPIO_PD14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN14) +#define GPIO_PD15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN15) + +#define GPIO_PE0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN0) +#define GPIO_PE1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN1) +#define GPIO_PE2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN2) +#define GPIO_PE3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN3) +#define GPIO_PE4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN4) +#define GPIO_PE5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN5) +#define GPIO_PE6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN6) +#define GPIO_PE7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN7) +#define GPIO_PE8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN8) +#define GPIO_PE9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN9) +#define GPIO_PE10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN10) +#define GPIO_PE11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN11) +#define GPIO_PE12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN12) +#define GPIO_PE13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN13) +#define GPIO_PE14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN14) +#define GPIO_PE15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN15) + +#define GPIO_PF0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN0) +#define GPIO_PF1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN1) +#define GPIO_PF2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN2) +#define GPIO_PF3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN3) +#define GPIO_PF4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN4) +#define GPIO_PF5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN5) +#define GPIO_PF6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN6) +#define GPIO_PF7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN7) +#define GPIO_PF8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN8) +#define GPIO_PF9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN9) +#define GPIO_PF10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN10) +#define GPIO_PF11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN11) +#define GPIO_PF12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN12) +#define GPIO_PF13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN13) +#define GPIO_PF14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN14) +#define GPIO_PF15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN15) + +#define GPIO_PG0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN0) +#define GPIO_PG1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN1) +#define GPIO_PG2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN2) +#define GPIO_PG3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN3) +#define GPIO_PG4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN4) +#define GPIO_PG5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN5) +#define GPIO_PG6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN6) +#define GPIO_PG7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN7) +#define GPIO_PG8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN8) +#define GPIO_PG9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN9) +#define GPIO_PG10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN10) +#define GPIO_PG11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN11) +#define GPIO_PG12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN12) +#define GPIO_PG13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN13) +#define GPIO_PG14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN14) +#define GPIO_PG15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN15) + +#define GPIO_PH0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN0) +#define GPIO_PH1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN1) +#define GPIO_PH2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN2) +#define GPIO_PH3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN3) +#define GPIO_PH4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN4) +#define GPIO_PH5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN5) +#define GPIO_PH6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN6) +#define GPIO_PH7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN7) +#define GPIO_PH8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN8) +#define GPIO_PH9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN9) +#define GPIO_PH10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN10) +#define GPIO_PH11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN11) +#define GPIO_PH12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN12) +#define GPIO_PH13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN13) +#define GPIO_PH14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN14) +#define GPIO_PH15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN15) + +#define GPIO_PI0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN0) +#define GPIO_PI1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN1) +#define GPIO_PI2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN2) +#define GPIO_PI3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN3) +#define GPIO_PI4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN4) +#define GPIO_PI5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN5) +#define GPIO_PI6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN6) +#define GPIO_PI7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN7) +#define GPIO_PI8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN8) +#define GPIO_PI9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN9) +#define GPIO_PI10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN10) +#define GPIO_PI11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN11) +#define GPIO_PI12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN12) +#define GPIO_PI13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN13) +#define GPIO_PI14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN14) +#define GPIO_PI15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN15) + +#define GPIO_PJ0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN0) +#define GPIO_PJ1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN1) +#define GPIO_PJ2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN2) +#define GPIO_PJ3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN3) +#define GPIO_PJ4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN4) +#define GPIO_PJ5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN5) +#define GPIO_PJ6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN6) +#define GPIO_PJ7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN7) +#define GPIO_PJ8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN8) +#define GPIO_PJ9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN9) +#define GPIO_PJ10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN10) +#define GPIO_PJ11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN11) +#define GPIO_PJ12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN12) +#define GPIO_PJ13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN13) +#define GPIO_PJ14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN14) +#define GPIO_PJ15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTJ|GPIO_PIN15) + +#define GPIO_PK0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN0) +#define GPIO_PK1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN1) +#define GPIO_PK2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN2) +#define GPIO_PK3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN3) +#define GPIO_PK4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN4) +#define GPIO_PK5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN5) +#define GPIO_PK6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN6) +#define GPIO_PK7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTK|GPIO_PIN7) + +/* Flexible Static Memory Controller (FSMC) */ + +#define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0) +#define GPIO_FSMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1) +#define GPIO_FSMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2) +#define GPIO_FSMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3) +#define GPIO_FSMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4) +#define GPIO_FSMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5) +#define GPIO_FSMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12) +#define GPIO_FSMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13) +#define GPIO_FSMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14) +#define GPIO_FSMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15) +#define GPIO_FSMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0) +#define GPIO_FSMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1) +#define GPIO_FSMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2) +#define GPIO_FSMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3) +#define GPIO_FSMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4) +#define GPIO_FSMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5) +#define GPIO_FSMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11) +#define GPIO_FSMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_FSMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13) +#define GPIO_FSMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3) +#define GPIO_FSMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4) +#define GPIO_FSMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5) +#define GPIO_FSMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6) +#define GPIO_FSMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2) +#define GPIO_FSMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13) +#define GPIO_FSMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14) +#define GPIO_FSMC_ALE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4) +#define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5) +#define GPIO_FSMC_CLE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11) +#define GPIO_FSMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3) +#define GPIO_FSMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14) +#define GPIO_FSMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15) +#define GPIO_FSMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0) +#define GPIO_FSMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1) +#define GPIO_FSMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7) +#define GPIO_FSMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8) +#define GPIO_FSMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9) +#define GPIO_FSMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10) +#define GPIO_FSMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11) +#define GPIO_FSMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12) +#define GPIO_FSMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13) +#define GPIO_FSMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14) +#define GPIO_FSMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15) +#define GPIO_FSMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8) +#define GPIO_FSMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9) +#define GPIO_FSMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10) +#define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8) +#define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9) +#define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10) +#define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11) +#define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12) +#define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13) +#define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14) +#define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15) +#define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1) +#define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6) +#define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7) +#define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9) +#define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10) +#define GPIO_FSMC_INT (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7) +#define GPIO_FSMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0) +#define GPIO_FSMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1) +#define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4) +#define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5) +#define GPIO_FSMC_NCE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_FSMC_NCE_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_FSMC_NE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7) +#define GPIO_FSMC_NE1_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_FSMC_NE2_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_FSMC_NE2_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_FSMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10) +#define GPIO_FSMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12) +#define GPIO_FSMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_FSMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4) +#define GPIO_FSMC_NWAIT_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_FSMC_NWAIT_2 (GPIO_ALT|GPIO_AF9 |GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5) +#define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5) +#define GPIO_FSMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2) +#define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7) +#define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8) +#define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15) +#define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4) +#define GPIO_FSMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3) +#define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6) +#define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11) +#define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0) +#define GPIO_FSMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5) + +/* HDMI-CEC Controller */ + +#define GPIO_HDMICEC_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6) +#define GPIO_HDMICEC_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN15) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1) +#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4) +#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11) +#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0) +#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5) +#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2) +#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8) +#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7) +#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9) +#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8) +#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) + +#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14) +#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) +#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN15) +#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) +#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11) +#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13) +#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) +#define GPIO_I2C4_SMBA_4 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) + +/* I2S */ + +#define GPIO_I2S1_CK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN5) +#define GPIO_I2S1_CK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S1_CK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN11) +#define GPIO_I2S1_MCK (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN4) +#define GPIO_I2S1_SD_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN7) +#define GPIO_I2S1_SD_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S1_SD_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN7) +#define GPIO_I2S1_WS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2S1_WS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN4) +#define GPIO_I2S1_WS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN10) + +#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN13) +#define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN3) +#define GPIO_I2S2_CK_5 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN1) +#define GPIO_I2S2_CK_6 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN12) +#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN6) +#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN15) +#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN1) +#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN3) +#define GPIO_I2S2_SD_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN3) +#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTI|GPIO_PIN0) +#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN4) +#define GPIO_I2S2_WS_5 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN11) + +#define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN10) +#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN7) +#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN6) +#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN12) +#define GPIO_I2S3_SD_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN2) +#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN15) +#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN4) + +#define GPIO_I2S4_SD_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2S4_SD_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN9) + +/* JTAG */ + +#define GPIO_JTCK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) +#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTMS (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) +#define GPIO_NJTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) + +/* LCD-TFT Display Controller (LTDC) */ + +#define GPIO_LTDC_R0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) +#define GPIO_LTDC_R0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2) +#define GPIO_LTDC_R0_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15) +#define GPIO_LTDC_R1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_LTDC_R1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3) +#define GPIO_LTDC_R1_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0) +#define GPIO_LTDC_R2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_LTDC_R2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_LTDC_R2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN8) +#define GPIO_LTDC_R2_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN1) +#define GPIO_LTDC_R3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) +#define GPIO_LTDC_R3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN2) +#define GPIO_LTDC_R3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_LTDC_R4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_LTDC_R4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_LTDC_R4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) +#define GPIO_LTDC_R4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN3) +#define GPIO_LTDC_R5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_LTDC_R5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) +#define GPIO_LTDC_R5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) +#define GPIO_LTDC_R5_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN4) +#define GPIO_LTDC_R5_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_LTDC_R6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_LTDC_R6_2 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_LTDC_R6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) +#define GPIO_LTDC_R6_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN5) +#define GPIO_LTDC_R7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN15) +#define GPIO_LTDC_R7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6) +#define GPIO_LTDC_R7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN6) +#define GPIO_LTDC_R7_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0) + +#define GPIO_LTDC_B0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4) +#define GPIO_LTDC_B0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_LTDC_B0_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12) +#define GPIO_LTDC_B1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LTDC_B1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13) +#define GPIO_LTDC_B1_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_LTDC_B2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_LTDC_B2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_LTDC_B2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN14) +#define GPIO_LTDC_B2_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_LTDC_B2_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_LTDC_B3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) +#define GPIO_LTDC_B3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_LTDC_B3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN15) +#define GPIO_LTDC_B3_4 (GPIO_ALT|GPIO_AF13|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_LTDC_B4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12) +#define GPIO_LTDC_B4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN4) +#define GPIO_LTDC_B4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN3) +#define GPIO_LTDC_B4_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LTDC_B4_5 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_LTDC_B5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_LTDC_B5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5) +#define GPIO_LTDC_B5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN4) +#define GPIO_LTDC_B6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_LTDC_B6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6) +#define GPIO_LTDC_B6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN5) +#define GPIO_LTDC_B7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_LTDC_B7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7) +#define GPIO_LTDC_B7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN6) + +#define GPIO_LTDC_G0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_LTDC_G0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN7) +#define GPIO_LTDC_G0_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_LTDC_G1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) +#define GPIO_LTDC_G1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8) +#define GPIO_LTDC_G1_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_LTDC_G2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_LTDC_G2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) +#define GPIO_LTDC_G2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9) +#define GPIO_LTDC_G2_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15) +#define GPIO_LTDC_G3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_LTDC_G3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_LTDC_G3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_LTDC_G3_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10) +#define GPIO_LTDC_G3_5 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_LTDC_G3_6 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12) +#define GPIO_LTDC_G4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_LTDC_G4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN15) +#define GPIO_LTDC_G4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11) +#define GPIO_LTDC_G4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4) +#define GPIO_LTDC_G4_5 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13) +#define GPIO_LTDC_G5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_LTDC_G5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0) +#define GPIO_LTDC_G5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0) +#define GPIO_LTDC_G5_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4) +#define GPIO_LTDC_G6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_LTDC_G6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN1) +#define GPIO_LTDC_G6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1) +#define GPIO_LTDC_G6_4 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN11) +#define GPIO_LTDC_G7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3) +#define GPIO_LTDC_G7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2) +#define GPIO_LTDC_G7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN2) +#define GPIO_LTDC_G7_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_LTDC_G7_5 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8) + +#define GPIO_LTDC_HSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_LTDC_HSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10) +#define GPIO_LTDC_HSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN12) +#define GPIO_LTDC_VSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) +#define GPIO_LTDC_VSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) +#define GPIO_LTDC_VSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13) +#define GPIO_LTDC_CLK_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) +#define GPIO_LTDC_CLK_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7) +#define GPIO_LTDC_CLK_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN14) +#define GPIO_LTDC_DE_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_LTDC_DE_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10) +#define GPIO_LTDC_DE_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN7) + +/* Low Power Timer */ + +#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) +#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN14) +#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1) +#define GPIO_LPTIM1_IN2_4 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN2) +#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) + +/* Clocks outputs */ + +#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) + +/* Management data input/output */ + +#define MDIOS_MDIO_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2) +#define MDIOS_MDC_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define MDIOS_MDC_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1) +#define MDIOS_MDIO_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10) + +/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */ + +#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10) +#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) + +#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_OTGHSFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_OTGHSFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12) + +#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) + +#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0) +#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1) +#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10) +#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12) +#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13) +#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2) +#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4) +#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0) + +/* QuadSPI */ + +#define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8) +#define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN9) +#define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN11) +#define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9) +#define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN10) +#define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN12) +#define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN2) +#define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN7) +#define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN1) +#define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN13) +#define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN6) +#define GPIO_QUADSPI_BK1_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6) +#define GPIO_QUADSPI_BK1_NCS_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN10) + +#define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN7) +#define GPIO_QUADSPI_BK2_IO0_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTH|GPIO_PIN2) +#define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN8) +#define GPIO_QUADSPI_BK2_IO1_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTH|GPIO_PIN3) +#define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9) +#define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN9) +#define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10) +#define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN14) +#define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN11) + +#define GPIO_QUADSPI_CLK_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN2) +#define GPIO_QUADSPI_CLK_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN10) + +/* RTC */ + +#define GPIO_RTC_REFIN (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15) + +/* Serial Audio Interface */ + +#define GPIO_SAI1_FS_A (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN4) +#define GPIO_SAI1_FS_B (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN9) +#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN2) +#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN7) +#define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN7) +#define GPIO_SAI1_SCK_A (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN5) +#define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN8) +#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN2) +#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN1) +#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN6) +#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN3) +#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN6) +#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN12) +#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN7) +#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN12) +#define GPIO_SAI2_FS_B_4 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN0) +#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0) +#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN4) +#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1) +#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI2_MCLK_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN3) +#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN13) +#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN5) +#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN2) +#define GPIO_SAI2_SCK_B_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN2) +#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN11) +#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN6) +#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN0) +#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11) +#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10) + +/* SD/MMC */ + +#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2) +#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + +#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SDMMC2_D1_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN) +#define GPIO_SDMMC2_D3_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SDMMC2_D0_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SDMMC2_D1_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_SDMMC2_D2_2 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SDMMC2_D3_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SDMMC2_D4 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC2_D5 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC2_D6 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC2_D7 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + + +/* SPDIFRX */ + +#define GPIO_SPDIFRX_IN0_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SPDIFRX_IN0_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SPDIFRX_IN1_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SPDIFRX_IN1_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN8) +#define GPIO_SPDIFRX_IN2_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN8) +#define GPIO_SPDIFRX_IN2_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN4) +#define GPIO_SPDIFRX_IN3_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SPDIFRX_IN3_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN5) + +/* SPI */ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN10) +#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN11) + +#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12) +#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI2_NSS_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11) +#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13) +#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3) +#define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1) +#define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTIA|GPIO_PIN12) + +#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN2) +#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10) + +#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5) +#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2) +#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12) + +#define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8) +#define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7) +#define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9) +#define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN11) +#define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6) +#define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5) +#define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7) +#define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_SPI6_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SPI6_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN14) +#define GPIO_SPI6_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN8) +#define GPIO_SPI6_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN13) +#define GPIO_SPI6_MISO_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI6_MOSI_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI6_NSS_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI6_SCK_2 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI6_MISO_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI6_MOSI_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI6_NSS_3 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI6_SCK_3 (GPIO_ALT|GPIO_AF8|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) + +/* Timers */ + +#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15) +#define GPIO_TIM1_BKIN2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7) + +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2) + +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) + +#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10) +#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) + +#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN11) +#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) + +#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN12) +#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) + +#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN0) +#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0) + +#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4) +#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN1) +#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5) +#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5) +#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13) +#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6) +#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6) +#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14) +#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7) +#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7) +#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15) +#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2) +#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2) +#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN3) + +#define GPIO_TIM9_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM9_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM9_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM9_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) + +#define GPIO_TIM10_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM10_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) + +#define GPIO_TIM11_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM11_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) + +#define GPIO_TIM12_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN6) +#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9) +#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) + +#define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM13_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8) + +#define GPIO_TIM14_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM14_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) + +/* Trace */ + +#define GPIO_TRACECLK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2) +#define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN1) +#define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TRACED0_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN13) +#define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TRACED1_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN14) +#define GPIO_TRACED2_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN2) +#define GPIO_TRACED2_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TRACED3_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN12) +#define GPIO_TRACED3_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TRACESWO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) + +/* UARTs/USARTs */ + +#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_AF4|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) + +#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7) +#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3) +#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4) +#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) + +#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12) +#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12) +#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10) +#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13) +#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11) +#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14) +#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12) +#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9) +#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8) + +#define GPIO_UART4_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN0) +#define GPIO_UART4_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN15) +#define GPIO_UART4_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15) +#define GPIO_UART4_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN14) +#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_UART4_RX_3 (GPIO_ALT|GPIO_AF6|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_UART4_RX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_UART4_RX_5 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_UART4_RX_6 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) +#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_UART4_TX_3 (GPIO_ALT|GPIO_AF6|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_UART4_TX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_UART4_TX_5 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) + +#define GPIO_UART5_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN9) +#define GPIO_UART5_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8) +#define GPIO_UART5_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2) +#define GPIO_UART5_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12) +#define GPIO_UART5_RX_2 (GPIO_ALT|GPIO_AF1|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_UART5_TX_2 (GPIO_ALT|GPIO_AF1|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_UART5_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_UART5_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_UART5_RX_4 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_UART5_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8) +#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7) +#define GPIO_USART6_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN13) +#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15) +#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12) +#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8) +#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) + +#define GPIO_UART7_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN10) +#define GPIO_UART7_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN9) +#define GPIO_UART7_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN9) +#define GPIO_UART7_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN8) +#define GPIO_UART7_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7) +#define GPIO_UART7_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) +#define GPIO_UART7_RX_3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_UART7_RX_4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_UART7_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_UART7_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) +#define GPIO_UART7_TX_3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_UART7_TX_4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_UART8_CTS (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN14) +#define GPIO_UART8_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN15) +#define GPIO_UART8_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) +#define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h new file mode 100644 index 0000000000..21f78951f9 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h @@ -0,0 +1,159 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F76XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */ +#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register 1 */ + +#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ +#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT) +# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */ +# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */ +# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */ +# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ +#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ +#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */ +#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */ +#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ +#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */ +#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */ +# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */ +# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */ +#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */ +#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */ +#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */ +#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT) +# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */ +# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */ + +/* Power control/status register 1 */ + +#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */ +#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */ +#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */ +#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ +#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ +#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ +#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */ +#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT) +# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */ +# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */ + +/* Power control register 2 */ + +#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */ +#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */ +#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */ +#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */ +#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */ +#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */ +#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */ +# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */ +# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */ +# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */ +# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */ +# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */ +# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */ + +/* Power control/status register 2 */ + +#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */ +#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */ +#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */ +#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */ +#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */ +#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */ +#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */ +#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */ +#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */ +#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */ +#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ +#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h new file mode 100644 index 0000000000..dfe85e9da2 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -0,0 +1,737 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_CIR_OFFSET 0x000c /* Clock interrupt register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0010 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0014 /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */ +#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */ +#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */ +#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */ +#define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */ +#define STM32_RCC_DCKCFGR1_OFFSET 0x008c /* Dedicated clocks configuration register 1 */ +#define STM32_RCC_DCKCFGR2_OFFSET 0x0090 /* Dedicated clocks configuration register 2 */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR) +#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET) +#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET) +#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET) +#define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET) +#define STM32_RCC_DCKCFGR1 (STM32_RCC_BASE+STM32_RCC_DCKCFGR1_OFFSET) +#define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */ +#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) +#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */ +#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT) +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */ +#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */ +#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */ +#define RCC_CR_PLLI2SON (1 << 26) /* Bit 26: PLLI2S enable */ +#define RCC_CR_PLLI2SRDY (1 << 27) /* Bit 27: PLLI2S clock ready flag */ +#define RCC_CR_PLLSAION (1 << 28) /* Bit 28: PLLSAI enable */ +#define RCC_CR_PLLSAIRDY (1 << 29) /* Bit 29: PLLSAI clock ready flag */ + +/* PLL configuration register */ + +#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S) + * input clock divider */ +#define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT) +# define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */ +#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */ +#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT) +# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */ +#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */ +#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT) +# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ +# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */ +# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */ +# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */ +# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */ +#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) + * entry clock source */ +# define RCC_PLLCFG_PLLSRC_HSI (0) +# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC +#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider + * (USB OTG FS, SDIO and RNG clocks) */ +#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT) +# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */ + +#define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: PLL division factor for DSI clock */ +#define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT) +# define RCC_PLLCFG_PLLR(n) ((n) << RCC_PLLCFG_PLLR_SHIFT) /* n=2..7 */ + +#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */ + +/* Clock configuration register */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ +# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ +#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ +#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) +# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) +# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */ +#define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT) +# define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */ +#define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */ +#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */ +# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */ +# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */ +# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */ +#define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ +#define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) +# define RCC_CFGR_MCO1PRE_NONE (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */ +# define RCC_CFGR_MCO1PRE_DIV2 (4 << RCC_CFGR_MCO1PRE_SHIFT) /* 100: division by 2 */ +# define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */ +# define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */ +# define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */ +#define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT) +# define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */ +# define RCC_CFGR_MCO2PRE_DIV2 (4 << RCC_CFGR_MCO2PRE_SHIFT) /* 100: division by 2 */ +# define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */ +# define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */ +# define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */ +#define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT) +# define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */ +# define RCC_CFGR_MCO2_PLLI2S (1 << RCC_CFGR_MCO2_SHIFT) /* 01: PLLI2S clock selected */ +# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 10: HSE oscillator clock selected */ +# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO2_SHIFT) /* 11: PLL clock selected */ + +/* Clock interrupt register */ + +#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) /* Bit 5: PLLI2S Ready Interrupt flag */ +#define RCC_CIR_PLLSAIRDYF (1 << 6) /* Bit 6: PLLSAI Ready Interrupt flag */ +#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) /* Bit 13: PLLI2S Ready Interrupt enable */ +#define RCC_CIR_PLLSAIRDYIE (1 << 14) /* Bit 14: PLLSAI Ready Interrupt enable */ +#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) /* Bit 21: PLLI2S Ready Interrupt clear */ +#define RCC_CIR_PLLSAIRDYC (1 << 22) /* Bit 22: PLLSAI Ready Interrupt clear */ +#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_AHB1RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_AHB1RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_AHB1RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_AHB1RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_AHB1RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ +#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ +#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ +#define RCC_AHB1RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ +#define RCC_AHB1RSTR_GPIOJRST (1 << 9) /* Bit 9: IO port J reset */ +#define RCC_AHB1RSTR_GPIOKRST (1 << 10) /* Bit 10: IO port K reset */ +#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 CRC reset */ +#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */ +#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */ +#define RCC_AHB1RSTR_DMA2DRST (1 << 23) /* Bit 23: DMA2D reset */ +#define RCC_AHB1RSTR_ETHMACRST (1 << 25) /* Bit 25: Ethernet MAC reset */ +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_DCMIRST (1 << 0) /* Bit 0: Camera interface reset */ +#define RCC_AHB2RSTR_JPEGRST (1 << 1) /* Bit 1: Jpeg codec reset */ +#define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */ +#define RCC_AHB2RSTR_HASHRST (1 << 5) /* Bit 5: Hash module reset */ +#define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */ +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */ + +/* AHB3 peripheral reset register */ + +#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */ +#define RCC_AHB3RSTR_QSPIRST (1 << 1) /* Bit 1: Quad SPI memory controller reset */ + +/* APB1 Peripheral reset register */ + +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ +#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */ +#define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */ +#define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */ +#define RCC_APB1RSTR_LPTIM1RST (1 << 9) /* Bit 9: LPTIM1 reset */ +#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window watchdog reset */ +#define RCC_APB1RSTR_CAN3RST (1 << 13) /* Bit 13: CAN3 reset */ +#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */ +#define RCC_APB1RSTR_SPDIFRXRST (1 << 16) /* Bit 16: SPDIFRX reset */ +#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ +#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ +#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: USART 4 reset */ +#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: USART 5 reset */ +#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */ +#define RCC_APB1RSTR_I2C3RST (1 << 23) /* Bit 23: I2C 3 reset */ +#define RCC_APB1RSTR_I2C4RST (1 << 24) /* Bit 24: I2C 4 reset */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */ +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */ +#define RCC_APB1RSTR_CECRST (1 << 27) /* Bit 27: CEC reset */ +#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ +#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */ +#define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: USART 7 reset */ +#define RCC_APB1RSTR_UART8RST (1 << 31) /* Bit 31: USART 8 reset */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 4) /* Bit 4: USART1 reset */ +#define RCC_APB2RSTR_USART6RST (1 << 5) /* Bit 5: USART6 reset */ +#define RCC_APB2RSTR_SDMMC2RST (1 << 7) /* Bit 7: SDMMC2 reset */ +#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */ +#define RCC_APB2RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */ +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */ +#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */ +#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */ +#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */ +#define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */ +#define RCC_APB2RSTR_SPI6RST (1 << 21) /* Bit 21: SPI 6 reset */ +#define RCC_APB2RSTR_SAI1RST (1 << 22) /* Bit 22: SAI 1 reset */ +#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 23: SAI 2 reset */ +#define RCC_APB2RSTR_LTDCRST (1 << 26) /* Bit 26: LTDC reset */ +#define RCC_APB2RSTR_DSIRST (1 << 27) /* Bit 27: DSI reset */ +#define RCC_APB2RSTR_DFSDM1RST (1 << 29) /* Bit 29: DFSDM1 reset */ +#define RCC_APB2RSTR_MDIORST (1 << 30) /* Bit 30: MDIO reset */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_GPIOEN(n) (1 << (n)) +#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */ +#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */ +#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */ +#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */ +#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */ +#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */ +#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */ +#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */ +#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */ +#define RCC_AHB1ENR_GPIOJEN (1 << 9) /* Bit 9: IO port J clock enable */ +#define RCC_AHB1ENR_GPIOKEN (1 << 10) /* Bit 10: IO port K clock enable */ +#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */ +#define RCC_AHB1ENR_DTCMRAMEN (1 << 20) /* Bit 20: DTCM RAM clock enable */ +#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */ +#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */ +#define RCC_AHB1ENR_DMA2DEN (1 << 23) /* Bit 23: DMA2D clock enable */ +#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */ +#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */ +#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */ +#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */ +#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */ +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_DCMIEN (1 << 0) /* Bit 0: Camera interface enable */ +#define RCC_AHB2ENR_JPEGEN (1 << 1) /* Bit 1: Jpeg codec enable */ +#define RCC_AHB2ENR_CRYPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable */ +#define RCC_AHB2ENR_HASHEN (1 << 5) /* Bit 5: Hash modules clock enable */ +#define RCC_AHB2ENR_RNGEN (1 << 6) /* Bit 6: Random number generator clock enable */ +#define RCC_AHB2ENR_OTGFSEN (1 << 7) /* Bit 7: USB OTG FS clock enable */ + +/* AHB3 Peripheral Clock enable register */ + +#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */ +#define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: Quad SPI memory controller clock enable */ + +/* APB1 Peripheral Clock enable register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: TIM 2 clock enable */ +#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: TIM 3 clock enable */ +#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: TIM 4 clock enable */ +#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: TIM 5 clock enable */ +#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: TIM 6 clock enable */ +#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: TIM 7 clock enable */ +#define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM 12 clock enable */ +#define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM 13 clock enable */ +#define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM 14 clock enable */ +#define RCC_APB1ENR_LPTIM1EN (1 << 9) /* Bit 9: LPTIM 1 clock enable */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ +#define RCC_APB1ENR_CAN3EN (1 << 13) /* Bit 13: CAN 3 clock enable */ +#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI 3 clock enable */ +#define RCC_APB1ENR_SPDIFRXEN (1 << 16) /* Bit 16: SPDIFRX clock enable */ +#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ +#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */ +#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */ +#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ +#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C 3 clock enable */ +#define RCC_APB1ENR_I2C4EN (1 << 24) /* Bit 24: I2C 4 clock enable */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */ +#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */ +#define RCC_APB1ENR_CECEN (1 << 27) /* Bit 27: CEC clock enable */ +#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ +#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */ +#define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ +#define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: TIM 1 clock enable */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: TIM 8 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: USART 1 clock enable */ +#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: USART 6 clock enable */ +#define RCC_APB2ENR_SDMMC2EN (1 << 7) /* Bit 7: SDMMC 2 clock enable */ +#define RCC_APB2ENR_ADC1EN (1 << 8) /* Bit 8: ADC 1 clock enable */ +#define RCC_APB2ENR_ADC2EN (1 << 9) /* Bit 9: ADC 2 clock enable */ +#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC 3 clock enable */ +#define RCC_APB2ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC 1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */ +#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI 4 clock enable */ +#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */ +#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM 9 clock enable */ +#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM1 0 clock enable */ +#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM 11 clock enable */ +#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI 5 clock enable */ +#define RCC_APB2ENR_SPI6EN (1 << 21) /* Bit 21: SPI 6 clock enable */ +#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: SAI 1 clock enable */ +#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: SAI 2 clock enable */ +#define RCC_APB2ENR_LTDCEN (1 << 26) /* Bit 26: LTDC clock enable */ +#define RCC_APB2ENR_DSIEN (1 << 27) /* Bit 27: DSI clock enable */ +#define RCC_APB2ENR_DFSDM1EN (1 << 29) /* Bit 29: DFSDM1 clock enable */ +#define RCC_APB2ENR_MDIOEN (1 << 30) /* Bit 30: MDIO clock enable */ + +/* RCC AHB1 low power mode peripheral clock enable register */ + +#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n)) +#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOJLPEN (1 << 9) /* Bit 8: IO port J clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOKLPEN (1 << 10) /* Bit 10: IO port K clock enable during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */ +#define RCC_AHB1LPENR_AXILPEN (1 << 13) /* Bit 12: AXI to AHB bridge clock enable during Sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DTCMLPEN (1 << 20) /* Bit 20: DTCM RAM clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) /* Bit 23: DMA2D clock enable during Sleep mode */ +#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */ +#define RCC_AHB1LPENR_ETHTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */ +#define RCC_AHB1LPENR_ETHRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */ + +#define RCC_AHB1LPENR_ETHPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */ +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */ +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */ + +/* RCC AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* Bit 0: Camera interface enable during Sleep mode */ +#define RCC_AHB2LPENR_JPEGLPEN (1 << 1) /* Bit 1: Jpeg codec enable during Sleep mode */ +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* Bit 5: Hash modules clock enable during Sleep mode */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */ +#define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */ + +/* RCC AHB3 low power mode peripheral clock enable register */ + +#define RCC_AHB3LPENR_FSMLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock + * enable during Sleep mode */ +#define RCC_AHB3LPENR_QSPILPEN (1 << 1) /* Bit 1: Quad SPI memory controller clock + * enable during Sleep mode */ + +/* RCC APB1 low power mode peripheral clock enable register */ + +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM 5 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM 6 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM 7 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM 12 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM 13 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM 14 clock enable during Sleep mode */ +#define RCC_APB1LPENR_LPTIM1LPEN (1 << 9) /* Bit 9: LPTIM 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPDIFRXLPEN (1 << 16) /* Bit 16: SPDIFRX clock enable during Sleep mode */ +#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART5LPEN (1 << 20) /* Bit 20: UART 5 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C4LPEN (1 << 24) /* Bit 24: I2C 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CAN2LPEN (1 << 26) /* Bit 26: CAN 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CECLPEN (1 << 27) /* Bit 27: CEC clock enable during Sleep mode */ +#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */ +#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART 7 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART 8 clock enable during Sleep mode */ + +/* RCC APB2 low power mode peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM 8 clock enable during Sleep mode */ +#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* Bit 5: USART 6 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SDMMC2LPEN (1 << 7) /* Bit 7: SDMMC 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) /* Bit 8: ADC 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) /* Bit 9: ADC 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC 3 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI 4 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM 9 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM 10 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM 11 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI 5 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI6LPEN (1 << 21) /* Bit 21: SPI 6 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* Bit 22: SAI 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* Bit 23: SAI 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_LTDCLPEN (1 << 26) /* Bit 26: LTDC clock enable during Sleep mode */ +#define RCC_APB2LPENR_DSILPEN (1 << 27) /* Bit 27: DSI clock enable during Sleep mode */ +#define RCC_APB2LPENR_DFSDM1LPEN (1 << 29) /* Bit 29: DFSDM1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_MDIOLPEN (1 << 30) /* Bit 30: MDIO clock enable during Sleep mode */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + +/* Control/status register */ + +#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */ +#define RCC_CSR_BORRSTF (1 << 25) /* Bit 25: BOR reset flag */ +#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* Spread spectrum clock generation register */ + +#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */ +#define RCC_SSCGR_MODPER_MASK (0x1fff << RCC_SSCGR_MODPER_SHIFT) +# define RCC_SSCGR_MODPER(n) ((n) << RCC_SSCGR_MODPER_SHIFT) +#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */ +#define RCC_SSCGR_INCSTEP_MASK (0x7fff << RCC_SSCGR_INCSTEP_SHIFT) +# define RCC_SSCGR_INCSTEP(n) ((n) << RCC_SSCGR_INCSTEP_SHIFT) +#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */ +#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */ + +/* PLLI2S configuration register */ + +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S multiplication factor for VCO */ +#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIFRX clock */ +#define RCC_PLLI2SCFGR_PLLI2SP_MASK (3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SP(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */ +#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ +#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SR(n) (uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) + +/* PLLSAI configuration register */ + +#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */ +#define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */ +#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */ +#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIR_SHIFT (28) /* Bits 28-30: PLLSAI division factor for LCD clock */ +#define RCC_PLLSAICFGR_PLLSAIR_MASK (7 << RCC_PLLSAICFGR_PLLSAIR_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIR(n) ((n) << RCC_PLLSAICFGR_PLLSAIR_SHIFT) + +/* Dedicated clocks configuration register 1 */ + +#define RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division factor for I2S clock */ +#define RCC_DCKCFGR1_PLLI2SDIVQ_MASK (0x1F << RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT) +# define RCC_DCKCFGR1_PLLI2SDIVQ(n) ((n) << RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT) +#define RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT (8) /* Bits 8-12: PLLSAI division factor for SAI clock */ +#define RCC_DCKCFGR1_PLLSAIDIVQ_MASK (0x1F << RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT) +# define RCC_DCKCFGR1_PLLSAIDIVQ(n) ((n) << RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT) + +#define RCC_DCKCFGR1_PLLSAIDIVR_SHIFT (16) /* Bits 16-17: PLLSAI division factor for LCD_CLK clock */ +#define RCC_DCKCFGR1_PLLSAIDIVR_MASK (0x3 << RCC_DCKCFGR1_PLLSAIDIVR_SHIFT) +# define RCC_DCKCFGR1_PLLSAIDIVR(n) ((n) << RCC_DCKCFGR1_PLLSAIDIVR_SHIFT) + +#define RCC_DCKCFGR1_SAI1SEL_SHIFT (20) /* Bits 20-21: SAI 1 clock source selection */ +#define RCC_DCKCFGR1_SAI1SEL_MASK (0x3 << RCC_DCKCFGR1_SAI1SEL_SHIFT) +# define RCC_DCKCFGR1_SAI1SEL(n) ((n) << RCC_DCKCFGR1_SAI1SEL_SHIFT) + +#define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ +#define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) +# define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) +#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ +#define RCC_DCKCFGR1_DFSDM1SEL (1 << 25) /* Bit 25: DFSDM1 clock prescaler selection */ +#define RCC_DCKCFGR1_ADFSDM1SEL (1 << 26) /* Bit 26: DFSDM1 AUDIO clock prescaler selection */ + +/* Dedicated clocks configuration register 2 */ + +#define RCC_DCKCFGR2_USART1SEL_SHIFT (0) /* Bits 0-1: USART 1 clock source selection */ +#define RCC_DCKCFGR2_USART1SEL_MASK (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) +# define RCC_DCKCFGR2_USART1SEL_APB (0 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_SYSCLK (1 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* System clock is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_HSI (2 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* HSI clock is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_LSE (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* LSE clock is selected as USART 1 clock */ +#define RCC_DCKCFGR2_USART2SEL_SHIFT (2) /* Bits 2-3: USART 2 clock source selection */ +#define RCC_DCKCFGR2_USART2SEL_MASK (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) +# define RCC_DCKCFGR2_USART2SEL_APB (0 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_SYSCLK (1 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* System clock is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_HSI (2 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* HSI clock is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_LSE (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* LSE clock is selected as USART 2 clock */ +#define RCC_DCKCFGR2_UART4SEL_SHIFT (6) /* Bits 6-7: UART 4 clock source selection */ +#define RCC_DCKCFGR2_UART4SEL_MASK (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) +# define RCC_DCKCFGR2_UART4SEL_APB (0 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_SYSCLK (1 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* System clock is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_HSI (2 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* HSI clock is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_LSE (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* LSE clock is selected as UART 4 clock */ +#define RCC_DCKCFGR2_UART5SEL_SHIFT (8) /* Bits 8-9: UART 5 clock source selection */ +#define RCC_DCKCFGR2_UART5SEL_MASK (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) +# define RCC_DCKCFGR2_UART5SEL_APB (0 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_SYSCLK (1 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* System clock is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_HSI (2 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* HSI clock is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_LSE (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* LSE clock is selected as UART 5 clock */ +#define RCC_DCKCFGR2_USART6SEL_SHIFT (10) /* Bits 10-11: USART 6 clock source selection */ +#define RCC_DCKCFGR2_USART6SEL_MASK (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) +# define RCC_DCKCFGR2_USART6SEL_APB (0 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_SYSCLK (1 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* System clock is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_HSI (2 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* HSI clock is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_LSE (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* LSE clock is selected as USART 6 clock */ +#define RCC_DCKCFGR2_UART7SEL_SHIFT (12) /* Bits 12-13: UART 7 clock source selection */ +#define RCC_DCKCFGR2_UART7SEL_MASK (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) +# define RCC_DCKCFGR2_UART7SEL_APB (0 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_SYSCLK (1 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* System clock is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_HSI (2 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* HSI clock is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_LSE (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* LSE clock is selected as UART 7 clock */ +#define RCC_DCKCFGR2_UART8SEL_SHIFT (14) /* Bits 14-15: UART 8 clock source selection */ +#define RCC_DCKCFGR2_UART8SEL_MASK (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) +# define RCC_DCKCFGR2_UART8SEL_APB (0 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_SYSCLK (1 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* System clock is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_HSI (2 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* HSI clock is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_LSE (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* LSE clock is selected as UART 8 clock */ +#define RCC_DCKCFGR2_I2C1SEL_SHIFT (16) /* Bits 16-17: I2C1 clock source selection */ +#define RCC_DCKCFGR2_I2C1SEL_MASK (3 << RCC_DCKCFGR2_I2C1SEL_SHIFT) +# define RCC_DCKCFGR2_I2C1SEL_APB (0 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 1 clock */ +# define RCC_DCKCFGR2_I2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* System clock is selected as I2C 1 clock */ +# define RCC_DCKCFGR2_I2C1SEL_HSI (2 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* HSI clock is selected as I2C 1 clock */ +#define RCC_DCKCFGR2_I2C2SEL_SHIFT (18) /* Bits 18-19: I2C2 clock source selection */ +#define RCC_DCKCFGR2_I2C2SEL_MASK (3 << RCC_DCKCFGR2_I2C2SEL_SHIFT) +# define RCC_DCKCFGR2_I2C2SEL_APB (0 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 2 clock */ +# define RCC_DCKCFGR2_I2C2SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* System clock is selected as I2C 2 clock */ +# define RCC_DCKCFGR2_I2C2SEL_HSI (2 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* HSI clock is selected as I2C 2 clock */ +#define RCC_DCKCFGR2_I2C3SEL_SHIFT (20) /* Bits 20-21: I2C3 clock source selection */ +#define RCC_DCKCFGR2_I2C3SEL_MASK (3 << RCC_DCKCFGR2_I2C3SEL_SHIFT) +# define RCC_DCKCFGR2_I2C3SEL_APB (0 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 3 clock */ +# define RCC_DCKCFGR2_I2C3SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* System clock is selected as I2C 3 clock */ +# define RCC_DCKCFGR2_I2C3SEL_HSI (2 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* HSI clock is selected as I2C 3 clock */ +#define RCC_DCKCFGR2_I2C4SEL_SHIFT (22) /* Bits 22-23: I2C4 clock source selection */ +#define RCC_DCKCFGR2_I2C4SEL_MASK (3 << RCC_DCKCFGR2_I2C4SEL_SHIFT) +# define RCC_DCKCFGR2_I2C4SEL_APB (0 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 4 clock */ +# define RCC_DCKCFGR2_I2C4SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* System clock is selected as I2C 4 clock */ +# define RCC_DCKCFGR2_I2C4SEL_HSI (2 << RCC_DCKCFGR2_I2C4SEL_SHIFT) /* HSI clock is selected as I2C 4 clock */ +#define RCC_DCKCFGR2_LPTIM1SEL_SHIFT (24) /* Bits 24-25: Low power timer 1 clock source selection */ +#define RCC_DCKCFGR2_LPTIM1SEL_MASK (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) +# define RCC_DCKCFGR2_LPTIM1SEL_APB (0 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_SYSCLK (1 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* System clock is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_HSI (2 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* HSI clock is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_LSE (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* LSE clock is selected as LPTIM 1 clock */ +#define RCC_DCKCFGR2_CECSEL_SHIFT (26) /* Bit 26: HDMI-CEC clock source selection */ +#define RCC_DCKCFGR2_CECSEL_MASK (1 << RCC_DCKCFGR2_CECSEL_SHIFT) +# define RCC_DCKCFGR2_CECSEL_LSE (0 << RCC_DCKCFGR2_CECSEL_SHIFT) /* LSE clock is selected as HDMI-CEC clock */ +# define RCC_DCKCFGR2_CECSEL_HSI (1 << RCC_DCKCFGR2_CECSEL_SHIFT) /* HSI clock is selected as HDMI-CEC clock */ +#define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48MHz clock source selection */ +#define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) +# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLL is selected */ +# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /*48MHz clock from PLLSAI is selected */ +#define RCC_DCKCFGR2_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC clock source selection */ +#define RCC_DCKCFGR2_SDMMCSEL_MASK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) +# define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ +# define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ +#define RCC_DCKCFGR2_SDMMC2SEL_SHIFT (29) /* Bit 29: SDMMC 2 clock source selection */ +#define RCC_DCKCFGR2_SDMMC2SEL_MASK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) +# define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC 2 clock */ +# define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC 2 clock */ +#define RCC_DCKCFGR2_DSISEL_SHIFT (30) /* Bit 30: DSI clock source selection */ +#define RCC_DCKCFGR2_DSISELL_MASK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) +# define RCC_DCKCFGR2_DSISEL_48MHZ (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* 48 MHz clock is selected as DSI clock */ +# define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h new file mode 100644 index 0000000000..78d25453f6 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h @@ -0,0 +1,180 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ + +#define STM32_SYSCFG_CBR_OFFSET 0x001c /* Class B register */ +#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET) + +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) + +#define STM32_SYSCFG_CBR (STM32_SYSCFG_BASE+STM32_SYSCFG_CBR_OFFSET) +#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* SYSCFG memory remap register */ + +#define SYSCFG_MEMRMP_MEMBOOT (1 << 0) /* Bit 0: Memory boot mapping */ +#define SYSCFG_MEMRMP_MEMBOOT_ADD0 (0 << 0) /* 0=BOOT_ADD0 defines */ +#define SYSCFG_MEMRMP_MEMBOOT_ADD1 (1 << 0) /* 1=BOOT_ADD1 defines */ +#define SYSCFG_MEMRMP_SWP_FB (1 << 8) /* Bits 8: Flash Bank swap */ +#define SYSCFG_MEMRMP_SWP_FB_BNK1 (0 << 8) /* Flash Bank 1 mapped at 0x08000000 + * Flash Bank 2 mapped at 0x08100000 */ +#define SYSCFG_MEMRMP_SWP_FB_BNK2 (1 << 8) /* Flash Bank 2 mapped at 0x08000000 + * Flash Bank 1 mapped at 0x08100000 */ +#define SYSCFG_MEMRMP_SWPFMC_SHIFT (10) /* Bits 10-11: FMC memory mapping swap */ +#define SYSCFG_MEMRMP_SWPFMC_MASK (3 << SYSCFG_MEMRMP_SWPFMC_SHIFT) +# define SYSCFG_MEMRMP_SWPFMC_NONE (0 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* No FMC memory mapping swapping */ +# define SYSCFG_MEMRMP_SWPFMC_NORRAM (1 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* NOR/RAM and SDRAM memory mapping swapped */ + +/* SYSCFG peripheral mode configuration register */ + +#define SYSCFG_PMC_I2C1_FMP (1 << 0) /* Bit 0: I2C1 Fast-mode Plus Enable */ +#define SYSCFG_PMC_I2C2_FMP (1 << 1) /* Bit 1: I2C2 Fast-mode Plus Enable */ +#define SYSCFG_PMC_I2C3_FMP (1 << 2) /* Bit 2: I2C3 Fast-mode Plus Enable */ +#define SYSCFG_PMC_I2C4_FMP (1 << 3) /* Bit 3: I2C4 Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB6_FMP (1 << 4) /* Bit 4: PB6 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB7_FMP (1 << 5) /* Bit 5: PB7 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB8_FMP (1 << 6) /* Bit 6: PB8 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_PB9_FMP (1 << 7) /* Bit 7: PB9 IO pads Fast-mode Plus Enable */ +#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */ +#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */ +#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */ +#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */ +# define SYSCFG_PMC_MII_SEL (0 << 23) /* 0 selects MII */ +# define SYSCFG_PMC_RMII_SEL (1 << 23) /* 1 selects RMII */ + +/* SYSCFG external interrupt configuration register 1-4 */ + +#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */ +#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */ +#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */ +#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */ +#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */ +#define SYSCFG_EXTICR_PORTJ (9) /* 1001: PJ[x] pin */ +#define SYSCFG_EXTICR_PORTK (10) /* 1010: PK[x] pin */ + +#define SYSCFG_EXTICR_PORT_MASK (15) +#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) +#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) + +#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) +#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) +#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) +#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) + +#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) +#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) +#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) +#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) + +#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) +#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) +#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) +#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) + +#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) +#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) +#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) +#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) + +/* Class B register */ + +#define SYSCFG_CBR_PVD (1 << 0) /* Bit 0: PVDL: PVD Lock */ +#define SYSCFG_CBR_CLL (1 << 2) /* Bit 2: CLL Core Lockup Lock*/ + +/* Compensation cell control register */ + +#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ +#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ + +#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index ff904c1d6b..eab3412fbe 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -59,7 +59,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index e1772e89cd..24429b01e2 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -57,7 +57,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index 7c15027563..ec4cd1a7d7 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -65,7 +65,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index ee4e0f819b..0cd386725f 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -57,7 +57,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Public Data diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index bd1d1e7bca..21cac17ad7 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/stm32_rcc.c * * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -75,6 +76,8 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "stm32f74xx75xx_rcc.c" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "stm32f76xx77xx_rcc.c" #else # error "Unsupported STM32 F7 chip" #endif diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c new file mode 100644 index 0000000000..74d58b52ad --- /dev/null +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -0,0 +1,886 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32f76xxx77xx_rcc.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_pwr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/* Same for HSI */ + +#define HSIRDY_TIMEOUT HSERDY_TIMEOUT + +/* HSE divisor to yield ~1MHz RTC clock */ + +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 + +/* FLASH wait states */ + +#if !defined(BOARD_FLASH_WAITSTATES) +# error BOARD_FLASH_WAITSTATES not defined +#elif BOARD_FLASH_WAITSTATES < 0 || BOARD_FLASH_WAITSTATES > 15 +# error BOARD_FLASH_WAITSTATES is out of range +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Reset the RCC clock configuration to the default reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + /* Enable the Internal High Speed clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + /* Reset CFGR register */ + + putreg32(0x00000000, STM32_RCC_CFGR); + + /* Reset HSION, HSEON, CSSON and PLLON bits */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + putreg32(regval, STM32_RCC_CR); + + /* Reset PLLCFGR register to reset default */ + + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); + + /* Reset HSEBYP bit */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + /* Disable all interrupts */ + + putreg32(0x00000000, STM32_RCC_CIR); +} + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB1ENR register to enabled the + * selected AHB1 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB1ENR); + + /* Enable GPIOA, GPIOB, .... GPIOI */ + +#if STM32F7_NGPIO > 0 + regval |= (RCC_AHB1ENR_GPIOAEN +#if STM32F7_NGPIO > 1 + | RCC_AHB1ENR_GPIOBEN +#endif +#if STM32F7_NGPIO > 2 + | RCC_AHB1ENR_GPIOCEN +#endif +#if STM32F7_NGPIO > 3 + | RCC_AHB1ENR_GPIODEN +#endif +#if STM32F7_NGPIO > 4 + | RCC_AHB1ENR_GPIOEEN +#endif +#if STM32F7_NGPIO > 5 + | RCC_AHB1ENR_GPIOFEN +#endif +#if STM32F7_NGPIO > 6 + | RCC_AHB1ENR_GPIOGEN +#endif +#if STM32F7_NGPIO > 7 + | RCC_AHB1ENR_GPIOHEN +#endif +#if STM32F7_NGPIO > 8 + | RCC_AHB1ENR_GPIOIEN +#endif +#if STM32F7_NGPIO > 9 + | RCC_AHB1ENR_GPIOJEN +#endif +#if STM32F7_NGPIO > 10 + | RCC_AHB1ENR_GPIOKEN +#endif + ); +#endif + +#ifdef CONFIG_STM32F7_CRC + /* CRC clock enable */ + + regval |= RCC_AHB1ENR_CRCEN; +#endif + +#ifdef CONFIG_STM32F7_BKPSRAM + /* Backup SRAM clock enable */ + + regval |= RCC_AHB1ENR_BKPSRAMEN; +#endif + +#ifdef CONFIG_ARMV7M_DTCM + /* DTCM data RAM clock enable */ + + regval |= RCC_AHB1ENR_DTCMRAMEN; +#endif + +#ifdef CONFIG_STM32F7_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHB1ENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32F7_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHB1ENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32F7_DMA2D + /* DMA2D clock */ + + regval |= RCC_AHB1ENR_DMA2DEN; +#endif + +#ifdef CONFIG_STM32F7_ETHMAC + /* Ethernet MAC clocking */ + + regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN); + +#ifdef CONFIG_STM32F7_ETH_PTP + /* Precision Time Protocol (PTP) */ + + regval |= RCC_AHB1ENR_ETHMACPTPEN; + +#endif +#endif + +#ifdef CONFIG_STM32F7_OTGHS + /* USB OTG HS */ + + regval |= RCC_AHB1ENR_OTGHSEN; +#endif /* CONFIG_STM32F7_OTGHS */ + + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB2ENR register to enabled the + * selected AHB2 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB2ENR); + +#ifdef CONFIG_STM32F7_DCMI + /* Camera interface enable */ + + regval |= RCC_AHB2ENR_DCMIEN; +#endif + +#ifdef CONFIG_STM32F7_CRYP + /* Cryptographic modules clock enable */ + + regval |= RCC_AHB2ENR_CRYPEN; +#endif + +#ifdef CONFIG_STM32F7_HASH + /* Hash modules clock enable */ + + regval |= RCC_AHB2ENR_HASHEN; +#endif + +#ifdef CONFIG_STM32F7_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + +#ifdef CONFIG_STM32F7_OTGFS + /* USB OTG FS clock enable */ + + regval |= RCC_AHB2ENR_OTGFSEN; +#endif + + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb3 + * + * Description: + * Enable selected AHB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB3ENR register to enabled the + * selected AHB3 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB3ENR); + +#ifdef CONFIG_STM32F7_FSMC + /* Flexible static memory controller module clock enable */ + + regval |= RCC_AHB3ENR_FSMCEN; +#endif + +#ifdef CONFIG_STM32F7_QUADSPI + /* FQuad SPI memory controller clock enable */ + + regval |= RCC_AHB3ENR_QSPIEN; +#endif + + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32F7_TIM2 + /* TIM2 clock enable */ + + regval |= RCC_APB1ENR_TIM2EN; +#endif + +#ifdef CONFIG_STM32F7_TIM3 + /* TIM3 clock enable */ + + regval |= RCC_APB1ENR_TIM3EN; +#endif + +#ifdef CONFIG_STM32F7_TIM4 + /* TIM4 clock enable */ + + regval |= RCC_APB1ENR_TIM4EN; +#endif + +#ifdef CONFIG_STM32F7_TIM5 + /* TIM5 clock enable */ + + regval |= RCC_APB1ENR_TIM5EN; +#endif + +#ifdef CONFIG_STM32F7_TIM6 + /* TIM6 clock enable */ + + regval |= RCC_APB1ENR_TIM6EN; +#endif + +#ifdef CONFIG_STM32F7_TIM7 + /* TIM7 clock enable */ + + regval |= RCC_APB1ENR_TIM7EN; +#endif + +#ifdef CONFIG_STM32F7_TIM12 + /* TIM12 clock enable */ + + regval |= RCC_APB1ENR_TIM12EN; +#endif + +#ifdef CONFIG_STM32F7_TIM13 + /* TIM13 clock enable */ + + regval |= RCC_APB1ENR_TIM13EN; +#endif + +#ifdef CONFIG_STM32F7_TIM14 + /* TIM14 clock enable */ + + regval |= RCC_APB1ENR_TIM14EN; +#endif + +#ifdef CONFIG_STM32F7_LPTIM1 + /* Low-power timer 1 clock enable */ + + regval |= RCC_APB1ENR_LPTIM1EN; +#endif + +#ifdef CONFIG_STM32F7_WWDG + /* Window watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32F7_SPI2 + /* SPI2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32F7_SPI3 + /* SPI3 clock enable */ + + regval |= RCC_APB1ENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32F7_SPDIFRX + /* SPDIFRX clock enable */ + + regval |= RCC_APB1ENR_SPDIFRXEN; +#endif + +#ifdef CONFIG_STM32F7_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#ifdef CONFIG_STM32F7_USART3 + /* USART3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#ifdef CONFIG_STM32F7_UART4 + /* UART4 clock enable */ + + regval |= RCC_APB1ENR_UART4EN; +#endif + +#ifdef CONFIG_STM32F7_UART5 + /* UART5 clock enable */ + + regval |= RCC_APB1ENR_UART5EN; +#endif + +#ifdef CONFIG_STM32F7_I2C1 + /* I2C1 clock enable */ + + regval |= RCC_APB1ENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32F7_I2C2 + /* I2C2 clock enable */ + + regval |= RCC_APB1ENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32F7_I2C3 + /* I2C3 clock enable */ + + regval |= RCC_APB1ENR_I2C3EN; +#endif + +#ifdef CONFIG_STM32F7_I2C4 + /* I2C4 clock enable */ + + regval |= RCC_APB1ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32F7_CAN1 + /* CAN 1 clock enable */ + + regval |= RCC_APB1ENR_CAN1EN; +#endif + +#ifdef CONFIG_STM32F7_CAN2 + /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ + + regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); +#endif + +#ifdef CONFIG_STM32F7_CEC + /* CEC clock enable. */ + + regval |= RCC_APB1ENR_CECEN; +#endif + + /* Power interface clock enable. The PWR block is always enabled so that + * we can set the internal voltage regulator for maximum performance. + */ + + regval |= RCC_APB1ENR_PWREN; + +#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) + /* DAC interface clock enable */ + + regval |= RCC_APB1ENR_DACEN; +#endif + +#ifdef CONFIG_STM32F7_UART7 + /* UART7 clock enable */ + + regval |= RCC_APB1ENR_UART7EN; +#endif + +#ifdef CONFIG_STM32F7_UART8 + /* UART8 clock enable */ + + regval |= RCC_APB1ENR_UART8EN; +#endif + + putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32F7_TIM1 + /* TIM1 clock enable */ + + regval |= RCC_APB2ENR_TIM1EN; +#endif + +#ifdef CONFIG_STM32F7_TIM8 + /* TIM8 clock enable */ + + regval |= RCC_APB2ENR_TIM8EN; +#endif + +#ifdef CONFIG_STM32F7_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32F7_USART6 + /* USART6 clock enable */ + + regval |= RCC_APB2ENR_USART6EN; +#endif + +#ifdef CONFIG_STM32F7_ADC1 + /* ADC1 clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + +#ifdef CONFIG_STM32F7_ADC2 + /* ADC2 clock enable */ + + regval |= RCC_APB2ENR_ADC2EN; +#endif + +#ifdef CONFIG_STM32F7_ADC3 + /* ADC3 clock enable */ + + regval |= RCC_APB2ENR_ADC3EN; +#endif + +#ifdef CONFIG_STM32F7_SDMMC1 + /* SDIO clock enable */ + + regval |= RCC_APB2ENR_SDMMC1EN; +#endif + +#ifdef CONFIG_STM32F7_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32F7_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + + /* System configuration controller clock enable */ + + regval |= RCC_APB2ENR_SYSCFGEN; + +#ifdef CONFIG_STM32F7_TIM9 + /* TIM9 clock enable */ + + regval |= RCC_APB2ENR_TIM9EN; +#endif + +#ifdef CONFIG_STM32F7_TIM10 + /* TIM10 clock enable */ + + regval |= RCC_APB2ENR_TIM10EN; +#endif + +#ifdef CONFIG_STM32F7_TIM11 + /* TIM11 clock enable */ + + regval |= RCC_APB2ENR_TIM11EN; +#endif + +#ifdef CONFIG_STM32F7_SPI5 + /* SPI5 clock enable */ + + regval |= RCC_APB2ENR_SPI5EN; +#endif + +#ifdef CONFIG_STM32F7_SPI6 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SPI6EN; +#endif + +#ifdef CONFIG_STM32F7_SAI1 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SAI1EN; +#endif + +#ifdef CONFIG_STM32F7_SAI2 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SAI2EN; +#endif + +#ifdef CONFIG_STM32F7_LTDC + /* LTDC clock enable */ + + regval |= RCC_APB2ENR_LTDCEN; +#endif + + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + +#ifdef STM32_BOARD_USEHSI + /* Enable Internal High-Speed Clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; /* Enable HSI */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSI is ready (or until a timeout elapsed) */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#else /* if STM32_BOARD_USEHSE */ + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#endif + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Select regulator voltage output Scale 1 mode to support system + * frequencies up to 216 MHz. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + regval |= RCC_APB1ENR_PWREN; + putreg32(regval, STM32_RCC_APB1ENR); + + regval = getreg32(STM32_PWR_CR1); + regval &= ~PWR_CR1_VOS_MASK; + regval |= PWR_CR1_VOS_SCALE_1; + putreg32(regval, STM32_PWR_CR1); + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE2_MASK; + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + +#ifdef CONFIG_RTC_HSECLOCK + /* Set the RTC clock divisor */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_RTCPRE_MASK; + regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); + putreg32(regval, STM32_RCC_CFGR); +#endif + + /* Set the PLL dividers and multipliers to configure the main PLL */ + +#ifdef STM32_BOARD_USEHSI + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | + RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ); +#else /* if STM32_BOARD_USEHSE */ + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | + RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ); +#endif + putreg32(regval, STM32_RCC_PLLCFG); + + /* Enable the main PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) + { + } + + /* Enable the Over-drive to extend the clock frequency to 216 Mhz */ + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) + { + } + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODSWEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + { + } + + /* Configure FLASH wait states */ + + regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); + +#ifdef CONFIG_STM32F7_FLASH_PREFETCH + /* Enable FLASH prefetch */ + + regval |= FLASH_ACR_PRFTEN; +#endif + +#ifdef CONFIG_ARMV7M_ITCM + /* The Flash memory interface accelerates code execution with a system of + * instruction prefetch and cache lines on ITCM interface (ART + * Accelerator™). + */ + + regval |= FLASH_ACR_ARTEN; +#endif + + putreg32(regval, STM32_FLASH_ACR); + + /* Select the main PLL as system clock source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_PLL; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the PLL source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + { + } + +#ifdef CONFIG_STM32F7_LTDC + /* Configure PLLSAI */ + + regval = getreg32(STM32_RCC_PLLSAICFGR); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIR + | STM32_RCC_PLLSAICFGR_PLLSAIQ); + putreg32(regval, STM32_RCC_PLLSAICFGR); + + regval = getreg32(STM32_RCC_DCKCFGR); + regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; + putreg32(regval, STM32_RCC_DCKCFGR); + + /* Enable PLLSAI */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLSAION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLSAI is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0) + { + } +#endif + +#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) + /* Low speed internal clock source LSI */ + + stm32_rcc_enablelsi(); +#endif + +#if defined(CONFIG_RTC_LSECLOCK) + /* Low speed external clock source LSE + * + * TODO: There is another case where the LSE needs to + * be enabled: if the MCO1 pin selects LSE as source. + */ + + stm32_rcc_enablelse(); +#endif + } +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb3(); + rcc_enableapb1(); + rcc_enableapb2(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ From 4a4f407175249e55510af227b0d6b1c56f7f2392 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 8 Jun 2016 08:29:30 -0600 Subject: [PATCH 15/18] STM32F7: Fix a redefinition warning the DMA header file --- arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h index 82ab312cb3..d4d4eb0f89 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h @@ -489,8 +489,8 @@ #define DMAMAP_I2C2_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN8) #define DMAMAP_I2C4_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN8) -#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN9) -#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN9) +#define DMAMAP_SPI2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN9) +#define DMAMAP_SPI2_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN9) #define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) #define DMAMAP_SAI1_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN0) @@ -586,7 +586,7 @@ #define DMAMAP_SAI1_A_3 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN10) #define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) -#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) +#define DMAMAP_QUADSPI_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ From 79a157cc9d42f56cdd1c1670fdb67f4e1c028d3c Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Wed, 8 Jun 2016 11:07:24 -0400 Subject: [PATCH 16/18] assert: Check if NDEBUG is defined --- include/assert.h | 65 ++++++++++++++---------------------------------- 1 file changed, 18 insertions(+), 47 deletions(-) diff --git a/include/assert.h b/include/assert.h index bb6948ab53..2302a7b8eb 100644 --- a/include/assert.h +++ b/include/assert.h @@ -51,9 +51,10 @@ #undef ASSERT /* Assert if the condition is not true */ #undef VERIFY /* Assert if a function returns a negative value */ +#undef PANIC /* Unconditional abort */ #undef DEBUGASSERT /* Like ASSERT, but only if CONFIG_DEBUG is defined */ #undef DEBUGVERIFY /* Like VERIFY, but only if CONFIG_DEBUG is defined */ -#undef PANIC /* Unconditional abort */ +#undef DEBUGPANIC /* Like PANIC, but only if CONFIG_DEBUG is defined */ #ifdef CONFIG_HAVE_FILENAME @@ -80,62 +81,32 @@ # define PANIC() \ up_assert((const uint8_t *)__FILE__, (int)__LINE__) -# ifdef CONFIG_DEBUG +#else -# define DEBUGASSERT(f) \ - do \ - { \ - if (!(f)) \ - { \ - up_assert((const uint8_t *)__FILE__, (int)__LINE__); \ - } \ - } \ - while (0) +# define ASSERT(f) do { if (!(f)) up_assert(); } while (0) +# define VERIFY(f) do { if ((f) < 0) up_assert(); } while (0) +# define PANIC() up_assert() -# define DEBUGVERIFY(f) \ - do \ - { \ - if ((f) < 0) \ - { \ - up_assert((const uint8_t *)__FILE__, (int)__LINE__); \ - } \ - } \ - while (0) +#endif -# define DEBUGPANIC() \ - up_assert((const uint8_t *)__FILE__, (int)__LINE__) +#ifdef CONFIG_DEBUG -# else - -# define DEBUGASSERT(f) -# define DEBUGVERIFY(f) ((void)(f)) -# define DEBUGPANIC() - -# endif /* CONFIG_DEBUG */ +# define DEBUGASSERT(f) ASSERT(f) +# define DEBUGVERIFY(f) VERIFY(f) +# define DEBUGPANIC() PANIC() #else -# define ASSERT(f) { if (!(f)) up_assert(); } -# define VERIFY(f) { if ((f) < 0) up_assert(); } -# define PANIC() up_assert() - -# ifdef CONFIG_DEBUG - -# define DEBUGASSERT(f) { if (!(f)) up_assert(); } -# define DEBUGVERIFY(f) { if ((f) < 0) up_assert(); } -# define DEBUGPANIC() up_assert() - -# else - -# define DEBUGASSERT(f) -# define DEBUGVERIFY(f) ((void)(f)) -# define DEBUGPANIC() +# define DEBUGASSERT(f) +# define DEBUGVERIFY(f) ((void)(f)) +# define DEBUGPANIC() # endif /* CONFIG_DEBUG */ -#endif -#ifndef assert -# define assert ASSERT +#ifdef NDEBUG +# define assert(f) +#else +# define assert(f) ASSERT(f) #endif /**************************************************************************** From 982982d62b813a2ebeff4295fe7d9267d22d8035 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 8 Jun 2016 09:43:54 -0600 Subject: [PATCH 17/18] Eliminate some warnings --- arch/arm/src/kinetis/kinetis_usbdev.c | 16 ++++++++++++---- configs/teensy-3.x/src/k20_appinit.c | 1 + configs/teensy-3.x/src/k20_usbdev.c | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 287f0f3abd..6bb47d5e3b 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -1930,7 +1930,7 @@ static void khci_ep0rdcomplete(struct khci_usbdev_s *priv) if (!priv->ep0done) { bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); - physaddr = &priv->ctrl; + physaddr = (uint32_t)&priv->ctrl; bdt = &g_bdt[EP0_OUT_EVEN]; bdt->addr = (uint8_t *)physaddr; @@ -2999,7 +2999,9 @@ interrupt_exit: static void khci_suspend(struct khci_usbdev_s *priv) { +#if 0 uint32_t regval; +#endif /* Notify the class driver of the suspend event */ @@ -3008,6 +3010,7 @@ static void khci_suspend(struct khci_usbdev_s *priv) CLASS_SUSPEND(priv->driver, &priv->usbdev); } +#if 0 /* Enable the ACTV interrupt. * * NOTE: Do not clear UIRbits.ACTVIF here! Reason: ACTVIF is only @@ -3018,7 +3021,7 @@ static void khci_suspend(struct khci_usbdev_s *priv) * first because ACTIVIE=0. If this routine clears the only ACTIVIF, * then it can never get out of the suspend mode. */ -#if 0 + regval = khci_getreg(KINETIS_USB0_OTGICR); regval |= USBOTG_INT_ACTV; khci_putreg(regval, KINETIS_USB0_OTGICR); @@ -3651,7 +3654,7 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) if (epno == 0 && !epin) { uint32_t bytecount = (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); - uint32_t physaddr = &priv->ctrl; + uint32_t physaddr = (uint32_t)&priv->ctrl; /* Configure the other BDT to receive a SETUP command. */ @@ -4094,7 +4097,10 @@ static void khci_attach(struct khci_usbdev_s *priv) static void khci_detach(struct khci_usbdev_s *priv) { +#ifdef CONFIG_USBOTG uint32_t regval; +#endif + /* Disable USB interrupts at the interrupt controller */ up_disable_irq(KINETIS_IRQ_USBOTG); @@ -4205,7 +4211,6 @@ static void khci_swreset(struct khci_usbdev_s *priv) static void khci_hwreset(struct khci_usbdev_s *priv) { - uint32_t physaddr; uint32_t regval; #define USB_FLASH_ACCESS @@ -4342,7 +4347,9 @@ static void khci_stateinit(struct khci_usbdev_s *priv) static void khci_hwshutdown(struct khci_usbdev_s *priv) { +#if 0 uint32_t regval; +#endif /* Put the hardware and driver in its initial, unconnected state */ @@ -4366,6 +4373,7 @@ static void khci_hwshutdown(struct khci_usbdev_s *priv) /* Power down the USB controller */ #warning FIXME powerdown USB Controller + #if 0 regval = khci_getreg(KHCI_USB_PWRC); regval &= ~USB_PWRC_USBPWR; diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c index c4d9e3fd44..f027eb7167 100644 --- a/configs/teensy-3.x/src/k20_appinit.c +++ b/configs/teensy-3.x/src/k20_appinit.c @@ -41,6 +41,7 @@ #include #include +#include "kinetis_usbotg.h" #include "teensy-3x.h" /**************************************************************************** diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c index d8b801193a..ca0ed25800 100644 --- a/configs/teensy-3.x/src/k20_usbdev.c +++ b/configs/teensy-3.x/src/k20_usbdev.c @@ -92,7 +92,9 @@ void kinetis_usbinitialize(void) int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable) { usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); +#if 0 uint32_t regval; +#endif if (enable) { From d84dbbc45590e024143f7d081b665e590f18d14d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 8 Jun 2016 09:59:11 -0600 Subject: [PATCH 18/18] Add a comment to assert.h --- include/assert.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/assert.h b/include/assert.h index 2302a7b8eb..c636dae9a9 100644 --- a/include/assert.h +++ b/include/assert.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/assert.h * - * Copyright (C) 2007-2009, 2011-2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -103,6 +103,11 @@ # endif /* CONFIG_DEBUG */ +/* The C standard states that if NDEBUG is defined, assert will do nothing. + * Users can define and undefine NDEBUG as they see fit to choose when assert + * does something or does not do anything. + */ + #ifdef NDEBUG # define assert(f) #else