Xtensa/ESP32: Add up_cpu_idlestack() and fix some compile issues.
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28d1478480
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4d0b0e44f1
@ -276,6 +276,7 @@ void xtensa_user(int exccause, uint32_t *regs) noreturn_function;
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/* Software interrupt handler */
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#ifdef CONFIG_SMP
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void __cpu1_start(void) noreturn_function;
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int xtensa_intercpu_interrupt(int tocpu, int intcode);
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void xtensa_pause_handler(void);
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#endif
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@ -164,7 +164,6 @@ void up_assert(const uint8_t *filename, int lineno)
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filename, lineno);
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#endif
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CURRENT_REGS = regs;
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xtensa_assert(EXIT_FAILURE);
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}
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@ -125,7 +125,7 @@
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* a consequence of context switching.
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*/
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mov s12, sp /* a12 = address of save area */
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mov a12, sp /* a12 = address of save area */
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._xtensa_dispatch_level&level&:
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@ -274,7 +274,7 @@ _xtensa_syscall_handler:
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/* Save EPC */
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#ifidef XCHAL_HAVE_LOOPS
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#ifdef XCHAL_HAVE_LOOPS
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/* Save A2 and A3 now to give us some registers to work with. A0, A2
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* and A3 are now available. NOTE that A3 will get saved again in
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* _xtensa_context_save().
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@ -215,6 +215,8 @@ _xtensa_nmi_vector:
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.size _xtensa_nmi_vector, . - _xtensa_nmi_vector
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.end literal_prefix
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#endif /* XCHAL_HAVE_NMI */
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/****************************************************************************
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* Name: _debug_exception_vector
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*
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@ -41,7 +41,7 @@ HEAD_CSRC = esp32_start.c
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# Common XTENSA files (arch/xtensa/src/common)
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CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S
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CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handlers.S
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CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handler.S
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CMN_ASRCS += xtensa_vectors.S
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CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
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@ -81,7 +81,7 @@ endif
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# Required ESP32 files (arch/xtensa/src/lx6)
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CHIP_ASRCS = esp32_cpuhead.S
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CHIP_ASRCS =
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CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c
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CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c
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CHIP_CSRCS += esp32_start.c esp32_timerisr.c
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@ -89,9 +89,8 @@ CHIP_CSRCS += esp32_start.c esp32_timerisr.c
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# Configuration-dependent ESP32 files
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ifeq ($(CONFIG_SMP),y)
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CHIP_ASRCS = esp32_cpuindex.S
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CMN_CSRCS += esp32_cpustart.c esp32_intercpu_interrupt.c
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#CMN_CSRCS += esp32_cpuidlestack.c
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CHIP_ASRCS = esp32_cpuhead.S esp32_cpuindex.S
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CMN_CSRCS += esp32_cpuidlestack.c esp32_cpustart.c esp32_intercpu_interrupt.c
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endif
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ifeq ($(CONFIG_ESP32_UART),y)
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/exp32_cpuindex.S
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* arch/xtensa/src/esp32/esp32_clockconfig.C
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*
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* Mofidifed by use in NuttX by:
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*
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@ -40,15 +40,19 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/xtensa/xtensa_corebits.h>
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#include <arch/esp32/core-isa.h>
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Private Data
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****************************************************************************/
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section .noinit, "aw"
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.align 16
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.section .noinit, "aw"
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.global g_cpu1_idlestack
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.type g_cpu1_idlestack, @object
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.align 16
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g_cpu1_idlestack:
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.space (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15)
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@ -79,30 +83,36 @@ g_cpu1_idlestack:
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*
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****************************************************************************/
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#if CONFIG_SMP_NCPUS > 1
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.global __cpu1_start
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.type __cpu1_start, #function
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.type __cpu1_start, @function
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.align 4
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.Lcpu1_bottomofstack:
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long .Lcpu1_stacktop
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.long .Lcpu1_stacktop
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.size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack
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#ifdef CONFIG_STACK_COLORATION
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.Lcpu1_bottomofstack:
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long .Lcpu1_stacktop
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.long .Lcpu1_stacktop
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.size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack
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.Lcpu1_stackcolor:
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long STACK_COLOR
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.long STACK_COLOR
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.size .Lcpu1_stackcolor, . - .Lcpu1_stackcolor
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#endif
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.align 4
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__cpu1_start:
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/* Set up the stack pointer and the CPU index */
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l32r .Lcpu1_bottomofstack
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l32r sp, .Lcpu1_bottomofstack
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/* Does it make since to have co-processors enabled on the IDLE thread? */
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//#warning REVISIT: Must set aside co-processor save ares
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#ifdef CONFIG_STACK_COLORATION
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/* Write a known value to the IDLE thread stack to support stack
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@ -122,9 +132,9 @@ __cpu1_start:
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/* Set up the intiali PS */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM;
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movi a0, (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM)
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#else
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
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movi a0, (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1))
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#endif
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wsr a0, PS
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@ -135,5 +145,6 @@ __cpu1_start:
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/* xtensa_start_handler() does not return */
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2: b 2b
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2: j 2b
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.size __cpu1_start, . - __cpu1_start
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#endif /* CONFIG_SMP */
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114
arch/xtensa/src/esp32/esp32_cpuidlestack.c
Normal file
114
arch/xtensa/src/esp32/esp32_cpuidlestack.c
Normal file
@ -0,0 +1,114 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_cpuidlestack.c
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*
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* Mofidifed by use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from software originally provided by Expressif Systems:
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*
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* Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include "xtensa.h"
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#include "esp32_smp.h"
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_cpu_idlestack
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*
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* Description:
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* Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
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* setup up stack-related information in the IDLE task's TCB. This
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* function is always called before up_cpu_start(). This function is
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* only called for the CPU's initial IDLE task; up_create_task is used for
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* all normal tasks, pthreads, and kernel threads for all CPUs.
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*
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* The initial IDLE task is a special case because the CPUs can be started
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* in different wans in different environments:
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*
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* 1. The CPU may already have been started and waiting in a low power
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* state for up_cpu_start(). In this case, the IDLE thread's stack
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* has already been allocated and is already in use. Here
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* up_cpu_idlestack() only has to provide information about the
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* already allocated stack.
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*
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* 2. The CPU may be disabled but started when up_cpu_start() is called.
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* In this case, a new stack will need to be created for the IDLE
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* thread and this function is then equivalent to:
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*
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* return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
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*
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* The following TCB fields must be initialized by this function:
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*
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* - adj_stack_size: Stack size after adjustment for hardware, processor,
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* etc. This value is retained only for debug purposes.
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* - stack_alloc_ptr: Pointer to allocated stack
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* - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
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* the stack pointer.
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*
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* Inputs:
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* - cpu: CPU index that indicates which CPU the IDLE task is
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* being created for.
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* - tcb: The TCB of new CPU IDLE task
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* - stack_size: The requested stack size for the IDLE task. At least
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* this much must be allocated. This should be
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* CONFIG_SMP_IDLETHREAD_STACKSIZE.
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*
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****************************************************************************/
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int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
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{
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uintptr_t topofstack;
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/* XTENSA uses a push-down stack: the stack grows toward lower* addresses
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* in memory. The stack pointer register points to the lowest, valid
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* working address (the "top" of the stack). Items on the stack are
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* referenced as positive word offsets from sp.
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*/
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/* Save information about pre-allocated IDLE thread stack */
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tcb->stack_alloc_ptr = g_cpu1_idlestack;
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tcb->adj_stack_size = CPU1_IDLETHREAD_STACKSIZE;
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topofstack = (uintptr_t)g_cpu1_idlestack + CPU1_IDLETHREAD_STACKSIZE;
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tcb->adj_stack_ptr = (uint32_t *)topofstack;
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#if XCHAL_CP_NUM > 0
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/* Does it make since to have co-processors enabled on the IDLE thread? */
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//#warning REVISIT: Need to set co-processor save are in TCB
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#endif
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return OK;
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}
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#endif /* CONFIG_SMP */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/exp32_cpuindex.S
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* arch/xtensa/src/esp32/esp32_cpuindex.S
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -52,7 +52,7 @@
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#include "chip/esp32_dport.h"
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#include "esp32_region.h"
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#include "esp32_cpuint.h"
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#include "esp32_intercpu_interrupt.h"
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#include "esp32_smp.h"
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#ifdef CONFIG_SMP
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@ -193,6 +193,14 @@ int xtensa_start_handler(int irq, FAR void *context)
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esp32_detach_peripheral(1, i);;
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}
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#if 0 /* Does it make since to have co-processors enabled on the IDLE thread? */
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#if XTENSA_CP_ALLSET != 0
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/* Set initial co-processor state */
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xtensa_coproc_enable(struct xtensa_cpstate_s *cpstate, int cpset);
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#endif
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#endif
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/* Dump registers so that we can see what is going to happen on return */
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xtensa_registerdump(tcb);
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#include <sys/types.h>
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#include <stdint.h>
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#include <sched.h>
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#include <assert.h>
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#include <errno.h>
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#include <nuttx/spinlock.h>
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#include <arch/irq.h>
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#include "chip/esp32_dport.h"
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#include "xtensa.h"
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#ifdef CONFIG_SMP
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#include "xtensa.h"
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#include "esp32_cpuint.h"
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#include "esp32_intercpu_interrupt.h"
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#include "esp32_smp.h"
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/****************************************************************************
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* Public Data
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_intercpu_interrupt.h
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* arch/xtensa/src/esp32/esp32_smp.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>>
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@ -33,8 +33,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H
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#define __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H
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#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H
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#define __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H
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/****************************************************************************
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* Included Files
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@ -44,8 +44,18 @@
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Pre-processor Definitions
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* Public Data
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****************************************************************************/
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/* This is the CPU1 IDLE stack */
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#define CPU1_IDLETHREAD_STACKSIZE (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15)
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extern uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKSIZE / 34];
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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@ -60,4 +70,4 @@ int esp32_fromcpu0_interrupt(int irq, FAR void *context);
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int esp32_fromcpu1_interrupt(int irq, FAR void *context);
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#endif /* CONFIG_SMP */
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#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H */
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#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H */
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