SAM4E: Update SAM3/4 ACC, DACC, and PDC register definition header files
This commit is contained in:
Gregory Nutt
parent
1c596b06d8
commit
4d600b7a73
@ -507,7 +507,7 @@ config SAM34_HMATRIX
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config SAM34_PDCA
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bool "Peripheral DMA controller (PDC)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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select ARCH_DMA
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config SAM34_DMA
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154
arch/arm/src/sam34/chip/sam_acc.h
Normal file
154
arch/arm/src/sam34/chip/sam_acc.h
Normal file
@ -0,0 +1,154 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_rtt.h
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*Analog Comparator Controller (ACC) definitions for the SAM4E
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_ACC_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_ACC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* ACC register offsets *****************************************************************/
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#define SAM_ACC_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_ACC_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_ACC_IER_OFFSET 0x0024 /* Interrupt Enable Register */
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#define SAM_ACC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
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#define SAM_ACC_IMR_OFFSET 0x002c /* Interrupt Mask Register */
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#define SAM_ACC_ISR_OFFSET 0x0030 /* Interrupt Status Register */
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#define SAM_ACC_ACR_OFFSET 0x0094 /* Analog Control Register */
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#define SAM_ACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
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#define SAM_ACC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
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/* ACC register addresses **************************************************************/
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#define SAM_ACC_CR (SAM_ACC_BASE+SAM_ACC_CR_OFFSET)
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#define SAM_ACC_MR (SAM_ACC_BASE+SAM_ACC_MR_OFFSET)
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#define SAM_ACC_IER (SAM_ACC_BASE+SAM_ACC_IER_OFFSET)
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#define SAM_ACC_IDR (SAM_ACC_BASE+SAM_ACC_IDR_OFFSET)
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#define SAM_ACC_IMR (SAM_ACC_BASE+SAM_ACC_IMR_OFFSET)
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#define SAM_ACC_ISR (SAM_ACC_BASE+SAM_ACC_ISR_OFFSET)
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#define SAM_ACC_ACR (SAM_ACC_BASE+SAM_ACC_ACR_OFFSET
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#define SAM_ACC_WPMR (SAM_ACC_BASE+SAM_ACC_WPMR_OFFSET)
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#define SAM_ACC_WPSR (SAM_ACC_BASE+SAM_ACC_WPSR_OFFSET
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/* ACC register bit definitions ********************************************************/
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/* Control Register */
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#define ACC_CR_SWRST (1 << 0) /* Bit 0: Software reset */
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/* Mode Register */
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#define ACC_MR_SELMINUS_SHIFT (0) /* Bits 0-2: Selection for minus comparator input */
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#define ACC_MR_SELMINUS_MASK (7 << ACC_MR_SELMINUS_SHIFT)
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# define ACC_MR_SELMINUS_TS (0 << ACC_MR_SELMINUS_SHIFT) /* Select TS */
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# define ACC_MR_SELMINUS_ADVREF (1 << ACC_MR_SELMINUS_SHIFT) /* Select ADVREF */
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# define ACC_MR_SELMINUS_DAC0 (2 << ACC_MR_SELMINUS_SHIFT) /* Select DAC0 */
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# define ACC_MR_SELMINUS_DAC1 (3 << ACC_MR_SELMINUS_SHIFT) /* Select DAC1 */
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# define ACC_MR_SELMINUS_AD0 (4 << ACC_MR_SELMINUS_SHIFT) /* Select AD0 */
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# define ACC_MR_SELMINUS_AD1 (5 << ACC_MR_SELMINUS_SHIFT) /* Select AD1 */
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# define ACC_MR_SELMINUS_AD2 (6 << ACC_MR_SELMINUS_SHIFT) /* Select AD2 */
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# define ACC_MR_SELMINUS_AD3 (7 << ACC_MR_SELMINUS_SHIFT) /* Select AD3 */
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#define ACC_MR_SELPLUS_SHIFT (4) /* Bits 4-6: Selection for plus comparator input */
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#define ACC_MR_SELPLUS_MASK (7 << ACC_MR_SELPLUS_SHIFT)
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# define ACC_MR_SELPLUS_AD(n) ((uint32_t)(n) << ACC_MR_SELPLUS_SHIFT) /* Select ADn, n=0-7 */
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# define ACC_MR_SELPLUS_AD0 (0 << ACC_MR_SELPLUS_SHIFT) /* Select AD0 */
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# define ACC_MR_SELPLUS_AD1 (1 << ACC_MR_SELPLUS_SHIFT) /* Select AD1 */
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# define ACC_MR_SELPLUS_AD2 (2 << ACC_MR_SELPLUS_SHIFT) /* Select AD2 */
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# define ACC_MR_SELPLUS_AD3 (3 << ACC_MR_SELPLUS_SHIFT) /* Select AD3 */
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# define ACC_MR_SELPLUS_AD4 (4 << ACC_MR_SELPLUS_SHIFT) /* Select AD4 */
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# define ACC_MR_SELPLUS_AD5 (5 << ACC_MR_SELPLUS_SHIFT) /* Select AD5 */
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# define ACC_MR_SELPLUS_AD6 (6 << ACC_MR_SELPLUS_SHIFT) /* Select AD6 */
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# define ACC_MR_SELPLUS_AD7 (7 << ACC_MR_SELPLUS_SHIFT) /* Select AD7 */
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#define ACC_MR_ACEN (1 << 8) /* Bit 8: Analog comparator enable */
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#define ACC_MR_EDGETYP_SHIFT (9) /* Bits 9-10: Edge type */
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#define ACC_MR_EDGETYP_MASK (3 << ACC_MR_EDGETYP_SHIFT)
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# define ACC_MR_EDGETYP_RISING (0 << ACC_MR_EDGETYP_SHIFT) /* Only rising edge of comparator output */
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# define ACC_MR_EDGETYP_FALLING (1 << ACC_MR_EDGETYP_SHIFT) /* Falling edge of comparator output */
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# define ACC_MR_EDGETYP_ANY (2 << ACC_MR_EDGETYP_SHIFT) /* Any edge of comparator output */
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#define ACC_MR_INV (1 << 12) /* Bit 12: Invert comparator output */
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#define ACC_MR_SELFS (1 << 13) /* Bit 13: Selection of fault source */
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#define ACC_MR_FE (1 << 14) /* Bit 14: Fault enable */
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/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status */
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#define ACC_INT_CE (1 << 0) /* Bit 0: Comparison edge interrupt */
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/* Interrupt Status Register (only) */
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#define ACC_ISR_SCO (1 << 1) /* Bit 1: Synchronized Comparator Output */
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#define ACC_ISR_MASK (1 << 31)
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/* Analog Control Register */
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#define ACC_ACR_ISEL (1 << 0) /* Bit 0: Current selection */
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#define ACC_ACR_HYST_SHIFT (1) /* Bits 1-2: Hysteresis selection */
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#define ACC_ACR_HYST_MASK (3 << ACC_ACR_HYST_SHIFT)
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/* Write Protect Mode Register */
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#define ACC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
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#define ACC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
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#define ACC_WPMR_WPKEY_MASK (0x00ffffff << ACC_WPMR_WPKEY_SHIFT)
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# define ACC_WPMR_WPKEY (0x00414343 << ACC_WPMR_WPKEY_SHIFT)
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/* Write Protect Status Register */
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#define ACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_ACC_H */
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232
arch/arm/src/sam34/chip/sam_dacc.h
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232
arch/arm/src/sam34/chip/sam_dacc.h
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@ -0,0 +1,232 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_dacc.h
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* Digital-to-Analog Converter Controller (DACC) for the SAM4E
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_DACC_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_DACC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* DACC register offsets *****************************************************************/
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#define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_DACC_CHER_OFFSET 0x0010 /* Channel Enable Register */
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#define SAM_DACC_CHDR_OFFSET 0x0014 /* Channel Disable Register */
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#define SAM_DACC_CHSR_OFFSET 0x0018 /* Channel Status Register */
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#define SAM_DACC_CDR_OFFSET 0x0020 /* Conversion Data Register */
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#define SAM_DACC_IER_OFFSET 0x0024 /* Interrupt Enable Register */
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#define SAM_DACC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
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#define SAM_DACC_IMR_OFFSET 0x002c /* Interrupt Mask Register */
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#define SAM_DACC_ISR_OFFSET 0x0030 /* Interrupt Status Register */
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#define SAM_DACC_ACR_OFFSET 0x0094 /* Analog Current Register */
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#define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */
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#define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */
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/* DACC register adresses ***************************************************************/
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#define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET)
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#define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET)
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#define SAM_DACC_CHER (SAM_DACC_BASE+SAM_DACC_CHER_OFFSET)
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#define SAM_DACC_CHDR (SAM_DACC_BASE+SAM_DACC_CHDR_OFFSET)
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#define SAM_DACC_CHSR (SAM_DACC_BASE+SAM_DACC_CHSR_OFFSET)
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#define SAM_DACC_CDR (SAM_DACC_BASE+SAM_DACC_CDR_OFFSET)
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#define SAM_DACC_IER (SAM_DACC_BASE+SAM_DACC_IER_OFFSET)
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#define SAM_DACC_IDR (SAM_DACC_BASE+SAM_DACC_IDR_OFFSET)
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#define SAM_DACC_IMR (SAM_DACC_BASE+SAM_DACC_IMR_OFFSET)
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#define SAM_DACC_ISR (SAM_DACC_BASE+SAM_DACC_ISR_OFFSET)
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#define SAM_DACC_ACR (SAM_DACC_BASE+SAM_DACC_ACR_OFFSET)
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#define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET)
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#define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET)
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/* DACC register bit definitions ********************************************************/
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/* Control Register */
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#define DACC_CR_SWRST (1 << 0) /* Bit 0: Software reset */
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/* Mode Register */
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#define DACC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
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#define DACC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
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#define DACC_MR_TRGSEL_MASK (7 << DACC_MR_TRGSEL_SHIFT)
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# define DACC_MR_TRGSEL_EXTERN (0 << DACC_MR_TRGSEL_SHIFT) /* External trigger */
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# define DACC_MR_TRGSEL_TIO0 (1 << DACC_MR_TRGSEL_SHIFT) /* TIO Output of the TC Channel 0 */
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# define DACC_MR_TRGSEL_TIO1 (2 << DACC_MR_TRGSEL_SHIFT) /* TIO Output of the TC Channel 1 */
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# define DACC_MR_TRGSEL_TIO2 (3 << DACC_MR_TRGSEL_SHIFT) /* TIO Output of the TC Channel 2 */
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# define DACC_MR_TRGSEL_PWM0 (4 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */
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# define DACC_MR_TRGSEL_PWM1 (5 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */
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#define DACC_MR_WORD (1 << 4) /* Bit 4: Word Transfer */
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#define DACC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
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#define DACC_MR_FASTWKUP (1 << 6) /* Bit 6: Fast Wake up Mode */
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#define DACC_MR_REFRESH_SHIFT (8) /* Bits 8-15: Refresh Period */
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#define DACC_MR_REFRESH_MASK (0xff << DACC_MR_REFRESH_SHIFT)
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#define DACC_MR_USERSEL_SHIFT (16) /* Bits 16-17: User Channel Selection */
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#define DACC_MR_USERSEL_MASK (3 << DACC_MR_USERSEL_SHIFT)
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# define DACC_MR_USERSEL_CHAN0 (0 << DACC_MR_USERSEL_SHIFT) /* Channel 0 */
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# define DACC_MR_USERSEL_CHAN1 (1 << DACC_MR_USERSEL_SHIFT) /* Channel 1 */
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#define DACC_MR_TAG (1 << 20) /* Bit 20: Tag Selection Mode */
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#define DACC_MR_MAXS (1 << 21) /* Bit 21: Max Speed Mode */
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#define DACC_MR_CLKDIV (1 << 22) /* Bit 22: Clock Divider */
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# define DACC_MR_CLKDIV_2 (0) /* DAC clock is MCK divided by 2 */
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# define DACC_MR_CLKDIV_4 DACC_MR_CLKDIV /* DAC clock is MCK divided by 4 */
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#define DACC_MR_STARTUP_SHIFT (24) /* Bits 24-29: Startup Time Select */
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#define DACC_MR_STARTUP_MASK (63 << DACC_MR_STARTUP_SHIFT)
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# define DACC_MR_STARTUP_0 (0 << DACC_MR_STARTUP_SHIFT) /* 0 periods of DACClock */
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# define DACC_MR_STARTUP_8 (1 << DACC_MR_STARTUP_SHIFT) /* 8 periods of DACClock */
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# define DACC_MR_STARTUP_16 (2 << DACC_MR_STARTUP_SHIFT) /* 16 periods of DACClock */
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# define DACC_MR_STARTUP_24 (3 << DACC_MR_STARTUP_SHIFT) /* 24 periods of DACClock */
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# define DACC_MR_STARTUP_64 (4 << DACC_MR_STARTUP_SHIFT) /* 64 periods of DACClock */
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# define DACC_MR_STARTUP_80 (5 << DACC_MR_STARTUP_SHIFT) /* 80 periods of DACClock */
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# define DACC_MR_STARTUP_96 (6 << DACC_MR_STARTUP_SHIFT) /* 96 periods of DACClock */
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# define DACC_MR_STARTUP_112 (7 << DACC_MR_STARTUP_SHIFT) /* 112 periods of DACClock */
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# define DACC_MR_STARTUP_512 (8 << DACC_MR_STARTUP_SHIFT) /* 512 periods of DACClock */
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# define DACC_MR_STARTUP_576 (9 << DACC_MR_STARTUP_SHIFT) /* 576 periods of DACClock */
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# define DACC_MR_STARTUP_640 (10 << DACC_MR_STARTUP_SHIFT) /* 640 periods of DACClock */
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# define DACC_MR_STARTUP_704 (11 << DACC_MR_STARTUP_SHIFT) /* 704 periods of DACClock */
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# define DACC_MR_STARTUP_768 (12 << DACC_MR_STARTUP_SHIFT) /* 768 periods of DACClock */
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# define DACC_MR_STARTUP_832 (13 << DACC_MR_STARTUP_SHIFT) /* 832 periods of DACClock */
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# define DACC_MR_STARTUP_896 (14 << DACC_MR_STARTUP_SHIFT) /* 896 periods of DACClock */
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# define DACC_MR_STARTUP_960 (51 << DACC_MR_STARTUP_SHIFT) /* 960 periods of DACClock */
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# define DACC_MR_STARTUP_1024 (16 << DACC_MR_STARTUP_SHIFT) /* 1024 periods of DACClock */
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# define DACC_MR_STARTUP_1088 (17 << DACC_MR_STARTUP_SHIFT) /* 1088 periods of DACClock */
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# define DACC_MR_STARTUP_1152 (18 << DACC_MR_STARTUP_SHIFT) /* 1152 periods of DACClock */
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# define DACC_MR_STARTUP_1216 (19 << DACC_MR_STARTUP_SHIFT) /* 1216 periods of DACClock */
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# define DACC_MR_STARTUP_1280 (20 << DACC_MR_STARTUP_SHIFT) /* 1280 periods of DACClock */
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# define DACC_MR_STARTUP_1344 (21 << DACC_MR_STARTUP_SHIFT) /* 1344 periods of DACClock */
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# define DACC_MR_STARTUP_1408 (22 << DACC_MR_STARTUP_SHIFT) /* 1408 periods of DACClock */
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# define DACC_MR_STARTUP_1472 (23 << DACC_MR_STARTUP_SHIFT) /* 1472 periods of DACClock */
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# define DACC_MR_STARTUP_1536 (24 << DACC_MR_STARTUP_SHIFT) /* 1536 periods of DACClock */
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# define DACC_MR_STARTUP_1600 (25 << DACC_MR_STARTUP_SHIFT) /* 1600 periods of DACClock */
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# define DACC_MR_STARTUP_1664 (26 << DACC_MR_STARTUP_SHIFT) /* 1664 periods of DACClock */
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# define DACC_MR_STARTUP_1728 (27 << DACC_MR_STARTUP_SHIFT) /* 1728 periods of DACClock */
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# define DACC_MR_STARTUP_1792 (28 << DACC_MR_STARTUP_SHIFT) /* 1792 periods of DACClock */
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# define DACC_MR_STARTUP_1856 (29 << DACC_MR_STARTUP_SHIFT) /* 1856 periods of DACClock */
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# define DACC_MR_STARTUP_1920 (30 << DACC_MR_STARTUP_SHIFT) /* 1920 periods of DACClock */
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# define DACC_MR_STARTUP_1984 (31 << DACC_MR_STARTUP_SHIFT) /* 1984 periods of DACClock */
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# define DACC_MR_STARTUP_2048 (32 << DACC_MR_STARTUP_SHIFT) /* 2048 periods of DACClock */
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# define DACC_MR_STARTUP_2112 (33 << DACC_MR_STARTUP_SHIFT) /* 2112 periods of DACClock */
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# define DACC_MR_STARTUP_2176 (34 << DACC_MR_STARTUP_SHIFT) /* 2176 periods of DACClock */
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# define DACC_MR_STARTUP_2240 (35 << DACC_MR_STARTUP_SHIFT) /* 2240 periods of DACClock */
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# define DACC_MR_STARTUP_2304 (36 << DACC_MR_STARTUP_SHIFT) /* 2304 periods of DACClock */
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# define DACC_MR_STARTUP_2368 (37 << DACC_MR_STARTUP_SHIFT) /* 2368 periods of DACClock */
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||||
# define DACC_MR_STARTUP_2432 (38 << DACC_MR_STARTUP_SHIFT) /* 2432 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2496 (39 << DACC_MR_STARTUP_SHIFT) /* 2496 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2560 (40 << DACC_MR_STARTUP_SHIFT) /* 2560 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2624 (41 << DACC_MR_STARTUP_SHIFT) /* 2624 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2688 (42 << DACC_MR_STARTUP_SHIFT) /* 2688 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2752 (43 << DACC_MR_STARTUP_SHIFT) /* 2752 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2816 (44 << DACC_MR_STARTUP_SHIFT) /* 2816 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2880 (45 << DACC_MR_STARTUP_SHIFT) /* 2880 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_2944 (46 << DACC_MR_STARTUP_SHIFT) /* 2944 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3008 (47 << DACC_MR_STARTUP_SHIFT) /* 3008 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3072 (48 << DACC_MR_STARTUP_SHIFT) /* 3072 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3136 (49 << DACC_MR_STARTUP_SHIFT) /* 3136 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3200 (50 << DACC_MR_STARTUP_SHIFT) /* 3200 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3264 (51 << DACC_MR_STARTUP_SHIFT) /* 3264 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3328 (52 << DACC_MR_STARTUP_SHIFT) /* 3328 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3392 (53 << DACC_MR_STARTUP_SHIFT) /* 3392 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3456 (54 << DACC_MR_STARTUP_SHIFT) /* 3456 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3520 (55 << DACC_MR_STARTUP_SHIFT) /* 3520 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3584 (56 << DACC_MR_STARTUP_SHIFT) /* 3584 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3648 (57 << DACC_MR_STARTUP_SHIFT) /* 3648 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3712 (58 << DACC_MR_STARTUP_SHIFT) /* 3712 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3776 (59 << DACC_MR_STARTUP_SHIFT) /* 3776 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3840 (60 << DACC_MR_STARTUP_SHIFT) /* 3840 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3940 (61 << DACC_MR_STARTUP_SHIFT) /* 3904 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_3968 (62 << DACC_MR_STARTUP_SHIFT) /* 3968 periods of DACClock */
|
||||
# define DACC_MR_STARTUP_4032 (63 << DACC_MR_STARTUP_SHIFT) /* 4032 periods of DACClock */
|
||||
|
||||
/* Channel Enable, Channel Disable, and Channel Status Registers */
|
||||
|
||||
#define DACC_CH0 (1 << 0) /* Bit 0: Channel 0 */
|
||||
#define DACC_CH1 (1 << 1) /* Bit 1: Channel 1 */
|
||||
|
||||
/* Conversion Data Register -- 32-bit data */
|
||||
|
||||
/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
|
||||
|
||||
#define DACC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready Interrupt */
|
||||
#define DACC_INT_EOC (1 << 1) /* Bit 1: End of Conversion Interrupt Flag */
|
||||
#define DACC_INT_ENDTX (1 << 2) /* Bit 2: End of DMA Interrupt Flag */
|
||||
#define DACC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */
|
||||
|
||||
/* Analog Current Register */
|
||||
|
||||
#define DACC_ACR_IBCTLCH_SHIFT (0) /* Bits 0-1: Analog Output Current Control */
|
||||
#define DACC_ACR_IBCTLCH_MASK (3 << DACC_ACR_IBCTLCH_SHIFT
|
||||
#define DACC_ACR_IBCTLCH0 (1 << 0) /* Bit 0: Analog Output Current Control 0 */
|
||||
#define DACC_ACR_IBCTLCH1 (1 << 1) /* Bit 1: Analog Output Current Control 1 */
|
||||
#define DACC_ACR_IBCTLDACCORE_SHIFT (8) /* Bits 8-9: Bias Current Control for DAC Core */
|
||||
#define DACC_ACR_IBCTLDACCORE_MASK (3 << DACC_ACR_IBCTLDACCORE_SHIFT)
|
||||
# define DACC_ACR_IBCTLDACCORE(n) ((uint32_t)(n) << DACC_ACR_IBCTLDACCORE_SHIFT)
|
||||
|
||||
/* Write Protect Mode register */
|
||||
|
||||
#define DACC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
|
||||
#define DACC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
|
||||
#define DACC_WPMR_WPKEY_MASK (0x00ffffff << DACC_WPMR_WPKEY_SHIFT)
|
||||
# define DACC_WPMR_WPKEY_MASK (0x00444143 << DACC_WPMR_WPKEY_SHIFT)
|
||||
|
||||
/* Write Protect Status register */
|
||||
|
||||
#define DACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */
|
||||
#define DACC_WPSR_WPROTADDR_SHIFT (8) /* Bits 8-15: Write protection error address */
|
||||
#define DACC_WPSR_WPROTADDR_MASK (0xff << DACC_WPSR_WPROTADDR_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_DACC_H */
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************************
|
||||
* arch/arm/src/sam34/chip/sam_pdc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -62,29 +62,45 @@
|
||||
#define SAM_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */
|
||||
#define SAM_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */
|
||||
|
||||
/* PDC register adresses ****************************************************************/
|
||||
/* PDC register addresses ***************************************************************/
|
||||
|
||||
/* These 10 registers are mapped in the peripheral memory space at the same offset. */
|
||||
|
||||
/* PDC register bit definitions *********************************************************/
|
||||
|
||||
/* Receive Pointer Register -- 32-bit address value */
|
||||
/* Receive Counter Register -- 16-bit counter value */
|
||||
|
||||
#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */
|
||||
#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT)
|
||||
|
||||
/* Transmit Pointer Register -- 32-bit address value */
|
||||
/* Transmit Counter Register -- 16-bit counter value */
|
||||
|
||||
#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */
|
||||
#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT)
|
||||
|
||||
/* Receive Next Pointer Register -- 32-bit address value */
|
||||
/* Receive Next Counter Register -- 16-bit counter value */
|
||||
|
||||
#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */
|
||||
#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT)
|
||||
|
||||
/* Transmit Next Pointer Register -- 32-bit address value */
|
||||
/* Transmit Next Counter Register -- 16-bit counter value */
|
||||
|
||||
#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */
|
||||
#define PDC_TNCR_TXNCTR_MASK (0xffff << PDC_TNCR_TXNCTR_SHIFT)
|
||||
|
||||
/* Transfer Control Register */
|
||||
|
||||
#define PDC_PTCR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */
|
||||
#define PDC_PTCR_RXTDIS (1 << 1) /* Bit 1: Receiver Transfer Disable */
|
||||
#define PDC_PTCR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */
|
||||
#define PDC_PTCR_TXTDIS (1 << 9) /* Bit 9: Transmitter Transfer Disable */
|
||||
|
||||
/* Transfer Status Register */
|
||||
|
||||
#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */
|
||||
#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user