arch/mips/include/mips32/cp0.h: Fix some copy-paste errors that cause malformed comments and syntax errors when certain CP0 CONFIG1 bits are referenced. Note in Issue 123 by Anonymous.
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@ -340,13 +340,13 @@
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* Compliance Level: Required.
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*/
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#define CP0_CONFIG1_FP (1 << 0 FPU implemented
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#define CP0_CONFIG1_EP (1 << 1 EJTAG implemented
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#define CP0_CONFIG1_CA (1 << 2 Code compression (MIPS16) implemented
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#define CP0_CONFIG1_WR (1 << 3 Watch registers implemented
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#define CP0_CONFIG1_PC (1 << 4 Performance Counter registers implemented
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#define CP0_CONFIG1_MD (1 << 5 MDMX ASE implemented (MIPS64)
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#define CP0_CONFIG1_C2 (1 << 6 Coprocessor 2 implemented
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#define CP0_CONFIG1_FP (1 << 0) /* FPU implemented */
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#define CP0_CONFIG1_EP (1 << 1) /* EJTAG implemented */
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#define CP0_CONFIG1_CA (1 << 2) /* Code compression (MIPS16) implemented */
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#define CP0_CONFIG1_WR (1 << 3) /* Watch registers implemented */
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#define CP0_CONFIG1_PC (1 << 4) /* Performance Counter registers implemented */
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#define CP0_CONFIG1_MD (1 << 5) /* MDMX ASE implemented (MIPS64) */
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#define CP0_CONFIG1_C2 (1 << 6) /* Coprocessor 2 implemented */
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#define CP0_CONFIG1_DA_SHIFT (7) /* Bits 7-9: Dcache associativity */
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#define CP0_CONFIG1_DA_MASK (7 << CP0_CONFIG1_DA_SHIFT)
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# define CP0_CONFIG1_DA_DIRECT (0 << CP0_CONFIG1_DA_SHIFT) /* Direct mapped */
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@ -20,9 +20,9 @@ STATUS
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still missing.
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- Mini-UART Baud divisor calculation,
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- Start-up logic. My understand from what I have read on the internet
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- Start-up logic. My understand from what I have read on the Internet
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is the PiZero OS starts up in hypervisor mode with the MMU and I- and
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D-Caches enabled. This probaby means that the standard, classic ARM
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D-Caches enabled. This probably means that the standard, classic ARM
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startup logic at at arch/arm/src/arm/up_head.S will need to be replaced
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with some custom logic.
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