arch/mips/include/mips32/cp0.h: Fix some copy-paste errors that cause malformed comments and syntax errors when certain CP0 CONFIG1 bits are referenced. Note in Issue 123 by Anonymous.

This commit is contained in:
Gregory Nutt 2018-10-12 14:52:05 -06:00
parent c6c9064464
commit 4d75901cc4
2 changed files with 9 additions and 9 deletions

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@ -340,13 +340,13 @@
* Compliance Level: Required.
*/
#define CP0_CONFIG1_FP (1 << 0 FPU implemented
#define CP0_CONFIG1_EP (1 << 1 EJTAG implemented
#define CP0_CONFIG1_CA (1 << 2 Code compression (MIPS16) implemented
#define CP0_CONFIG1_WR (1 << 3 Watch registers implemented
#define CP0_CONFIG1_PC (1 << 4 Performance Counter registers implemented
#define CP0_CONFIG1_MD (1 << 5 MDMX ASE implemented (MIPS64)
#define CP0_CONFIG1_C2 (1 << 6 Coprocessor 2 implemented
#define CP0_CONFIG1_FP (1 << 0) /* FPU implemented */
#define CP0_CONFIG1_EP (1 << 1) /* EJTAG implemented */
#define CP0_CONFIG1_CA (1 << 2) /* Code compression (MIPS16) implemented */
#define CP0_CONFIG1_WR (1 << 3) /* Watch registers implemented */
#define CP0_CONFIG1_PC (1 << 4) /* Performance Counter registers implemented */
#define CP0_CONFIG1_MD (1 << 5) /* MDMX ASE implemented (MIPS64) */
#define CP0_CONFIG1_C2 (1 << 6) /* Coprocessor 2 implemented */
#define CP0_CONFIG1_DA_SHIFT (7) /* Bits 7-9: Dcache associativity */
#define CP0_CONFIG1_DA_MASK (7 << CP0_CONFIG1_DA_SHIFT)
# define CP0_CONFIG1_DA_DIRECT (0 << CP0_CONFIG1_DA_SHIFT) /* Direct mapped */

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@ -20,9 +20,9 @@ STATUS
still missing.
- Mini-UART Baud divisor calculation,
- Start-up logic. My understand from what I have read on the internet
- Start-up logic. My understand from what I have read on the Internet
is the PiZero OS starts up in hypervisor mode with the MMU and I- and
D-Caches enabled. This probaby means that the standard, classic ARM
D-Caches enabled. This probably means that the standard, classic ARM
startup logic at at arch/arm/src/arm/up_head.S will need to be replaced
with some custom logic.