TMS570: Add FLASH wait state configuration
This commit is contained in:
Gregory Nutt
parent
c9c473997c
commit
4d99e2b0e6
@ -88,7 +88,7 @@
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#define TMS570_FLASH_FEDACSDIS2_OFFSET 0x0c0 /* Flash Error Detection and Correction Sector Disable Register 2 */
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#define TMS570_FLASH_FSMWRENA_OFFSET 0x288 /* FSM Register Write Enable */
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#define TMS570_FLASH_FSMSECTOR_OFFSET 0x2a4 /* FSM Sector Register */
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#define TMS570_FLASH_EEPROMCONFIG_OFFSET 0x2b8 /* EEPROM Emulation Configuration Register */
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#define TMS570_FLASH_EEPROMCFG_OFFSET 0x2b8 /* EEPROM Emulation Configuration Register */
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#define TMS570_FLASH_EECTRL1_OFFSET 0x308 /* EEPROM Emulation Error Detection and Correction Control Register 1 */
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#define TMS570_FLASH_EECTRL2_OFFSET 0x30c /* EEPROM Emulation Error Detection and Correction Control Register 2 */
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#define TMS570_FLASH_EECORERRCNT_OFFSET 0x310 /* EEPROM Emulation Correctable Error Count Register */
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@ -133,7 +133,7 @@
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#define TMS570_FLASH_FEDACSDIS2 (TMS570_FWRAP_BASE+TMS570_FLASH_FEDACSDIS2_OFFSET)
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#define TMS570_FLASH_FSMWRENA (TMS570_FWRAP_BASE+TMS570_FLASH_FSMWRENA_OFFSET)
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#define TMS570_FLASH_FSMSECTOR (TMS570_FWRAP_BASE+TMS570_FLASH_FSMSECTOR_OFFSET)
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#define TMS570_FLASH_EEPROMCONFIG (TMS570_FWRAP_BASE+TMS570_FLASH_EEPROMCONFIG_OFFSET)
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#define TMS570_FLASH_EEPROMCFG (TMS570_FWRAP_BASE+TMS570_FLASH_EEPROMCFG_OFFSET)
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#define TMS570_FLASH_EECTRL1 (TMS570_FWRAP_BASE+TMS570_FLASH_EECTRL1_OFFSET)
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#define TMS570_FLASH_EECTRL2 (TMS570_FWRAP_BASE+TMS570_FLASH_EECTRL2_OFFSET)
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#define TMS570_FLASH_EECORERRCNT (TMS570_FWRAP_BASE+TMS570_FLASH_EECORERRCNT_OFFSET)
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@ -146,7 +146,13 @@
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/* Register Bit-Field Definitions *******************************************************************/
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/* Flash Option Control Register */
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#define FLASH_FRDCNTL_
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#define FLASH_FRDCNTL_ENPIPE (1 << 0) /* Bit 0: Enable Pipeline Mode */
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#define FLASH_FRDCNTL_ASWSTEN (1 << 4) /* Bit 4: Address Setup Wait State Enable */
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#define FLASH_FRDCNTL_RWAIT_SHIFT (8) /* Bits 8-11: Random/data Read Wait State */
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#define FLASH_FRDCNTL_RWAIT_MASK (15 << FLASH_FRDCNTL_RWAIT_SHIFT)
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# define FLASH_FRDCNTL_RWAIT(n) ((uint32_t)(n) << FLASH_FRDCNTL_RWAIT_SHIFT)
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/* Flash Error Detection and Correction Control Register 1 */
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#define FLASH_FEDACTRL1_
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/* Flash Error Detection and Correction Control Register 2 */
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@ -175,8 +181,25 @@
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#define FLASH_FBBUSY_
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/* Flash Bank Access Control Register */
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#define FLASH_FBAC_
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/* Flash Bank Fallback Power Register */
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#define FLASH_FBFALLBACK_
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#define FLASH_FBFALLBACK_BANKPWR0_SHIFT (0) /* Bit 0: Bank 0 Fallback Power Mode */
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#define FLASH_FBFALLBACK_BANKPWR0_MASK (3 << FLASH_FBFALLBACK_BANKPWR0_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR0_SLEEP (0 << FLASH_FBFALLBACK_BANKPWR0_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR0_STDBY (1 << FLASH_FBFALLBACK_BANKPWR0_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR0_ACTIV (3 << FLASH_FBFALLBACK_BANKPWR0_SHIFT)
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#define FLASH_FBFALLBACK_BANKPWR1_SHIFT (2) /* Bit 2: Bank 1 Fallback Power Mode */
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#define FLASH_FBFALLBACK_BANKPWR1_MASK (3 << FLASH_FBFALLBACK_BANKPWR1_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR1_SLEEP (0 << FLASH_FBFALLBACK_BANKPWR1_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR1_STDBY (1 << FLASH_FBFALLBACK_BANKPWR1_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR1_ACTIV (3 << FLASH_FBFALLBACK_BANKPWR1_SHIFT)
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#define FLASH_FBFALLBACK_BANKPWR7_SHIFT (14) /* Bit 14: Bank 7 Fallback Power Mode */
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#define FLASH_FBFALLBACK_BANKPWR7_MASK (3 << FLASH_FBFALLBACK_BANKPWR7_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR7_SLEEP (0 << FLASH_FBFALLBACK_BANKPWR7_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR7_STDBY (1 << FLASH_FBFALLBACK_BANKPWR7_SHIFT)
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# define FLASH_FBFALLBACK_BANKPWR7_ACTIV (3 << FLASH_FBFALLBACK_BANKPWR7_SHIFT)
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/* Flash Bank/Pump Ready Register */
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#define FLASH_FBPRDY_
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/* Flash Pump Access Control Register 1 */
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@ -207,12 +230,27 @@
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#define FLASH_FPAROVR_
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/* Flash Error Detection and Correction Sector Disable Register 2 */
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#define FLASH_FEDACSDIS2_
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/* FSM Register Write Enable */
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#define FLASH_FSMWRENA_
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#define FLASH_FSMWRENA_ENABLE_SHIFT (0) /* Bits 0-2: FSM Write Enable */
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#define FLASH_FSMWRENA_ENABLE_MASK (7 << FLASH_FSMWRENA_ENABLE_SHIFT)
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# define FLASH_FSMWRENA_ENABLE (5 << FLASH_FSMWRENA_ENABLE_SHIFT) /* Enable write to FSM registers */
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# define FLASH_FSMWRENA_DISABLE (2 << FLASH_FSMWRENA_ENABLE_SHIFT) /* Any other value disables */
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/* FSM Sector Register */
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#define FLASH_FSMSECTOR_
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/* EEPROM Emulation Configuration Register */
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#define FLASH_EEPROMCONFIG_
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#define FLASH_EEPROMCFG_GRACE_SHIFT (0) /* Bits 0-7: Auto-suspend Startup Grace Period */
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#define FLASH_EEPROMCFG_GRACE_MASK (0xff << FLASH_EEPROMCFG_GRACE_SHIFT)
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# define FLASH_EEPROMCFG_GRACE(n) ((uint32_t)(n) << FLASH_EEPROMCFG_GRACE_SHIFT)
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#define FLASH_EEPROMCFG_AUTOSUSPEN (1 << 8) /* Bit 8: Auto suspend enable */
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#define FLASH_EEPROMCFG_EWAIT_SHIFT (16) /* Bits 16-19: EEPROM Wait state Counter */
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#define FLASH_EEPROMCFG_EWAIT_MASK (15 << FLASH_EEPROMCFG_EWAIT_SHIFT)
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# define FLASH_EEPROMCFG_EWAIT(n) ((uint32_t)(n) << FLASH_EEPROMCFG_EWAIT_SHIFT)
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/* EEPROM Emulation Error Detection and Correction Control Register 1 */
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#define FLASH_EECTRL1_
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/* EEPROM Emulation Error Detection and Correction Control Register 2 */
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@ -53,6 +53,7 @@
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#include "chip/tms570_sys.h"
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#include "chip/tms570_pcr.h"
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#include "chip/tms570_flash.h"
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#include "tms570_clockconfig.h"
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/****************************************************************************
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@ -243,6 +244,53 @@ static void tms570_lpo_trim(void)
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putreg32(regval, TMS570_SYS_LPOMONCTL);
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}
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/****************************************************************************
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* Name: tms570_flash_setup
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*
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* Description:
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* Set up flash address and data wait states based on the target CPU clock
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* frequency The number of address and data wait states for the target CPU
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* clock frequency are specified in the specific part's datasheet.
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*
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****************************************************************************/
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static void tms570_flash_setup(void)
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{
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uint32_t regval;
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/* Setup flash read mode, address wait states and data wait states
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*
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* ENPIPE=1, Bit 0, Enable pipeline mode.
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* ASWSTEN=0/1, Bit 1, Address Setup Wait State is enabled/disabled.
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* RWAIT=BOARD_RWAIT, Bits 8-11, Wait states added to FLASH read access
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*/
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regval = FLASH_FRDCNTL_ENPIPE | FLASH_FRDCNTL_RWAIT(BOARD_RWAIT);
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#if defined(BOARD_ASWAIT) && BOARD_ASWAIT > 0
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regval |= FLASH_FRDCNTL_ASWSTEN;
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#endif
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putreg32(regval, TMS570_FLASH_FRDCNTL);
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/* Setup flash access wait states for bank 7
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*
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* AUTOSTART_GRACE=2, Bits 0-7, Auto-suspend Startup Grace Period
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* AUTOSUSPEN=0, Bit 8, Auto suspend is disabled.
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* EWAIT=4, Bits 16-19, EEPROM wait states
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*/
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putreg32(FLASH_FSMWRENA_ENABLE, TMS570_FLASH_FSMWRENA);
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regval = FLASH_EEPROMCFG_GRACE(2) | FLASH_EEPROMCFG_EWAIT(BOARD_EWAIT);
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putreg32(regval, TMS570_FLASH_EEPROMCFG);
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putreg32(FLASH_FSMWRENA_DISABLE, TMS570_FLASH_FSMWRENA);
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/* Setup flash bank power modes */
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regval = FLASH_FBFALLBACK_BANKPWR0_ACTIV |
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FLASH_FBFALLBACK_BANKPWR1_SLEEP |
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FLASH_FBFALLBACK_BANKPWR7_ACTIV;
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putreg32(regval, TMS570_FLASH_FBFALLBACK);
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}
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/****************************************************************************
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* Name: tms570_clocksrc_configure
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*
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@ -333,6 +381,14 @@ static void tms570_clocksrc_configure(void)
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putreg32(SYS_VCLKASRC_VCLKA1S_VCLK, TMS570_SYS_VCLKASRC);
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}
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/****************************************************************************
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* Name: tms570_eclk_configure
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*
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* Description:
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* Configure the External Clock (ECLK) pin.
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*
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****************************************************************************/
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static void tms570_eclk_configure(void)
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{
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uint32_t regval;
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@ -409,11 +465,9 @@ void tms570_clockconfig(void)
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#endif
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/* Set up flash address and data wait states based on the target CPU clock
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* frequency The number of address and data wait states for the target CPU
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* clock frequency are specified in the specific part's datasheet.
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*/
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#warning Missing Logic
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/* Set up flash address and data wait states. */
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tms570_flash_setup();
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/* Configure the LPO such that HF LPO is as close to 10MHz as possible */
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