sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

stm32_hrtim: cosmetics

Browse Source
This commit is contained in:
raiden00pl 2017-06-17 22:12:56 +02:00
parent 5e3360b8b9
commit 4d9d3c4a9c
2 changed files with 23 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/src/stm32/stm32_hrtim.c
View File

@ -223,8 +223,8 @@ struct stm32_hrtim_timout_s
struct stm32_hrtim_chopper_s
{
uint16_t start:4; /* Chopper start pulsewidth */
uint16_t duty:3; /* Chopper duty cycle */
uint16_t freq:4; /* Chopper carrier frequency value */
uint16_t duty:3; /* Chopper duty cycle */
uint16_t _res:5; /* Reserved */
};
#endif
@ -271,7 +271,7 @@ struct stm32_hrtim_timcmn_s
{
uint32_t base; /* The base adress of the timer */
uint32_t pclk; /* The frequency of the peripheral clock
* that drives the timer module
* that drives the timer module.
*/
#ifdef HRTIM_HAVE_INTERRUPTS
uint16_t irq; /* interrupts configuration */
@ -303,7 +303,7 @@ struct stm32_hrtim_slave_priv_s
#ifdef HRTIM_HAVE_FAULTS
uint8_t flt; /* Faults configuration.
* First five bits are fault sources,
* last bit is lock configuration
* last bit is lock configuration.
*/
#endif
uint16_t update; /* Update configuration */
@ -326,6 +326,7 @@ struct stm32_hrtim_fault_cfg_s
uint8_t src:1; /* Fault source */
uint8_t filter:4; /* Fault filter */
uint8_t lock:1; /* Fault lock */
uint8_t _res:1; /* Reserved */
};
/* Structure describes HRTIM Faults configuration */
@ -2255,8 +2256,6 @@ static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index)
}
}
errout:
return ret;
}
@ -2811,7 +2810,6 @@ errout:
*
****************************************************************************/
FAR struct hrtim_dev_s* stm32_hrtiminitialize(void)
{
FAR struct hrtim_dev_s *dev;

30
arch/arm/src/stm32/stm32_hrtim.h
View File

@ -118,7 +118,7 @@ enum stm32_hrtim_out_rst_e
HRTIM_OUT_RST_CMP1 = (1 << 28),
HRTIM_OUT_RST_PER = (1 << 29),
HRTIM_OUT_RST_RESYNC = (1 << 30),
HRTIM_OUT_RST_SOFT = (1 << 31),
HRTIM_OUT_RST_SOFT = (1 << 31)
};
/* Source which can force the Tx1/Tx2 output to its active state */
@ -156,7 +156,7 @@ enum stm32_hrtim_out_set_e
HRTIM_OUT_SET_CMP1 = (1 << 28),
HRTIM_OUT_SET_PER = (1 << 29),
HRTIM_OUT_SET_RESYNC = (1 << 30),
HRTIM_OUT_SET_SOFT = (1 << 31),
HRTIM_OUT_SET_SOFT = (1 << 31)
};
/* Events that can reset TimerX Counter */
@ -206,7 +206,7 @@ enum stm32_hrtim_tim_rst_e
HRTIM_RST_EXTEVNT4,
HRTIM_RST_EXTEVNT3,
HRTIM_RST_EXTEVNT2,
HRTIM_RST_EXTEVNT1,
HRTIM_RST_EXTEVNT1
};
/* HRTIM Timer X prescaler */
@ -220,7 +220,7 @@ enum stm32_hrtim_tim_prescaler_e
HRTIM_PRESCALER_16,
HRTIM_PRESCALER_32,
HRTIM_PRESCALER_64,
HRTIM_PRESCALER_128,
HRTIM_PRESCALER_128
};
/* HRTIM Slave Timer fault sources Lock */
@ -228,7 +228,7 @@ enum stm32_hrtim_tim_prescaler_e
enum stm32_hrtim_tim_fault_lock_e
{
HRTIM_TIM_FAULT_RW = 0, /* Slave Timer fault source are read/write */
HRTIM_TIM_FAULT_LOCK = (1 << 7), /* Slave Timer fault source are read only */
HRTIM_TIM_FAULT_LOCK = (1 << 7) /* Slave Timer fault source are read only */
};
/* HRTIM Slave Timer Fault configuration */
@ -239,7 +239,7 @@ enum stm32_hrtim_tim_fault_src_e
HRTIM_TIM_FAULT2 = (1 << 2),
HRTIM_TIM_FAULT3 = (1 << 3),
HRTIM_TIM_FAULT4 = (1 << 4),
HRTIM_TIM_FAULT5 = (1 << 5),
HRTIM_TIM_FAULT5 = (1 << 5)
};
/* HRTIM Fault Source */
@ -251,7 +251,7 @@ enum stm32_hrtim_fault_src_e
};
/* HRTIM External Event Source
* NOTE: according to Table 82 from STM32F334XX Manual
* NOTE: according to Table 82 from STM32F334XX Manual.
*/
enum stm32_hrtim_eev_src_e
@ -299,18 +299,18 @@ enum stm32_hrtim_eev_sampling_e
};
/* HRTIM External Event Mode.
* NOTE: supported only for EEV1-5
* NOTE: supported only for EEV1-5.
*/
enum stm32_hrtim_eev_mode_e
{
HRTIM_EEV_MODE_NORMAL,
HRTIM_EEV_MODE_FAST /* low latency mode */
HRTIM_EEV_MODE_NORMAL = 0,
HRTIM_EEV_MODE_FAST = 1 /* low latency mode */
};
/* External Event filter.
* NOTE: supported only for EEV6-10
* NOTE: supported only for EEV6-10.
*/
enum stm32_hrtim_eev_filter_e
@ -330,7 +330,7 @@ enum stm32_hrtim_eev_filter_e
HRTIM_EEV_EEVSd16_N8 = 12,
HRTIM_EEV_EEVSd32_N5 = 13,
HRTIM_EEV_EEVSd32_N6 = 14,
HRTIM_EEV_EEVSd32_N8 = 15,
HRTIM_EEV_EEVSd32_N8 = 15
};
/* Compare register index */
@ -356,7 +356,7 @@ enum stm32_outputs_e
HRTIM_OUT_TIMD_CH1 = (1 << 6),
HRTIM_OUT_TIMD_CH2 = (1 << 7),
HRTIM_OUT_TIME_CH1 = (1 << 8),
HRTIM_OUT_TIME_CH2 = (1 << 9),
HRTIM_OUT_TIME_CH2 = (1 << 9)
};
/* DAC synchronization event */
@ -366,7 +366,7 @@ enum stm32_hrtim_dacsync_e
HRTIM_DACSYNC_DIS,
HRTIM_DACSYNC_1,
HRTIM_DACSYNC_2,
HRTIM_DACSYNC_3,
HRTIM_DACSYNC_3
};
/* HRTIM Deadtime Locks */
@ -417,7 +417,7 @@ enum stm32_chopper_duty_e
HRTIM_CHP_DUTY_4,
HRTIM_CHP_DUTY_5,
HRTIM_CHP_DUTY_6,
HRTIM_CHP_DUTY_7 ,
HRTIM_CHP_DUTY_7
};
/* Chopper carrier frequency */