SAM4CM: Fix SUPC register definitions. From Max Neklyudov
Remove conditional logic form non-SAM4CM parts (Gregory Nutt)
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Max Neklyudov
Gregory Nutt
parent
01a35ff27f
commit
4dc6164ba1
@ -2,7 +2,7 @@
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* arch/arm/src/sam34/chip/sam4cm_supc.h
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* Supply Controller (SUPC) definitions for the SAM4CM
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -113,15 +113,6 @@
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#define SUPC_MR_
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#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
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#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */
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#endif
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#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */
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#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */
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#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT)
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@ -129,29 +120,18 @@
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/* Supply Controller Wake Up Mode Register */
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */
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#endif
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#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */
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#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */
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#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */
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#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */
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# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */
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# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */
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#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */
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# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT)
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# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */
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# define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
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#endif
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#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */
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#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT)
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# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */
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# define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */
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# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
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#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
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#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
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# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
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@ -161,19 +141,6 @@
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# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
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# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */
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# define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT)
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# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */
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# define SUPC_WUMR_LPDBC_2_RTCOUT0 (1 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 2 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_3_RTCOUT0 (2 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 3 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_4_RTCOUT0 (3 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 4 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_5_RTCOUT0 (4 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 5 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_6_RTCOUT0 (5 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 6 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_7_RTCOUT0 (6 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 7 RTCOUT0 */
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# define SUPC_WUMR_LPDBC_8_RTCOUT0 (7 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 8 RTCOUT0 */
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#endif
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/* System Controller Wake Up Inputs Register */
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#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */
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@ -185,10 +152,6 @@
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/* Supply Controller Status Register */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */
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#endif
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#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */
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#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */
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#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */
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@ -196,14 +159,6 @@
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#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */
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#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
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#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */
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#elif defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */
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# define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */
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#endif
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#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */
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#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
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@ -2,7 +2,7 @@
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* arch/arm/src/sam34/chip/sam_supc.h
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* Supply Controller (SUPC) definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
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*
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* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -182,7 +182,7 @@
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/* Supply Controller Wake Up Mode Register */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4E)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */
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#endif
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