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Correct configuration of GPIO pin interrupts on Kinetis K60. Fromo mrechte.

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This commit is contained in:
Gregory Nutt 2016-04-20 06:41:51 -06:00
parent b8ee28cb57
commit 4e04b3e931
3 changed files with 17 additions and 5 deletions
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2
arch/arm/src/kinetis/kinetis.h
View File

@ -221,7 +221,7 @@
* (restricted to inputs).
*/
#define _PIN_INT_SHIFT (20)
#define _PIN_INT_SHIFT (19)
#define _PIN_INT_MASK (31 << _PIN_INT_SHIFT)
#define _PIN_INTDMA_MASK (3 << _PIN_INT_SHIFT)

2
arch/arm/src/kinetis/kinetis_irq.c
View File

@ -120,7 +120,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
lldbg(" IRQ ENABLE: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE);
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE));
lldbg(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),

18
arch/arm/src/kinetis/kinetis_pinirq.c
View File

@ -379,18 +379,30 @@ void kinetis_pinirqenable(uint32_t pinset)
regval |= PORT_PCR_IRQC_RISING;
break;
case PIN_INT_BOTH : /* Interrupt on falling edge */
case PIN_INT_FALLING : /* Interrupt on falling edge */
regval |= PORT_PCR_IRQC_FALLING;
break;
case PIN_DMA_FALLING : /* nterrupt on either edge */
case PIN_INT_BOTH : /* Interrupt on either edge */
regval |= PORT_PCR_IRQC_BOTH;
break;
case PIN_INT_ONE : /* IInterrupt when logic one */
case PIN_INT_ONE : /* Interrupt when logic one */
regval |= PORT_PCR_IRQC_ONE;
break;
case PIN_DMA_RISING : /* DMA on rising edge */
regval |= PORT_PCR_IRQC_DMARISING;
break;
case PIN_DMA_FALLING : /* DMA on falling edge */
regval |= PORT_PCR_IRQC_DMAFALLING;
break;
case PIN_DMA_BOTH : /* DMA on either edge */
regval |= PORT_PCR_IRQC_DMABOTH;
break;
default:
return;
}