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arch: risc-v: Add SMP support for BUILD_KERNEL

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Summary:
- This commit adds SMP support for BUILD_KERNEL

Impact:
- RISC-V: BUILD_KERNEL + SMP only

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa 2022-10-07 17:17:50 +09:00 committed by Xiang Xiao
parent 0d52b5be56
commit 4e095d2e90
5 changed files with 53 additions and 7 deletions
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16
arch/risc-v/src/common/riscv_cpustart.c
View File

@ -38,6 +38,11 @@
#include "sched/sched.h"
#include "init/init.h"
#include "riscv_internal.h"
#ifdef CONFIG_BUILD_KERNEL
# include "riscv_mmu.h"
#endif
#include "chip.h"
/****************************************************************************
@ -72,6 +77,17 @@ void riscv_cpu_boot(int cpu)
asm("WFI");
#ifdef CONFIG_BUILD_KERNEL
/* Initialize the per CPU areas */
riscv_percpu_add_hart((uintptr_t)cpu);
/* Enable MMU */
binfo("mmu_enable: satp=%lx\n", g_kernel_pgt_pbase);
mmu_enable(g_kernel_pgt_pbase, 0);
#endif
_info("CPU%d Started\n", this_cpu());
#ifdef CONFIG_STACK_COLORATION

6
arch/risc-v/src/common/riscv_mmu.h
View File

@ -115,6 +115,12 @@
#error "Unsupported RISC-V MMU implementation selected"
#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
/****************************************************************************
* Public Data
****************************************************************************/
extern uintptr_t g_kernel_pgt_pbase;
/****************************************************************************
* Name: mmu_satp_reg
*

11
arch/risc-v/src/qemu-rv/hardware/qemu_rv_clint.h
View File

@ -29,8 +29,15 @@
#define QEMU_RV_CLINT_MTIMECMP (QEMU_RV_CLINT_BASE + 0x4000)
#define QEMU_RV_CLINT_MTIME (QEMU_RV_CLINT_BASE + 0xbff8)
#define RISCV_CLINT_MSIP QEMU_RV_CLINT_MSIP
#define QEMU_RV_ACLINT_SSIP (QEMU_RV_ACLINT_BASE + 0x0000)
#define RISCV_IPI RISCV_CLINT_MSIP
#define RISCV_CLINT_MSIP QEMU_RV_CLINT_MSIP
#define RISCV_ACLINT_SSIP QEMU_RV_ACLINT_SSIP
#ifdef CONFIG_ARCH_USE_S_MODE
# define RISCV_IPI RISCV_ACLINT_SSIP
#else
# define RISCV_IPI RISCV_CLINT_MSIP
#endif
#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_CLINT_H */

1
arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h
View File

@ -28,6 +28,7 @@
/* Register Base Address ****************************************************/
#define QEMU_RV_CLINT_BASE 0x02000000
#define QEMU_RV_ACLINT_BASE 0x02f00000
#define QEMU_RV_PLIC_BASE 0x0c000000
#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */

26
arch/risc-v/src/qemu-rv/qemu_rv_start.c
View File

@ -123,6 +123,8 @@ void qemu_rv_start(int mhartid)
showprogress('C');
#ifdef CONFIG_BUILD_KERNEL
/* Setup page tables for kernel and enable MMU */
qemu_rv_mm_init();
#endif
@ -144,13 +146,22 @@ cpux:
#ifdef CONFIG_BUILD_KERNEL
/****************************************************************************
* Name: qemu_rv_start_s
****************************************************************************/
void qemu_rv_start_s(int mhartid)
{
qemu_rv_clear_bss();
/* NOTE: still in M-mode */
/* Initialize the per CPU areas */
if (0 == mhartid)
{
qemu_rv_clear_bss();
riscv_percpu_add_hart(mhartid);
/* Initialize the per CPU areas */
riscv_percpu_add_hart(mhartid);
}
/* Disable MMU and enable PMP */
@ -180,9 +191,14 @@ void qemu_rv_start_s(int mhartid)
WRITE_CSR(mtvec, (uintptr_t)__trap_vec_m);
/* Initialize mtimer before entering to S-mode */
if (0 == mhartid)
{
/* Only the primary CPU needs to initialize mtimer
* before entering to S-mode
*/
up_mtimer_initialize();
up_mtimer_initialize();
}
/* Set mepc to the entry */