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Update some comments

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This commit is contained in:
Gregory Nutt 2015-06-17 06:31:30 -06:00
parent f1e5cb2e38
commit 4e0ba036fa
2 changed files with 23 additions and 4 deletions
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2
arch/arm/src/samdl/sam_dmac.c
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@ -1145,7 +1145,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
* DMAC_CHCTRLB_EVIE=0 - No channel input actions
* DMAC_CHCTRLB_EVOE=0 - Channel event output disabled
* DMAC_CHCTRLB_LVL - Determined by DMACH_FLAG_PRIORITY
* DMAC_CHCTRLB_TRIGSRC - Determined by DMACH_FLAG_PERIPH_TRIG
* DMAC_CHCTRLB_TRIGSRC - Determined by DMACH_FLAG_PERIPH_*XTRIG
* DMAC_CHCTRLB_TRIGACT_BEAT - One trigger required for beat transfer
* DMAC_CHCTRLB_CMD_NOACTION - No action
*/

25
arch/arm/src/samdl/sam_dmac.h
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@ -75,7 +75,12 @@
* be used if, for example, both sides were memory although the naming would be awkward)
*/
/* Common characteristics */
/* Common characteristics
*
* BEATSIZE - The size of one bus transfer or "beat". 8-, 16-, or 32-bits
* STEPSIZE - When the address is incremented, it is increments by how many "beats"?
* STEPSEL - The STEPSIZE may be applied only to the memory to the peripheral.
*/
#define DMACH_FLAG_BEATSIZE_SHIFT (0) /* Bits 0-1: Beat size */
#define DMACH_FLAG_BEATSIZE_MASK (3 << DMACH_FLAG_BEATSIZE_SHIFT)
@ -100,7 +105,16 @@
# define DMACH_FLAG_PRIORITY(n) ((uint32_t)(n) << DMACH_FLAG_PRIORITY_SHIFT)
#define DMACH_FLAG_RUNINSTDBY (1 << 8) /* Bit 8: Run in standby */
/* Peripheral endpoint characteristics */
/* Peripheral endpoint characteristics.
*
* PERIPH_TXTRIG - The TX ID of the peripheral that provides the DMA trigger. This
* is one of the DMA_TRIGSRC_*_TX definitions.
* PERIPH_RXTRIG - The RX ID of the peripheral that provides the DMA trigger. This
* is one of the DMA_TRIGSRC_*_RX definitions.
* PERIPH_INCREMENT - Indicates the that peripheral address should be incremented on
* each "beat"
* PERIPH_QOS - Quality of service for peripheral accesses
*/
#define DMACH_FLAG_PERIPH_TXTRIG_SHIFT (9) /* Bits 9-14: See DMAC_TRIGSRC_*_TX */
#define DMACH_FLAG_PERIPH_TXTRIG_MASK (0x3f << DMACH_FLAG_PERIPH_TXTRIG_SHIFT)
@ -116,7 +130,12 @@
# define DMACH_FLAG_PERIPH_QOS_MEDIUM (2 << DMACH_FLAG_PERIPH_QOS_SHIFT) /* Sensitive latency */
# define DMACH_FLAG_PERIPH_QOS_HIGH (3 << DMACH_FLAG_PERIPH_QOS_SHIFT) /* Critical latency */
/* Memory endpoint characteristics */
/* Memory endpoint characteristics
*
* MEM_INCREMENT - Indicates the that memory address should be incremented on each
* "beat"
* MEM_QOS - Quality of service for memory accesses
*/
#define DMACH_FLAG_MEM_INCREMENT (1 << 24) /* Bit 24: Autoincrement memory address */
#define DMACH_FLAG_MEM_QOS_SHIFT (25) /* Bits 25-26: Memory quality of service */