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Basic USART setup works

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2126 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-10-11 19:52:20 +00:00
parent c268f1e71d
commit 4e9c298c2d
6 changed files with 137 additions and 44 deletions
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99
arch/arm/src/stm32/stm32_flash.h Executable file
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@ -0,0 +1,99 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_flash.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "chip.h"
#include "stm32_memorymap.h"
/************************************************************************************
* Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000
#define STM32_FLASH_KEYR_OFFSET 0x0004
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
#define STM32_FLASH_SR_OFFSET 0x000c
#define STM32_FLASH_CR_OFFSET 0x0010
#define STM32_FLASH_AR_OFFSET 0x0014
#define STM32_FLASH_OBR_OFFSET 0x001c
#define STM32_FLASH_WRPR_OFFSET 0x0020
/* Register Addresses ***************************************************************/
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
#define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
#define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* TODO: FLASH details from the STM32F10xxx Flash programming manual. */
/* Flash Access Control Register (ACR) */
#define ACR_LATENCY_SHIFT (0)
#define ACR_LATENCY_MASK (7 << ACR_LATENCY_SHIFT)
# define ACR_LATENCY_0 (0 << ACR_LATENCY_SHIFT) /* FLASH Zero Latency cycle */
# define ACR_LATENCY_1 (1 << ACR_LATENCY_SHIFT)) /* FLASH One Latency cycle */
# define ACR_LATENCY_2 (2 << ACR_LATENCY_SHIFT) /* FLASH Two Latency cycles */
#define ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
#define ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */

2
arch/arm/src/stm32/stm32_internal.h
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@ -72,7 +72,7 @@
#define GPIO_ALT (0)
/* These bits set the primary function of the pin:
* .... .... .... .... FFF. .... .... ....
* .... .... .... .... .FF. .... .... ....
*/
#define GPIO_CNF_SHIFT 13 /* Bits 13-14: GPIO function */

20
arch/arm/src/stm32/stm32_lowputc.c
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@ -220,11 +220,11 @@ void up_lowputc(char ch)
#ifdef HAVE_CONSOLE
/* Wait until the TX FIFO is not full */
while ((getreg16(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0);
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0);
/* Then send the character */
putreg16((uint16)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
putreg32((uint32)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
#endif
}
@ -330,24 +330,24 @@ void stm32_lowsetup(void)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG)
/* Configure CR2 */
cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
/* Configure CR1 */
cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
/* Configure CR3 */
cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
/* Configure the USART Baud Rate */
@ -355,9 +355,9 @@ void stm32_lowsetup(void)
/* Enable Rx, Tx, and the USART */
cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif
#endif /* CONFIG_STM32_USART1 || CONFIG_STM32_USART2 || CONFIG_STM32_USART3 */
}

1
arch/arm/src/stm32/stm32_memorymap.h
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@ -125,6 +125,7 @@
/* Other registers */
#define STM32_SCS_BASE 0xe000e000
#define STM32_NVIC_BASE 0xe000e000 /* 0xe000e00-0xe000efff: Nested Vectored Interrupt Controller */
#define STM32_DEBUGMCU_BASE 0xe0042000

10
arch/arm/src/stm32/stm32_rcc.c
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@ -48,6 +48,7 @@
#include "chip.h"
#include "stm32_rcc.h"
#include "stm32_flash.h"
#include "stm32_internal.h"
/****************************************************************************
@ -356,11 +357,12 @@ void stm32_clockconfig(void)
if( timeout > 0)
{
#if 0
/* Enable Prefetch Buffer */
/* Enable FLASH prefetch buffer and 2 wait states */
/* Flash 2 wait state */
#endif
regval = getreg32(STM32_FLASH_ACR);
regval &= ~ACR_LATENCY_MASK;
regval |= (ACR_LATENCY_2|ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set the HCLK source/divider */

33
arch/arm/src/stm32/stm32_serial.c
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@ -325,29 +325,20 @@ static uart_dev_t g_usart3port =
* Name: up_serialin
****************************************************************************/
static inline uint16 up_serialin(struct up_dev_s *priv, int offset)
static inline uint32 up_serialin(struct up_dev_s *priv, int offset)
{
return getreg16(priv->usartbase + offset);
return getreg32(priv->usartbase + offset);
}
/****************************************************************************
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, int offset, uint16 value)
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32 value)
{
putreg16(value, priv->usartbase + offset);
}
/****************************************************************************
* Name: up_serialout32
****************************************************************************/
static inline void up_serialout32(struct up_dev_s *priv, int offset, uint32 value)
{
putreg32(value, priv->usartbase + offset);
}
/****************************************************************************
* Name: up_disableusartint
****************************************************************************/
@ -356,8 +347,8 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16 *ie)
{
if (ie)
{
uint16 cr1;
uint16 cr3;
uint32 cr1;
uint32 cr3;
/* USART interrupts:
*
@ -399,7 +390,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16 *ie)
static inline void up_restoreusartint(struct up_dev_s *priv, uint16 ie)
{
uint16 cr;
uint32 cr;
/* Save the interrupt mask */
@ -435,7 +426,7 @@ static int up_setup(struct uart_dev_s *dev)
uint32 mantissa;
uint32 fraction;
uint32 brr;
uint16 regval;
uint32 regval;
/* Note: The logic here depends on the fact that that the USART module
* was enabled and the pins were configured in stm32_lowsetup().
@ -517,7 +508,7 @@ static int up_setup(struct uart_dev_s *dev)
fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
brr |= fraction << USART_BRR_FRAC_SHIFT;
up_serialout32(priv, STM32_USART1_BRR, brr);
up_serialout(priv, STM32_USART1_BRR, brr);
/* Enable Rx, Tx, and the USART */
@ -544,7 +535,7 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint16 regval;
uint32 regval;
/* Disable all interrupts */
@ -786,7 +777,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
static int up_receive(struct uart_dev_s *dev, uint32 *status)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
uint16 dr;
uint32 dr;
/* Get the Rx byte */
@ -794,7 +785,7 @@ static int up_receive(struct uart_dev_s *dev, uint32 *status)
/* Get the Rx byte plux error information. Return those in status */
*status = (uint32)priv->sr << 16 | dr;
*status = priv->sr << 16 | dr;
priv->sr = 0;
/* Then return the actual received byte */
@ -880,7 +871,7 @@ static boolean up_rxavailable(struct uart_dev_s *dev)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
up_serialout(priv, STM32_USART_DR_OFFSET, (uint16)ch);
up_serialout(priv, STM32_USART_DR_OFFSET, (uint32)ch);
}
/****************************************************************************