sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

esp32c3: Simplify irq dispatch logic

Browse Source 
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-04-07 17:30:58 +08:00 committed by Abdelatif Guettouche
parent d38b4965f8
commit 4ebc581c73
2 changed files with 29 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/risc-v/include/esp32c3/irq.h
View File

@ -140,9 +140,8 @@
/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */
#define ESP32C3_IRQ_ECALL_M 0
#define RISCV_NIRQ_INTERRUPTS 1 /* Number of RISC-V dispatched interrupts. */
#define ESP32C3_IRQ_FIRSTPERIPH 1 /* First peripheral IRQ number */
#define RISCV_NIRQ_INTERRUPTS 16 /* Number of RISC-V dispatched interrupts. */
#define ESP32C3_IRQ_FIRSTPERIPH 16 /* First peripheral IRQ number */
/* Peripheral IRQs */

42
arch/risc-v/src/esp32c3/esp32c3_irq.c
View File

@ -24,6 +24,7 @@
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
@ -113,7 +114,7 @@ void up_irqinitialize(void)
/* Attach the ECALL interrupt. */
irq_attach(ESP32C3_IRQ_ECALL_M, riscv_swint, NULL);
irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
#ifdef CONFIG_ESP32C3_GPIO_IRQ
/* Initialize GPIO interrupt support */
@ -355,10 +356,11 @@ void esp32c3_free_cpuint(uint8_t periphid)
IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
{
int irq;
uintptr_t *mepc = regs;
uint8_t cpuint = mcause & RISCV_IRQ_MASK;
bool is_irq = (RISCV_IRQ_BIT & mcause) != 0;
#ifdef CONFIG_ESP32C3_EXCEPTION_ENABLE_CACHE
if (((RISCV_IRQ_BIT & mcause) == 0) &&
if (!is_irq &&
(mcause != RISCV_IRQ_ECALLM))
{
if (!spi_flash_cache_enabled())
@ -371,37 +373,37 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause);
if ((RISCV_IRQ_BIT & mcause) != 0)
{
uint8_t cpuint = mcause & RISCV_IRQ_MASK;
DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX);
irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint);
if (is_irq)
{
/* Clear edge interrupts. */
putreg32(1 << cpuint, INTERRUPT_CPU_INT_CLEAR_REG);
irq = g_cpuint_map[cpuint] + ESP32C3_IRQ_FIRSTPERIPH;
}
else
{
/* It's exception */
irq = mcause;
}
if (mcause == RISCV_IRQ_ECALLM)
{
regs[REG_EPC] += 4;
}
regs = riscv_doirq(irq, regs);
/* Toggle the bit back to zero. */
if (is_irq)
{
putreg32(0, INTERRUPT_CPU_INT_CLEAR_REG);
}
else
{
if (mcause == RISCV_IRQ_ECALLM)
{
*mepc += 4;
regs = riscv_doirq(ESP32C3_IRQ_ECALL_M, regs);
}
else
{
riscv_exception(mcause, regs);
}
}
return regs;
}