From 4f2287e5d70342d0621bbd4431ad9e8908931981 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 16 Feb 2013 18:13:12 +0000 Subject: [PATCH] Add Nuvoton chip selection logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5656 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/Kconfig | 8 +- arch/arm/include/nuc1xx/chip.h | 484 +++++++++++++++++++++++++++++++++ arch/arm/src/nuc1xx/Kconfig | 137 ++++++++++ 3 files changed, 625 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d47218ef64..f25b689811 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -96,8 +96,8 @@ config ARCH_CHIP_LPC43XX ---help--- NPX LPC43XX architectures (ARM Cortex-M4). -config ARCH_CHIP_NUC120 - bool "Nuvoton NUC120" +config ARCH_CHIP_NUC1XX + bool "Nuvoton NUC100/120" select ARCH_CORTEXM0 select ARCH_HAVE_CMNVECTOR ---help--- @@ -167,7 +167,7 @@ config ARCH_CHIP default "lpc2378" if ARCH_CHIP_LPC2378 default "lpc31xx" if ARCH_CHIP_LPC31XX default "lpc43xx" if ARCH_CHIP_LPC43XX - default "nuc1xx" if ARCH_CHIP_NUC120 + default "nuc1xx" if ARCH_CHIP_NUC1XX default "sam3u" if ARCH_CHIP_SAM3U default "stm32" if ARCH_CHIP_STM32 default "str71x" if ARCH_CHIP_STR71X @@ -318,7 +318,7 @@ endif if ARCH_CHIP_LPC43XX source arch/arm/src/lpc43xx/Kconfig endif -if ARCH_CHIP_NUC120 +if ARCH_CHIP_NUC1XX source arch/arm/src/nuc1xx/Kconfig endif if ARCH_CHIP_SAM3U diff --git a/arch/arm/include/nuc1xx/chip.h b/arch/arm/include/nuc1xx/chip.h index 3c4b29f1d1..0cf2c89b8a 100644 --- a/arch/arm/include/nuc1xx/chip.h +++ b/arch/arm/include/nuc1xx/chip.h @@ -46,6 +46,490 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +/* Chip capabilities ****************************************************************/ +/* NUC100 Advanced Line (Low Density) */ + +#if defined(CONFIG_ARCH_CHIP_NUC100LC1BN) /* Flash 32K SRAM 4K, LQFP48 package */ +# define NUC_FLASH (32*1024) /* 32K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 35 /* (35) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100LD1BN) /* Flash 64K SRAM 4K, LQFP48 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 31 /* (35) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100LD2BN) /* Flash 64K SRAM 8K, LQFP48 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (8*1024) /* 8K SRAM */ +# define NUC_NIO 31 /* (35) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100RC1BN) /* Flash 32K SRAM 4K, LQFP64 package */ +# define NUC_FLASH (32*1024) /* 32K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 49 /* (49) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# define NUC_EBI 1 /* Supports EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100RD1BN) /* Flash 64K SRAM 4K, LQFP64 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 49 /* (49) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# define NUC_EBI 1 /* Supports EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100RD2BN) /* Flash 64K SRAM 8K, LQFP64 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (8*1024) /* 4K SRAM */ +# define NUC_NIO 49 /* (49) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# define NUC_EBI 1 /* Supports EBI */ + +/* NUC100 Advanced Line (Medium Density) */ + +#elif defined(CONFIG_ARCH_CHIP_NUC100LD3AN) /* Flash 64K SRAM 16K, LQFP48 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 35 /* (35) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 6 /* (6) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100LE3AN) /* Flash 128K SRAM 16K, LQFP48 package */ +# define NUC_FLASH (128*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 35 /* (35) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 6 /* (6) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100RD3AN) /* Flash 64K SRAM 16K, LQFP64 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 49 /* (49) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparator */ +# define NUC_NPWM 6 /* (6) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100RE3AN) /* Flash 128K SRAM 16K, LQFP64 package */ +# define NUC_FLASH (128*1024) /* 128K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 49 /* (49) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparator */ +# define NUC_NPWM 6 /* (6) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100VD2AN) /* Flash 64K SRAM 8K, LQFP100 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (8*1024) /* 8K SRAM */ +# define NUC_NIO 80 /* (80) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 4 /* (4) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparator */ +# define NUC_NPWM 8 /* (8) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100VD3AN) /* Flash 64K SRAM 16K, LQFP100 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 80 /* (80) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 4 /* (4) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparator */ +# define NUC_NPWM 8 /* (8) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC100VE3AN) /* Flash 128K SRAM 8K, LQFP100 package */ +# define NUC_FLASH (128*1024) /* 128K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 80 /* (80) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 4 /* (4) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 0 /* No USB */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparator */ +# define NUC_NPWM 8 /* (8) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ + +/* NUC120 USB Line (Low Density) */ + +#elif defined(CONFIG_ARCH_CHIP_NUC120LC1BN) /* Flash 32K SRAM 4K, LQFP48 package */ +# define NUC_FLASH (32*1024) /* 32K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 31 /* (31) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120LD1BN) /* Flash 64K SRAM 4K, LQFP48 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 31 /* (31) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120LD2BN) /* Flash 64K SRAM 8K, LQFP48 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (8*1024) /* 8K SRAM */ +# define NUC_NIO 31 /* (31) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120RC1BN) /* Flash 32K SRAM 4K, LQFP64 package */ +# define NUC_FLASH (32*1024) /* 32K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 45 /* (45) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# define NUC_EBI 1 /* Have EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120RD1BN) /* Flash 64K SRAM 4K, LQFP64 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (4*1024) /* 4K SRAM */ +# define NUC_NIO 45 /* (45) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# define NUC_EBI 1 /* Have EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120RD2BN) /* Flash 64K SRAM 8K, LQFP64 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (8*1024) /* 8K SRAM */ +# define NUC_NIO 45 /* (45) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 1 /* 1 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# define NUC_EBI 1 /* Have EBI */ + +/* NUC120 USB Line (Medium Density) */ + +#elif defined(CONFIG_ARCH_CHIP_NUC120LD3AN) /* Flash 64K SRAM 16K, LQFP48 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 31 /* (31) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120LE3AN) /* Flash 128K SRAM 16K, LQFP48 package */ +# define NUC_FLASH (128*1024) /* 128K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 31 /* (31) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 1 /* (1) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 1 /* (1) Analog Comparator */ +# define NUC_NPWM 4 /* (4) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120RD3AN) /* Flash 64K SRAM 16K, LQFP64 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 45 /* (45) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 6 /* (6) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120RE3AN) /* Flash 128K SRAM 16K, LQFP64 package */ +# define NUC_FLASH (128*1024) /* 128K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 45 /* (45) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 2 /* (2) UARTs */ +# define NUC_NSPI 2 /* (2) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 6 /* (6) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120VD2AN) /* Flash 64K SRAM 8K, LQFP100 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (8*1024) /* 8K SRAM */ +# define NUC_NIO 76 /* (76) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 4 /* (4) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 8 /* (8) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120VD3AN) /* Flash 64K SRAM 16K, LQFP100 package */ +# define NUC_FLASH (64*1024) /* 64K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 76 /* (76) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 4 /* (4) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 8 /* (8) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ +#elif defined(CONFIG_ARCH_CHIP_NUC120VE3AN) /* Flash 128K SRAM 16K, LQFP100 package */ +# define NUC_FLASH (128*1024) /* 128K FLASH */ +# define NUC_SRAM (16*1024) /* 16K SRAM */ +# define NUC_NIO 76 /* (76) GPIO */ +# define NUC_NTIMERS 4 /* 4x32-bit Timers */ +# define NUC_NPDMA 9 /* 9 PDMA channels */ +# define NUC_NUARTS 3 /* (3) UARTs */ +# define NUC_NSPI 4 /* (4) SPI */ +# define NUC_NI2C 2 /* (2) I2C */ +# define NUC_NUSB 1 /* (1) USB 2.0 full speed */ +# define NUC_NLIN 0 /* No LIN */ +# define NUC_NCAN 0 /* No CAN */ +# define NUC_NI2S 1 /* (1) I2S */ +# define NUC_NCOMP 2 /* (2) Analog Comparators */ +# define NUC_NPWM 8 /* (8) PWM */ +# define NUC_NADC 8 /* 8x12-bit ADC */ +# define NUC_RTC 1 /* RTC */ +# undef NUC_EBI /* No EBI */ + +#else +# error "Unrecognized NUC1XX chip" +#endif /* NVIC priority levels *************************************************************/ /* Each priority field holds a priority value, 0-3. The lower the value, the greater diff --git a/arch/arm/src/nuc1xx/Kconfig b/arch/arm/src/nuc1xx/Kconfig index 9902936dac..50f72c355e 100644 --- a/arch/arm/src/nuc1xx/Kconfig +++ b/arch/arm/src/nuc1xx/Kconfig @@ -4,3 +4,140 @@ # comment "NUC100/120 Configuration Options" + +choice + prompt "Nuvoton NUC1xx Chip Selection" + default ARCH_CHIP_NUC120LE3AN + depends on ARCH_CHIP_NUC1XX + +config ARCH_CHIP_NUC100LC1BN + bool "NUC100LC1BN + ---help--- + Nuvoton NUC100 low density chip: Flash 32K SRAM 4K, LQFP48 package + +config ARCH_CHIP_NUC100LD1BN + bool "NUC100LD1BN + ---help--- + Nuvoton NUC100 low density chip: Flash 64K SRAM 4K, LQFP48 package + +config ARCH_CHIP_NUC100LD2BN + bool "NUC100LD2BN + ---help--- + Nuvoton NUC100 low density chip: Flash 64K SRAM 8K, LQFP48 package + +config ARCH_CHIP_NUC100RC1BN + bool "NUC100RC1BN + ---help--- + Nuvoton NUC100 low density chip: Flash 32K SRAM 4K, LQFP64 package + +config ARCH_CHIP_NUC100RD1BN + bool "NUC100RD1BN + ---help--- + Nuvoton NUC100 low density chip: Flash 64K SRAM 4K, LQFP64 package + +config ARCH_CHIP_NUC100RD2BN + bool "NUC100RD2BN + ---help--- + Nuvoton NUC100 low density chip: Flash 64K SRAM 8K, LQFP64 package + +config ARCH_CHIP_NUC100LD3AN + bool "NUC100LD3AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP48 package + +config ARCH_CHIP_NUC100LE3AN + bool "NUC100LE3AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 128K SRAM 16K, LQFP48 package + +config ARCH_CHIP_NUC100RD3AN + bool "NUC100RD3AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP64 package + +config ARCH_CHIP_NUC100RE3AN + bool "NUC100RE3AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 128K SRAM 16K, LQFP64 package + +config ARCH_CHIP_NUC100VD2AN + bool "NUC100VD2AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 64K SRAM 8K, LQFP100 package + +config ARCH_CHIP_NUC100VD3AN + bool "NUC100VD3AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 64K SRAM 16K, LQFP100 package + +config ARCH_CHIP_NUC100VE3AN + bool "NUC100VE3AN + ---help--- + Nuvoton NUC100 medium density chip: Flash 128K SRAM 8K, LQFP100 package + +config ARCH_CHIP_NUC120LC1BN + bool "NUC120LC1BN + ---help--- + Nuvoton NUC120 low density chip: Flash 32K SRAM 4K, LQFP48 package + +config ARCH_CHIP_NUC120LD1BN + bool "NUC120LD1BN + ---help--- + Nuvoton NUC120 low density chip: Flash 64K SRAM 4K, LQFP48 package + +config ARCH_CHIP_NUC120LD2BN + bool "NUC120LD2BN + ---help--- + Nuvoton NUC120 low density chip: Flash 64K SRAM 8K, LQFP48 package + +config ARCH_CHIP_NUC120RC1BN + bool "NUC120RC1BN + ---help--- + Nuvoton NUC120 low density chip: Flash 32K SRAM 4K, LQFP64 package + +config ARCH_CHIP_NUC120RD1BN + bool "NUC120RD1BN + ---help--- + Nuvoton NUC120 low density chip: Flash 64K SRAM 4K, LQFP64 package + +config ARCH_CHIP_NUC120RD2BN + bool "NUC120RD2BN + ---help--- + Nuvoton NUC120 low density chip: Flash 64K SRAM 8K, LQFP64 package + +config ARCH_CHIP_NUC120LD3AN + bool "NUC120LD3AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP48 package + +config ARCH_CHIP_NUC120LE3AN + bool "NUC120LE3AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP48 package + +config ARCH_CHIP_NUC120RD3AN + bool "NUC120RD3AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP64 package + +config ARCH_CHIP_NUC120RE3AN + bool "NUC120RE3AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP64 package + +config ARCH_CHIP_NUC120VD2AN + bool "NUC120VD2AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 64K SRAM 8K, LQFP100 package + +config ARCH_CHIP_NUC120VD3AN + bool "NUC120VD3AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 64K SRAM 16K, LQFP100 package + +config ARCH_CHIP_NUC120VE3AN + bool "NUC120VE3AN + ---help--- + Nuvoton NUC120 medium density chip: Flash 128K SRAM 16K, LQFP100 package + +endchoice