diff --git a/arch/arm/src/samv7/chip/sam_qspi.h b/arch/arm/src/samv7/chip/sam_qspi.h
index 0954e2d782..55605634e4 100644
--- a/arch/arm/src/samv7/chip/sam_qspi.h
+++ b/arch/arm/src/samv7/chip/sam_qspi.h
@@ -182,7 +182,7 @@
 /* Serial Clock Register */
 
 #define QSPI_SCR_CPOL              (1 << 0)  /* Bit 0:  Clock Polarity */
-#define QSPI_SCR_NCPHA             (1 << 1)  /* Bit 1:  Clock Phase */
+#define QSPI_SCR_CPHA              (1 << 1)  /* Bit 1:  Clock Phase */
 #define QSPI_SCR_SCBR_SHIFT        (8)       /* Bits 8-15: Serial Clock Baud Rate */
 #define QSPI_SCR_SCBR_MASK         (0xff << QSPI_SCR_SCBR_SHIFT)
 #  define QSPI_SCR_SCBR(n)         ((uint32_t)(n) << QSPI_SCR_SCBR_SHIFT)
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index 391ea8a461..f25564e6b2 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -1155,7 +1155,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
   /* Calculate the new actual frequency */
 
   actual = SAM_QSPI_CLOCK / scbr;
-  qspivdbg("SCR=%08x actual=%d\n", regval, actual);
+  qspivdbg("SCBR=%d actual=%d\n", scbr, actual);
 
   /* Save the frequency setting */
 
@@ -1194,34 +1194,34 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
     {
       /* Yes... Set the mode appropriately:
        *
-       * QSPI  CPOL NCPHA
+       * QSPI  CPOL CPHA
        * MODE
-       *  0    0    1
-       *  1    0    0
-       *  2    1    1
-       *  3    1    0
+       *  0    0    0
+       *  1    0    1
+       *  2    1    0
+       *  3    1    1
        */
 
       regval  = qspi_getreg(priv, SAM_QSPI_SCR_OFFSET);
-      regval &= ~(QSPI_SCR_CPOL | QSPI_SCR_NCPHA);
+      regval &= ~(QSPI_SCR_CPOL | QSPI_SCR_CPHA);
 
       switch (mode)
         {
-        case QSPIDEV_MODE0: /* CPOL=0; NCPHA=1 */
-          regval |= QSPI_SCR_NCPHA;
+        case QSPIDEV_MODE0: /* CPOL=0; CPHA=0 */
           break;
 
-        case QSPIDEV_MODE1: /* CPOL=0; NCPHA=0 */
+        case QSPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+          regval |= QSPI_SCR_CPHA;
           break;
 
-        case QSPIDEV_MODE2: /* CPOL=1; NCPHA=1 */
-          regval |= (QSPI_SCR_CPOL | QSPI_SCR_NCPHA);
-          break;
-
-        case QSPIDEV_MODE3: /* CPOL=1; NCPHA=0 */
+        case QSPIDEV_MODE2: /* CPOL=1; CPHA=0 */
           regval |= QSPI_SCR_CPOL;
           break;
 
+        case QSPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+          regval |= (QSPI_SCR_CPOL | QSPI_SCR_CPHA);
+          break;
+
         default:
           DEBUGASSERT(FALSE);
           return;
@@ -1527,12 +1527,11 @@ static int qspi_hw_initialize(struct sam_qspidev_s *priv)
 
   /* Set up the initial QSPI clock mode:
    *
-   * Mode 0:  CPOL=0; NCPHA=1
+   * Mode 0:  CPOL=0; CPHA=0
    */
 
   regval  = qspi_getreg(priv, SAM_QSPI_SCR_OFFSET);
-  regval &= ~QSPI_SCR_CPOL;
-  regval |= QSPI_SCR_NCPHA;
+  regval &= ~(QSPI_SCR_CPOL | QSPI_SCR_CPHA);
   qspi_putreg(priv, regval, SAM_QSPI_SCR_OFFSET);
 
   regval |= QSPI_SCR_SCBR(1);