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armv7-a: Inner Shareable TLB maintenance operations

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Summary:
- Use Inner Shareable for TLB maintenance operations
- Add config option as CONFIG_ARM_HAVE_MPCORE
- This PR is in preparation for smp with kernel build

Impact:
- armv7-a

Testing:
- sabre-6quad:smp w/ qemu
- sabre-6quad:knsh_smp w/ qemu (WIP)

Signed-off-by: Oki Minabe <minabe.oki@gmail.com>
This commit is contained in:
Oki Minabe 2022-05-05 20:34:40 +09:00 committed by Masayuki Ishikawa
parent 45fb96c508
commit 4fa21c4719
4 changed files with 38 additions and 6 deletions
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9
arch/arm/Kconfig
View File

@ -662,6 +662,7 @@ config ARCH_CORTEXA5
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_TESTSET
select ARM_HAVE_MPCORE
config ARCH_CORTEXA7
bool
@ -672,6 +673,7 @@ config ARCH_CORTEXA7
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_TESTSET
select ARM_HAVE_MPCORE
config ARCH_CORTEXA8
bool
@ -692,6 +694,7 @@ config ARCH_CORTEXA9
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_TESTSET
select ARM_HAVE_MPCORE
config ARCH_ARMV7R
bool
@ -924,6 +927,12 @@ config ARM_HAVE_MPU_UNIFIED
Automatically selected to indicate that the CPU supports a
unified MPU for both instruction and data addresses.
config ARM_HAVE_MPCORE
bool
default n
---help---
Decide whether support MPCore extension
config ARM_MPU
bool "MPU support"
default n

6
arch/arm/src/armv7-a/arm_cpuhead.S
View File

@ -200,11 +200,17 @@ __cpu3_start:
*/
mov r0, #0
#ifdef CONFIG_ARM_HAVE_MPCORE
mcr CP15_TLBIALLIS(r0) /* Invalidate the entire unified TLB */
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLUIS(r0) /* Invalidate I-cache */
#else
mcr CP15_TLBIALL(r0,c7) /* Invalidate the entire unified TLB */
mcr CP15_TLBIALL(r0,c6)
mcr CP15_TLBIALL(r0,c5)
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
#endif
/* Load the page table address.
*

6
arch/arm/src/armv7-a/arm_head.S
View File

@ -326,11 +326,17 @@ __start:
*/
mov r0, #0
#ifdef CONFIG_ARM_HAVE_MPCORE
mcr CP15_TLBIALLIS(r0) /* Invalidate the entire unified TLB */
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLUIS(r0) /* Invalidate I-cache */
#else
mcr CP15_TLBIALL(r0,c7) /* Invalidate the entire unified TLB */
mcr CP15_TLBIALL(r0,c6)
mcr CP15_TLBIALL(r0,c5)
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
#endif
/* Load the page table address.
*

23
arch/arm/src/armv7-a/mmu.h
View File

@ -963,10 +963,10 @@ struct section_mapping_s
.macro cp15_invalidate_tlb_bymva, vaddr
dsb
#if defined(CONFIG_ARCH_CORTEXA8)
mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */
#else
#ifdef CONFIG_ARM_HAVE_MPCORE
mcr p15, 0, \vaddr, c8, c3, 3 /* TLBIMVAAIS */
#else
mcr p15, 0, \vaddr, c8, c7, 1 /* TLBIMVA */
#endif
dsb
isb
@ -1227,7 +1227,16 @@ static inline void cp15_invalidate_tlbs(void)
{
__asm__ __volatile__
(
"\tdsb\n"
#ifdef CONFIG_ARM_HAVE_MPCORE
"\tmcr p15, 0, r0, c8, c3, 0\n" /* TLBIALLIS */
"\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
#else
"\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */
"\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
#endif
"\tdsb\n"
"\tisb\n"
:
:
: "r0", "memory"
@ -1250,10 +1259,12 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
__asm__ __volatile__
(
"\tdsb\n"
#if defined(CONFIG_ARCH_CORTEXA8)
"\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */
#else
#ifdef CONFIG_ARM_HAVE_MPCORE
"\tmcr p15, 0, %0, c8, c3, 3\n" /* TLBIMVAAIS */
"\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
#else
"\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */
"\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
#endif
"\tdsb\n"
"\tisb\n"