Add PHY setup for STM3240G-EVAL Ethernet driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4151 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
55ec626661
commit
4fee2145bd
@ -245,10 +245,18 @@
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#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */
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#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */
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#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT)
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# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
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#if 0 /* Per the reference manual */
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# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */
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# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */
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# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
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# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
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# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
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# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
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#else /* Per the driver example */
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# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
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# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */
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# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
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# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
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# define ETH_MACMIIAR_CR_150_168 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-168 MHz HCLK/102 */
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#endif
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#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */
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#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT)
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#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */
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@ -50,6 +50,7 @@
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/mii.h>
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#include <net/uip/uip.h>
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#include <net/uip/uip-arp.h>
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@ -75,11 +76,22 @@
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* Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* See configs/stm3240g-eval/README.txt for an explanation of the configuration
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* settings.
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*/
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#if STM32_NETHERNET > 1
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# error "Logic to support multiple Ethernet interfaces is incomplete"
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#endif
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#ifndef CONFIG_STM32_SYSCFG
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# error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration"
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#endif
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#ifndef CONFIG_STM32_PHYADDR
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# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration"
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#endif
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#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII)
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# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined"
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#endif
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@ -93,21 +105,91 @@
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# warning "Neither CONFIG_STM32_MII_MCO1 nor CONFIG_STM32_MII_MCO2 defined"
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# endif
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# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2)
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# warning "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined"
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# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined"
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# endif
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#endif
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#ifdef CONFIG_STM32_AUTONEG
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# ifndef CONFIG_STM32_PHYSR
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# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration"
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# endif
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# ifndef CONFIG_STM32_PHYSR_SPEED
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# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration"
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# endif
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# ifndef CONFIG_STM32_PHYSR_100MBPS
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# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration"
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# endif
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# ifndef CONFIG_STM32_PHYSR_MODE
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# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration"
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# endif
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# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX
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# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
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# endif
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#endif
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#ifdef CONFIG_STM32_ETH_PTP
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# warning "CONFIG_STM32_ETH_PTP is not yet supported"
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#endif
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/* This driver always uses enhanced descriptors. However, this would not be
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* the cased if support is added for stamping and/or IPv4 checksum offload
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*/
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#define CONFIG_STM32_ETH_ENHANCEDDESC 1
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/* Ethernet buffer sizes and numbers */
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#ifndef CONFIG_STM32_ETH_RXBUFSIZE
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# define CONFIG_STM32_ETH_RXBUFSIZE CONFIG_NET_BUFSIZE
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#endif
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#ifndef CONFIG_STM32_ETH_TXBUFSIZE
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# define CONFIG_STM32_ETH_TXBUFSIZE CONFIG_NET_BUFSIZE
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#endif
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#ifndef CONFIG_STM32_ETH_RXNBUFFERS
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# define CONFIG_STM32_ETH_RXNBUFFERS 20
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#endif
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#ifndef CONFIG_STM32_ETH_TXNBUFFERS
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# define CONFIG_STM32_ETH_TXNBUFFERS 5
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#endif
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/* Clocking *****************************************************************/
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/* Set MACMIIAR CR bits depending on HCLK setting */
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#if STM32_HCLK_FREQUENCY >= 20000000 && STM32_HCLK_FREQUENCY < 35000000
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# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_20_35
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#elif STM32_HCLK_FREQUENCY >= 35000000 && STM32_HCLK_FREQUENCY < 60000000
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# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_35_60
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#elif STM32_HCLK_FREQUENCY >= 60000000 && STM32_HCLK_FREQUENCY < 100000000
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# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_60_100
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#elif STM32_HCLK_FREQUENCY >= 100000000 && STM32_HCLK_FREQUENCY < 150000000
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# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_100_150
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#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 168000000
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# define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_150_168
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#else
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# error "STM32_HCLK_FREQUENCY not supportable"
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#endif
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/* Timing *******************************************************************/
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/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
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* second
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*/
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#define STM32_WDDELAY (1*CLK_TCK)
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#define STM32_POLLHSEC (1*2)
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#define STM32_WDDELAY (1*CLK_TCK)
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#define STM32_POLLHSEC (1*2)
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/* TX timeout = 1 minute */
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#define STM32_TXTIMEOUT (60*CLK_TCK)
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#define STM32_TXTIMEOUT (60*CLK_TCK)
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/* PHY reset/configuration delays in milliseconds */
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#define PHY_RESET_DELAY (65)
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#define PHY_CONFIG_DELAY (1000)
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/* PHY read/write delays in loop counts */
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#define PHY_READ_TIMEOUT (0x0004ffff)
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#define PHY_WRITE_TIMEOUT (0x0004ffff)
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/* Helpers ******************************************************************/
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/* This is a helper pointer for accessing the contents of the Ethernet
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@ -126,7 +208,9 @@
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struct stm32_ethmac_s
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{
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bool bifup; /* true:ifup false:ifdown */
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uint8_t ifup : 1; /* true:ifup false:ifdown */
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uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
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uint8_t fduplex : 1; /* Full (vs. half) duplex */
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WDOG_ID txpoll; /* TX poll timer */
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WDOG_ID txtimeout; /* TX timeout timer */
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@ -171,9 +255,18 @@ static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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#endif
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/* Initialization */
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/* PHY Initialization */
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static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
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static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value);
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static int stm32_phyinit(FAR struct stm32_ethmac_s *priv);
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/* MAC/DMA Initialization */
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static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv);
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static void stm32_ethreset(FAR struct stm32_ethmac_s *priv);
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static int stm32_macconfig(FAR struct stm32_ethmac_s *priv);
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static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv);
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/****************************************************************************
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* Private Functions
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@ -508,7 +601,7 @@ static int stm32_ifup(struct uip_driver_s *dev)
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/* Enable the Ethernet interrupt */
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priv->bifup = true;
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priv->ifup = true;
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up_enable_irq(STM32_IRQ_ETH);
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return OK;
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}
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@ -551,7 +644,7 @@ static int stm32_ifdown(struct uip_driver_s *dev)
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/* Mark the device "down" */
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priv->bifup = false;
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priv->ifup = false;
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irqrestore(flags);
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return OK;
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}
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@ -588,7 +681,7 @@ static int stm32_txavail(struct uip_driver_s *dev)
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/* Ignore the notification if the interface is not yet up */
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if (priv->bifup)
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if (priv->ifup)
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{
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/* Check if there is room in the hardware to hold another outgoing packet. */
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@ -660,10 +753,124 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
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#endif
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/****************************************************************************
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* Function: stm32_ethgpioconfig
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* Function: stm32_phyread
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*
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* Description:
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* Configure GPIOs for the Ethernet interface.
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* Read a PHY register.
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*
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* Parameters:
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* phydevaddr - The PHY device address
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* phyregaddr - The PHY register address
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* value - The location to return the 16-bit PHY register value.
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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*
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****************************************************************************/
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static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value)
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{
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volatile uint32_t timeout;
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uint32_t regval;
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/* Configure the MACMIIAR register, preserving CSR Clock Range CR[2:0] bits */
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regval = getreg32(STM32_ETH_MACMIIAR);
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regval &= ETH_MACMIIAR_CR_MASK;
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/* Set the PHY device address, PHY register address, and set the buy bit.
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* the ETH_MACMIIAR_MW is clear, indicating a read operation.
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*/
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regval |= (((uint32_t)phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK);
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regval |= (((uint32_t)phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK);
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regval |= ETH_MACMIIAR_MB;
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putreg32(regval, STM32_ETH_MACMIIAR);
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/* Wait for the transfer to complete */
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for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++)
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{
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if ((getreg32(STM32_ETH_MACMIIAR) && ETH_MACMIIAR_MB) == 0)
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{
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*value = (uint16_t)getreg32(STM32_ETH_MACMIIDR);
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return OK;
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}
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}
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ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
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phydevaddr, phyregaddr);
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return -ETIMEDOUT;
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}
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/****************************************************************************
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* Function: stm32_phywrite
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*
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* Description:
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* Write to a PHY register.
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*
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* Parameters:
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* phydevaddr - The PHY device address
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* phyregaddr - The PHY register address
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* value - The 16-bit value to write to the PHY register value.
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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*
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****************************************************************************/
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static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value)
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{
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volatile uint32_t timeout;
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uint32_t regval;
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/* Configure the MACMIIAR register, preserving CSR Clock Range CR[2:0] bits */
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regval = getreg32(STM32_ETH_MACMIIAR);
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regval &= ETH_MACMIIAR_CR_MASK;
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/* Set the PHY device address, PHY register address, and set the busy bit.
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* the ETH_MACMIIAR_MW is set, indicating a write operation.
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*/
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regval |= (((uint32_t)phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK);
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regval |= (((uint32_t)phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK);
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regval |= (ETH_MACMIIAR_MB | ETH_MACMIIAR_MW);
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/* Write the value into the MACIIDR register before setting the new MACMIIAR
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* register value.
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*/
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putreg32(value, STM32_ETH_MACMIIDR);
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putreg32(regval, STM32_ETH_MACMIIAR);
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/* Wait for the transfer to complete */
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for (timeout = 0; timeout < PHY_WRITE_TIMEOUT; timeout++)
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{
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if ((getreg32(STM32_ETH_MACMIIAR) && ETH_MACMIIAR_MB) == 0)
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{
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return OK;
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}
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}
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ndbg("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
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phydevaddr, phyregaddr, value);
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return -ETIMEDOUT;
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}
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/****************************************************************************
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* Function: stm32_phyinit
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*
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* Description:
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* Configure the PHY and determine the link speed/duplex.
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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@ -675,7 +882,153 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
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*
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****************************************************************************/
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#if STM32_NETHERNET == 1
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static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
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{
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volatile uint32_t timeout;
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uint32_t regval;
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uint16_t phyval;
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int ret;
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/* Assume 10MBps and half duplex */
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priv->mbps100 = 0;
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priv->fduplex = 0;
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/* Setup up PHY clocking by setting the SR field in the MACMIIAR register */
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regval = getreg32(STM32_ETH_MACMIIAR);
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regval &= ~ETH_MACMIIAR_CR_MASK;
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regval |= ETH_MACMIIAR_CR;
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putreg32(regval, STM32_ETH_MACMIIAR);
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/* Put the PHY in reset mode */
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ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET);
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if (ret < 0)
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{
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return ret;
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}
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up_mdelay(PHY_RESET_DELAY);
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/* Perform auto-negotion if so configured */
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#ifdef CONFIG_STM32_AUTONEG
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/* Wait for link status */
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for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++)
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{
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ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
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if (ret < 0)
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{
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return ret;
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}
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else if ((phyval & MII_MSR_LINKSTATUS) != 0)
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{
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break;
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}
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}
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if (timeout >= PHY_READ_TIMEOUT)
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{
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ndbg("Timed out waiting for link status\n");
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return -ETIMEDOUT;
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}
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/* Enable auto-gegotiation */
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ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
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if (ret < 0)
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{
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return ret;
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}
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/* Wait until auto-negotiation completes */
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for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++)
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{
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ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
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if (ret < 0)
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{
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return ret;
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}
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else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0)
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{
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break;
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}
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}
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if (timeout >= PHY_READ_TIMEOUT)
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{
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ndbg("Timed out waiting for auto-negotiation\n");
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return -ETIMEDOUT;
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}
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/* Read the result of the auto-negotiation from the PHY-specific register */
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ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval);
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if (ret < 0)
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{
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ndbg("Failed to read PHY status register\n");
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return ret;
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}
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/* Remember the selected speed and duplex modes */
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if ((phyval & CONFIG_STM32_PHYSR_MODE) == CONFIG_STM32_PHYSR_FULLDUPLEX)
|
||||
{
|
||||
priv->fduplex = 1;
|
||||
}
|
||||
|
||||
if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS)
|
||||
{
|
||||
priv->mbps100 = 1;
|
||||
}
|
||||
|
||||
#else /* Auto-negotion not selected */
|
||||
|
||||
phyval = 0;
|
||||
#ifdef CONFIG_STM32_ETHFD
|
||||
phyval |= MII_MCR_FULLDPLX;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_ETH100MBPS
|
||||
phyval |= MII_MCR_SPEED100;
|
||||
#endif
|
||||
|
||||
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
up_mdelay(PHY_CONFIG_DELAY);
|
||||
|
||||
/* Remember the selected speed and duplex modes */
|
||||
|
||||
#ifdef CONFIG_STM32_ETHFD
|
||||
priv->fduplex = 1;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_ETH100MBPS
|
||||
priv->mbps100 = 1;
|
||||
#endif
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_ethgpioconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure GPIOs for the Ethernet interface.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - A reference to the private driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
/* Configure GPIO pins to support Ethernet */
|
||||
@ -704,24 +1057,21 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
|
||||
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
|
||||
*/
|
||||
|
||||
# warning "REVISIT: This is very board-specific"
|
||||
# if defined(CONFIG_STM32_MII_MCO1)
|
||||
/* Configure MC01 to drive the PHY */
|
||||
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
|
||||
* info.
|
||||
*/
|
||||
|
||||
stm32_configgpio(GPIO_MCO1);
|
||||
|
||||
/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */
|
||||
|
||||
stm32_mco1config(RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1PRE_NONE);
|
||||
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
|
||||
|
||||
# elif defined(CONFIG_STM32_MII_MCO2)
|
||||
/* Configure MC02 to drive the PHY */
|
||||
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
|
||||
* info.
|
||||
*/
|
||||
|
||||
stm32_configgpio(GPIO_MCO2);
|
||||
|
||||
/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */
|
||||
|
||||
stm32_mco2config(RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2PRE_NONE);
|
||||
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
|
||||
# endif
|
||||
|
||||
/* MII interface pins (17):
|
||||
@ -776,9 +1126,114 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
|
||||
|
||||
stm32_configgpio(GPIO_ETH_PPS_OUT);
|
||||
}
|
||||
#else
|
||||
# warning "This would need to be re-designed to support multiple interfaces"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_ethreset
|
||||
*
|
||||
* Description:
|
||||
* Reset the Ethernet block.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - A reference to the private driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_ethreset(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Reset the Ethernet on the AHB1 bus */
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB1RSTR);
|
||||
regval |= RCC_AHB1RSTR_ETHMACRST;
|
||||
putreg32(regval, STM32_RCC_AHB1RSTR);
|
||||
|
||||
regval &= ~RCC_AHB1RSTR_ETHMACRST;
|
||||
putreg32(regval, STM32_RCC_AHB1RSTR);
|
||||
|
||||
/* Perform a software reset by setting the SR bit in the DMABMR register.
|
||||
* This Resets all MAC subsystem internal registers and logic. After this
|
||||
* reset all the registers holds their reset values.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_ETH_DMABMR);
|
||||
regval |= ETH_DMABMR_SR;
|
||||
putreg32(regval, STM32_ETH_DMABMR);
|
||||
|
||||
/* Wait for software reset to complete. The SR bit is cleared automatically
|
||||
* after the reset operation has completed in all of the core clock domains.
|
||||
*/
|
||||
|
||||
while ((getreg32(STM32_ETH_DMABMR) & ETH_DMABMR_SR) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_macconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure the Ethernet MAC for DMA operation.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - A reference to the private driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_macconfig(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_ethconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure the Ethernet interface for DMA operation.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - A reference to the private driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* NOTE: The Ethernet clocks were initialized early in the boot-up
|
||||
* sequence in stm32_rcc.c.
|
||||
*/
|
||||
|
||||
/* Reset the Ethernet block */
|
||||
|
||||
stm32_ethreset(priv);
|
||||
|
||||
/* Initialize the PHY */
|
||||
|
||||
ret = stm32_phyinit(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initialize the MAC and DMA */
|
||||
|
||||
return stm32_macconfig(priv);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
@ -811,6 +1266,7 @@ static inline
|
||||
int stm32_ethinitialize(int intf)
|
||||
{
|
||||
struct stm32_ethmac_s *priv;
|
||||
int ret;
|
||||
|
||||
/* Get the interface structure associated with this interface number. */
|
||||
|
||||
@ -838,7 +1294,13 @@ int stm32_ethinitialize(int intf)
|
||||
|
||||
stm32_ethgpioconfig(priv);
|
||||
|
||||
/* Check if a Ethernet chip is recognized at its I/O base */
|
||||
/* Configure the Ethernet interface for DMA operation. */
|
||||
|
||||
ret = stm32_ethconfig(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
@ -849,11 +1311,12 @@ int stm32_ethinitialize(int intf)
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* Put the interface in the down state. This usually amounts to resetting
|
||||
* the device and/or calling stm32_ifdown().
|
||||
*/
|
||||
/* Put the interface in the down state. */
|
||||
|
||||
stm32_ifdown(&priv->dev);
|
||||
|
||||
/* Read the MAC address from the hardware into priv->dev.d_mac.ether_addr_octet */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Register the device with the OS so that socket IOCTLs can be performed */
|
||||
|
||||
|
||||
@ -184,8 +184,14 @@ static inline void rcc_enableahb1(void)
|
||||
#ifdef CONFIG_STM32_ETHMAC
|
||||
/* Ethernet MAC clocking */
|
||||
|
||||
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|
|
||||
RCC_AHB1ENR_ETHMACRXEN|RCC_AHB1ENR_ETHMACPTPEN);
|
||||
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
|
||||
|
||||
#ifdef CONFIG_STM32_ETH_PTP
|
||||
/* Precision Time Protocol (PTP) */
|
||||
|
||||
regval |= RCC_AHB1ENR_ETHMACPTPEN;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_OTGHS
|
||||
|
||||
@ -161,7 +161,9 @@ __reset:
|
||||
* Name: _gen_exception
|
||||
*
|
||||
* Description:
|
||||
* General Exception Vector Handler. Jumps to _exception_handler
|
||||
* General Exception Vector Handler. Jumps to _exception_handler. NOTE:
|
||||
* we set the BEV bit in the status register so all interrupt vectors
|
||||
* should go through the _bev_exception.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
|
||||
@ -374,10 +374,29 @@ STM3240G-EVAL-specific Configuration Options
|
||||
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
|
||||
4-bit transfer mode.
|
||||
|
||||
CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
|
||||
CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
|
||||
CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
may be defined to select full duplex mode. Default: half-duplex
|
||||
CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
may be defined to select 100 MBps speed. Default: 10 Mbps
|
||||
CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. The PHY status register address may diff from PHY to PHY. This
|
||||
configuration sets the address of the PHY status register.
|
||||
CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides bit mask indicating 10 or 100MBps speed.
|
||||
CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides the value of the speed bit(s) indicating 100MBps speed.
|
||||
CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provide bit mask indicating full or half duplex modes.
|
||||
CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides the value of the mode bits indicating full duplex mode.
|
||||
CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
|
||||
but some hooks are indicated with this condition.
|
||||
|
||||
STM3240G-EVAL LCD Hardware Configuration
|
||||
|
||||
|
||||
@ -172,8 +172,26 @@
|
||||
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* Ethernet *************************************************************************/
|
||||
/* We need to provide clocking to the MII PHY via MCO1 (PA8) */
|
||||
|
||||
#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC)
|
||||
|
||||
# if !defined(CONFIG_STM32_MII)
|
||||
# warning "CONFIG_STM32_MII required for Ethernet"
|
||||
# elif !defined(CONFIG_STM32_MII_MCO1)
|
||||
# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII"
|
||||
# else
|
||||
|
||||
/* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */
|
||||
|
||||
# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE
|
||||
# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE
|
||||
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* The STM3240G-EVAL board has 4 LEDs that we will encode as: */
|
||||
|
||||
#define LED_STARTED 0 /* LED1 */
|
||||
@ -185,6 +203,7 @@
|
||||
#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
|
||||
#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
|
||||
|
||||
/* Button definitions ***************************************************************/
|
||||
/* The STM3240G-EVAL supports three buttons: */
|
||||
|
||||
#define BUTTON_WAKEUP 0
|
||||
@ -200,6 +219,7 @@
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
/* UART3:
|
||||
*
|
||||
* - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open)
|
||||
* - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX
|
||||
*/
|
||||
|
||||
@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
|
||||
#
|
||||
# STM32F40xxx Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
|
||||
# CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
# CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
|
||||
# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
# may be defined to select full duplex mode. Default: half-duplex
|
||||
# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
# may be defined to select 100 MBps speed. Default: 10 Mbps
|
||||
# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. The PHY status register address may diff from PHY to PHY. This
|
||||
# configuration sets the address of the PHY status register.
|
||||
# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provides bit mask indicating 10 or 100MBps speed.
|
||||
# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provides the value of the speed bit(s) indicating 100MBps speed.
|
||||
# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provide bit mask indicating full or half duplex modes.
|
||||
# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provides the value of the mode bits indicating full duplex mode.
|
||||
# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
|
||||
# but some hooks are indicated with this condition.
|
||||
#
|
||||
CONFIG_STM32_PHYADDR=0x01
|
||||
CONFIG_STM32_MII=y
|
||||
CONFIG_STM32_MII_MCO1=y
|
||||
CONFIG_STM32_MII_MCO2=n
|
||||
CONFIG_STM32_RMII=n
|
||||
CONFIG_STM32_AUTONEG=y
|
||||
#CONFIG_STM32_ETHFD
|
||||
#CONFIG_STM32_ETH100MB
|
||||
CONFIG_STM32_PHYSR=16
|
||||
CONFIG_STM32_PHYSR_SPEED=0x0002
|
||||
CONFIG_STM32_PHYSR_100MBPS=0x0000
|
||||
CONFIG_STM32_PHYSR_MODE=0x0004
|
||||
CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
|
||||
CONFIG_STM32_ETH_PTP=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
@ -684,7 +713,7 @@ CONFIG_NET=n
|
||||
CONFIG_NET_IPv6=n
|
||||
CONFIG_NSOCKET_DESCRIPTORS=10
|
||||
CONFIG_NET_SOCKOPTS=y
|
||||
CONFIG_NET_BUFSIZE=420
|
||||
CONFIG_NET_BUFSIZE=562
|
||||
CONFIG_NET_TCP=y
|
||||
CONFIG_NET_TCP_CONNS=40
|
||||
CONFIG_NET_MAX_LISTENPORTS=40
|
||||
|
||||
@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
|
||||
#
|
||||
# STM32F40xxx Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
|
||||
# CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
# CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
|
||||
# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
# may be defined to select full duplex mode. Default: half-duplex
|
||||
# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
# may be defined to select 100 MBps speed. Default: 10 Mbps
|
||||
# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. The PHY status register address may diff from PHY to PHY. This
|
||||
# configuration sets the address of the PHY status register.
|
||||
# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provides bit mask indicating 10 or 100MBps speed.
|
||||
# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provides the value of the speed bit(s) indicating 100MBps speed.
|
||||
# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provide bit mask indicating full or half duplex modes.
|
||||
# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
# defined. This provides the value of the mode bits indicating full duplex mode.
|
||||
# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
|
||||
# but some hooks are indicated with this condition.
|
||||
#
|
||||
CONFIG_STM32_PHYADDR=0x01
|
||||
CONFIG_STM32_MII=y
|
||||
CONFIG_STM32_MII_MCO1=y
|
||||
CONFIG_STM32_MII_MCO2=n
|
||||
CONFIG_STM32_RMII=n
|
||||
CONFIG_STM32_AUTONEG=y
|
||||
#CONFIG_STM32_ETHFD
|
||||
#CONFIG_STM32_ETH100MBPS
|
||||
CONFIG_STM32_PHYSR=16
|
||||
CONFIG_STM32_PHYSR_SPEED=0x0002
|
||||
CONFIG_STM32_PHYSR_100MBPS=0x0000
|
||||
CONFIG_STM32_PHYSR_MODE=0x0004
|
||||
CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
|
||||
CONFIG_STM32_ETH_PTP=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
@ -648,7 +677,7 @@ CONFIG_NET=n
|
||||
CONFIG_NET_IPv6=n
|
||||
CONFIG_NSOCKET_DESCRIPTORS=0
|
||||
CONFIG_NET_SOCKOPTS=y
|
||||
CONFIG_NET_BUFSIZE=420
|
||||
CONFIG_NET_BUFSIZE=562
|
||||
CONFIG_NET_TCP=n
|
||||
CONFIG_NET_TCP_CONNS=40
|
||||
CONFIG_NET_MAX_LISTENPORTS=40
|
||||
|
||||
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Reference in New Issue
Block a user