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nxstyle: cleanup UTF-8 Unicode to ASCII

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Signed-off-by: chao an <anchao@xiaomi.com>
This commit is contained in:
chao an 2023-09-18 16:31:07 +08:00 committed by Alan Carvalho de Assis
parent 02a3bbc73b
commit 5026a96cfa
43 changed files with 128 additions and 128 deletions
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2
arch/arm/src/eoss3/eoss3_clockconfig.c
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@ -84,7 +84,7 @@ void eoss3_clockconfig(void)
clk_cfg = getreg32(EOSS3_AIP_OSC_CTRL_1);
clk_cfg &= ~AIP_OSC_CTRL_1_PROG_MASK;
clk_cfg |= 0x980 << AIP_OSC_CTRL_1_PROG_SHIFT; /* (prog + 3) ∗ 32,768Hz */
clk_cfg |= 0x980 << AIP_OSC_CTRL_1_PROG_SHIFT; /* (prog + 3) * 32,768Hz */
putreg32(clk_cfg, EOSS3_AIP_OSC_CTRL_1);
/* Wait for the lock, we need to wait for lock twice

4
arch/arm/src/imx6/imx_timerisr.c
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@ -179,7 +179,7 @@ void up_timer_initialize(void)
putreg32(0, IMX_GPT_IR);
/* Configure Output Mode to unconnected/ disconnected—Write zeros in OM3,
/* Configure Output Mode to unconnected/ disconnected-Write zeros in OM3,
* OM2, and OM1 in GPT_CR.
*/
@ -187,7 +187,7 @@ void up_timer_initialize(void)
cr |= (GPT_CR_OM1_DISCON | GPT_CR_OM2_DISCON | GPT_CR_OM3_DISCON);
putreg32(cr, IMX_GPT_CR);
/* Disable Input Capture Modes—Write zeros in IM1 and IM2 in GPT_CR */
/* Disable Input Capture Modes-Write zeros in IM1 and IM2 in GPT_CR */
cr &= ~(GPT_CR_IM1_MASK | GPT_CR_IM2_MASK);
cr |= (GPT_CR_IM1_DISABLED | GPT_CR_IM2_DISABLED);

2
arch/arm/src/kl/kl_spi.c
View File

@ -288,7 +288,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
* divisor in the range {2, 4, 8, 16, 32, 64, 128, 256, or 512).
*
*
* BaudRateDivisor = (SPPR + 1) × 2^(SPR + 1)
* BaudRateDivisor = (SPPR + 1) * 2^(SPR + 1)
* BaudRate = BusClock / BaudRateDivisor
*
* The strategy is to pick the smallest divisor that yields an in-range

8
arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
View File

@ -1862,9 +1862,9 @@ static int lpc17_40_addmac(struct net_driver_s *dev, const uint8_t *mac)
/* Enabled multicast address filtering in the RxFilterControl register:
*
* AcceptUnicastHashEn: When set to ’1’, unicast frames that pass the
* AcceptUnicastHashEn: When set to '1', unicast frames that pass the
* imperfect hash filter are accepted.
* AcceptMulticastHashEn When set to ’1’, multicast frames that pass
* AcceptMulticastHashEn When set to '1', multicast frames that pass
* the imperfect hash filter are accepted.
*/
@ -1944,9 +1944,9 @@ static int lpc17_40_rmmac(struct net_driver_s *dev, const uint8_t *mac)
if (regval == 0 && lpc17_40_getreg(regaddr2) == 0)
{
/* AcceptUnicastHashEn: When set to ’1’, unicast frames that pass
/* AcceptUnicastHashEn: When set to '1', unicast frames that pass
* the imperfect hash filter are accepted.
* AcceptMulticastHashEn When set to ’1’, multicast frames that
* AcceptMulticastHashEn When set to '1', multicast frames that
* pass the imperfect hash filter are accepted.
*/

4
arch/arm/src/sam34/sam_dmac.c
View File

@ -1109,7 +1109,7 @@ static inline int sam_single(struct sam_dma_s *dmach)
putreg32(dmach->cfg, dmach->base + SAM_DMACHAN_CFG_OFFSET);
/* Enable the channel by writing a <EFBFBD>1<EFBFBD> to the CHER enable bit */
/* Enable the channel by writing a '1' to the CHER enable bit */
putreg32(DMAC_CHER_ENA(dmach->chan), SAM_DMAC_CHER);
@ -1173,7 +1173,7 @@ static inline int sam_multiple(struct sam_dma_s *dmach)
putreg32((uint32_t)llhead, dmach->base + SAM_DMACHAN_DSCR_OFFSET);
/* Finally, enable the channel by writing a <EFBFBD>1<EFBFBD> to the CHER enable */
/* Finally, enable the channel by writing a '1' to the CHER enable */
putreg32(DMAC_CHER_ENA(dmach->chan), SAM_DMAC_CHER);

2
arch/arm/src/sama5/sam_can.c
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@ -1552,7 +1552,7 @@ static void can_interrupt(int irq, void *context, void *arg)
* (1 x tCAN).
* 2. Propagation segment (PROP_SEG): This part of the bit time is used
* to compensate for the physical delay times within the network. It is
* twice the sum of the signal<EFBFBD>s propagation time on the bus line, the
* twice the sum of the signals propagation time on the bus line, the
* input comparator delay, and the output driver delay. It is
* programmable to be 1 to 8 Tq long. This parameter is defined in the
* PROPAG field of the CAN Baudrate Register.

2
arch/arm/src/samd2l2/sam_spi.c
View File

@ -20,7 +20,7 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
/****************************************************************************

18
arch/arm/src/samd2l2/sam_usb.c
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@ -31,19 +31,19 @@
*
* Device mode
* - Supports 8 IN endpoints and 8 OUT endpoints
* – No endpoint size limitations
* – Built-in DMA with multi-packet and dual bank for all endpoints
* – Supports feedback endpoint
* – Supports crystal less clock
* - No endpoint size limitations
* - Built-in DMA with multi-packet and dual bank for all endpoints
* - Supports feedback endpoint
* - Supports crystal less clock
*
* Host mode
* - Supports 8 physical pipes
* – No pipe size limitations
* – Supports multiplexed virtual pipe on one physical pipe to allow an
* - No pipe size limitations
* - Supports multiplexed virtual pipe on one physical pipe to allow an
* unlimited USB tree
* – Built-in DMA with multi-packet support and dual bank for all pipes
* – Supports feedback endpoint
* – Supports the USB 2.0 Phase-locked SOFs feature
* - Built-in DMA with multi-packet support and dual bank for all pipes
* - Supports feedback endpoint
* - Supports the USB 2.0 Phase-locked SOFs feature
*
****************************************************************************/

18
arch/arm/src/samd5e5/sam_usb.c
View File

@ -31,19 +31,19 @@
*
* Device mode
* - Supports 8 IN endpoints and 8 OUT endpoints
* – No endpoint size limitations
* – Built-in DMA with multi-packet and dual bank for all endpoints
* – Supports feedback endpoint
* – Supports crystal less clock
* - No endpoint size limitations
* - Built-in DMA with multi-packet and dual bank for all endpoints
* - Supports feedback endpoint
* - Supports crystal less clock
*
* Host mode
* - Supports 8 physical pipes
* – No pipe size limitations
* – Supports multiplexed virtual pipe on one physical pipe to allow an
* - No pipe size limitations
* - Supports multiplexed virtual pipe on one physical pipe to allow an
* unlimited USB tree
* – Built-in DMA with multi-packet support and dual bank for all pipes
* – Supports feedback endpoint
* – Supports the USB 2.0 Phase-locked SOFs feature
* - Built-in DMA with multi-packet support and dual bank for all pipes
* - Supports feedback endpoint
* - Supports the USB 2.0 Phase-locked SOFs feature
*
****************************************************************************/

4
arch/arm/src/samv7/sam_qencoder.c
View File

@ -324,8 +324,8 @@ int sam_qeinitialize(const char *devpath, int tc)
/* Allocate the timer/counter and select its mode of operation */
mode = TC_CMR_TCCLKS_XC0 | /* Use XC0 as an external TCCLKS value */
TC_CMR_ETRGEDG_RISING | /* Select ‘Rising edge’ as the External Trigger Edge */
TC_CMR_ABETRG | /* Select ‘TIOAx’ as the External Trigger */
TC_CMR_ETRGEDG_RISING | /* Select 'Rising edge' as the External Trigger Edge */
TC_CMR_ABETRG | /* Select 'TIOAx' as the External Trigger */
TC_CMR_CAPTURE; /* Select 'Capture mode' */
priv->tch = sam_tc_allocate(tc * SAM_TC_NCHANNELS, mode);

2
arch/arm/src/stm32h7/stm32_adc.c
View File

@ -1225,7 +1225,7 @@ static void adc_enable(struct stm32_dev_s *priv)
up_udelay(20);
/* Enable ADC calibration. ADCALDIF == 0 so this is only for
/* Enable ADC calibration. ADCALDIF == 0 so this is only for
* single-ended conversions, not for differential ones.
*/

2
arch/arm64/src/a64/a64_de.c
View File

@ -794,7 +794,7 @@ int a64_de_ui_channel_init(uint8_t channel,
* (Input Data Format is XRGB 8888 or ARGB 8888)
* Set LAY_ALPHA_MODE (Bits 1 to 2) to 2
* (Global Alpha is mixed with Pixel Alpha)
* (Input Alpha Value = Global Alpha Value * Pixel’s Alpha Value)
* (Input Alpha Value = Global Alpha Value * Pixel's Alpha Value)
* Set LAY_EN (Bit 0) to 1 (Enable Layer)
*/

42
arch/arm64/src/a64/a64_twi.c
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@ -479,11 +479,11 @@ static inline void twi_disable(struct a64_twi_priv_s *priv)
* Description:
* Enable i2c bus by A64_TWI_CNTR_REG
*
* 1’b0: The TWI bus inputs ISDA/ISCL are ignored and the TWI Controller
* 1'b0: The TWI bus inputs ISDA/ISCL are ignored and the TWI Controller
* will not respond to any address on the bus
* 1’b1: The TWI will respond to calls to its slave address – and to
* 1'b1: The TWI will respond to calls to its slave address - and to
* the general call address if the GCE bit in the ADDR register is set.
* Notes: In master operation mode, this bit should be set to ‘1’
* Notes: In master operation mode, this bit should be set to '1'
*
****************************************************************************/
@ -500,8 +500,8 @@ static inline void twi_enable(struct a64_twi_priv_s *priv)
* Description:
* Enable i2c bus interrupt
* Interrupt Enable
* bit7: 1’b0: The interrupt line always low
* bit7: 1’b1: The interrupt line will go high when INT_FLAG is set.
* bit7: 1'b0: The interrupt line always low
* bit7: 1'b1: The interrupt line will go high when INT_FLAG is set.
*
****************************************************************************/
@ -526,8 +526,8 @@ static inline void twi_enable_irq(struct a64_twi_priv_s *priv)
* Description:
* Disable i2c bus interrupt
*
* bit7: 1’b0: The interrupt line always low
* bit7: 1’b1: The interrupt line will go high when INT_FLAG is set.
* bit7: 1'b0: The interrupt line always low
* bit7: 1'b1: The interrupt line will go high when INT_FLAG is set.
*
****************************************************************************/
@ -545,15 +545,15 @@ static inline void twi_disable_irq(struct a64_twi_priv_s *priv)
* Description:
* Trigger start signal, the start bit will be cleared automatically
* Master Mode Start
* When M_STA is set to ‘1’, TWI Controller enters master mode and will
* When M_STA is set to '1', TWI Controller enters master mode and will
* transmit a START condition on the bus when the bus is free.
* If the M_STA bit is set to ‘1’ when the TWI Controller is already
* If the M_STA bit is set to '1' when the TWI Controller is already
* in master mode and one or more bytes have been transmitted, then a
* repeated START condition will be sent. If the M_STA bit is set to '1'
* when the TWI is being accessed in slave mode, the TWI will complete the
* data transfer in slave mode then enter master mode when the bus has been
* released.The M_STA bit is cleared automatically after a START condition
* has been sent,writing a ‘0’ to this bit has no effect.
* has been sent,writing a '0' to this bit has no effect.
*
****************************************************************************/
@ -588,13 +588,13 @@ static inline unsigned int twi_get_start(struct a64_twi_priv_s *priv)
* Description:
* Trigger stop signal, the stop bit will be cleared automatically
*
* If M_STP is set to ‘1’ in master mode, a STOP condition is
* transmitted on the TWI bus. If the M_STP bit is set to ‘1’ in slave
* If M_STP is set to '1' in master mode, a STOP condition is
* transmitted on the TWI bus. If the M_STP bit is set to '1' in slave
* mode, the TWI will behave as if a STOP condition has been received,
* but no STOP condition will be transmitted on the TWI bus. If both
* M_STA and M_STP bits are set, the TWI will first transmit the STOP
* condition (if in master mode) then transmit the START condition.
* The M_STP bit is cleared automatically,writing a ‘0’ to this bit has
* The M_STP bit is cleared automatically,writing a '0' to this bit has
* no effect.
*
****************************************************************************/
@ -643,7 +643,7 @@ static inline unsigned int twi_get_int_flag(struct a64_twi_priv_s *priv)
* clear the interrupt flag
*
* INT_FLAG is automatically set to '1' when any of 28 (out of the
* possible 29) states is entered (see ‘STAT Register’ below). The only
* possible 29) states is entered (see 'STAT Register' below). The only
* state that does not set INT_FLAG is state F8h. If the INT_EN bit is
* set, the interrupt line goes high when IFLG is set to '1'. If the TWI
* is operating in slave mode, data transfer is suspended when INT_FLAG
@ -684,7 +684,7 @@ static inline unsigned int twi_get_status(struct a64_twi_priv_s *priv)
* Description:
* Soft reset twi by A64_TWI_SRST_REG
*
* Write ‘1’ to this bit to reset the TWI and clear to ‘0’ when
* Write '1' to this bit to reset the TWI and clear to '0' when
* completing Soft Reset operation.
*
****************************************************************************/
@ -724,12 +724,12 @@ static inline void twi_disable_ack(struct a64_twi_priv_s *priv)
* Description:
* When sending ack or nack, it will send ack automatically
*
* When A_ACK is set to ‘1’, an Acknowledge (low level on SDA) will be
* When A_ACK is set to '1', an Acknowledge (low level on SDA) will be
* sent during the acknowledge clock pulse on the TWI bus if:
* 1. Either the whole of a matching 7-bit slave address or the first or
* the second byte of a matching 10-bit slave address has been received.
* 2. The general call address has been received and the GCE bit in the
* ADDR register is set to ‘1’.
* ADDR register is set to '1'.
* 3. A data byte has been received in master or slave mode.
* When A_ACK is '0', a Not Acknowledge (high level on SDA) will be sent
* when a data byte is received in master or slave mode.
@ -751,10 +751,10 @@ static inline void twi_enable_ack(struct a64_twi_priv_s *priv)
* Set Enhanced Feature Register
*
* Data Byte number follow Read Command Control
* 0— No Data Byte to be written after read command
* 1— Only 1 byte data to be written after read command
* 2— 2 bytes data can be written after read command
* 3— 3 bytes data can be written after read command
* 0- No Data Byte to be written after read command
* 1- Only 1 byte data to be written after read command
* 2- 2 bytes data can be written after read command
* 3- 3 bytes data can be written after read command
*
****************************************************************************/

2
arch/arm64/src/a64/mipi_dsi.c
View File

@ -183,7 +183,7 @@ ssize_t mipi_dsi_long_packet(uint8_t *pktbuf,
const uint8_t dt = cmd;
const uint8_t di = (vc << 6) | dt;
/* Word Count (WC) (2 bytes)：
/* Word Count (WC) (2 bytes):
* Number of bytes in the Packet Payload
*/

2
arch/renesas/src/rx65n/rx65n_eth.c
View File

@ -3212,7 +3212,7 @@ static void rx65n_phy_preamble(void)
* of "IEEE 802.3-2008_section2".
*/
/* Send 32 consecutive 1’s as per 34.3.4.1
/* Send 32 consecutive 1's as per 34.3.4.1
* MII/RMII Management Frame Format
*/

32
arch/renesas/src/rx65n/rx65n_riic.c
View File

@ -449,7 +449,7 @@ static void rx65n_riic_set_icier(struct rx65n_i2c_priv_s *priv,
* Name: rx65n_riic_setclock
*
* Description:
* Sets the I2C bus clock frequency – frequency for the transfer
* Sets the I2C bus clock frequency - frequency for the transfer
*
****************************************************************************/
@ -2150,11 +2150,11 @@ static void rx65n_riic_master_receive(struct rx65n_i2c_priv_s *priv)
* Name: rx65n_riic_rxi0interrupt
*
* Description:
* Interrupt RIIC0 RXI0 handler – Received Data Full Interrupt Handler
* Interrupt RIIC0 RXI0 handler - Received Data Full Interrupt Handler
*
* Occurs under following conditions:
* - Address/data transmission completed in Master Receive Mode
* - Reception of (last data – 1) completed in Master Receive Mode
* - Reception of (last data - 1) completed in Master Receive Mode
* - Reception of last data completed in Master Receive Mode
*
****************************************************************************/
@ -2173,11 +2173,11 @@ static int rx65n_riic_rxi0interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_rxi1interrupt
*
* Description:
* Interrupt RIIC1 RXI1 handler – Received Data Full Interrupt Handler
* Interrupt RIIC1 RXI1 handler - Received Data Full Interrupt Handler
*
* Occurs under following conditions:
* - Address/data transmission completed in Master Receive Mode
* - Reception of (last data – 1) completed in Master Receive Mode
* - Reception of (last data - 1) completed in Master Receive Mode
* - Reception of last data completed in Master Receive Mode
*
****************************************************************************/
@ -2196,11 +2196,11 @@ static int rx65n_riic_rxi1interrupt(int irq, void *context, void *arg)
* Name: rx65n_i2c_rxi2interrupt
*
* Description:
* Interrupt RIIC2 RXI2 handler – Received Data Full Interrupt Handler
* Interrupt RIIC2 RXI2 handler - Received Data Full Interrupt Handler
*
* Occurs under following conditions:
* - Address/data transmission completed in Master Receive Mode
* - Reception of (last data – 1) completed in Master Receive Mode
* - Reception of (last data - 1) completed in Master Receive Mode
* - Reception of last data completed in Master Receive Mode
*
****************************************************************************/
@ -2218,7 +2218,7 @@ static int rx65n_riic_rxi2interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_txi0interrupt
*
* Description:
* Interrupt RIIC0 TXI0 handler – Transmit Data Empty Interrupt Handler
* Interrupt RIIC0 TXI0 handler - Transmit Data Empty Interrupt Handler
*
* Occurs under following conditions:
* - Transmit Buffer is empty
@ -2244,7 +2244,7 @@ static int rx65n_riic_txi0interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_txi1interrupt
*
* Description:
* Interrupt RIIC1 TXI1 handler – Transmit Data Empty Interrupt Handler
* Interrupt RIIC1 TXI1 handler - Transmit Data Empty Interrupt Handler
*
* Occurs under following conditions:
* - Transmit Buffer is empty
@ -2270,7 +2270,7 @@ static int rx65n_riic_txi1interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_txi2interrupt
*
* Description:
* Interrupt RIIC2 TXI2 handler – Transmit Data Empty Interrupt Handler
* Interrupt RIIC2 TXI2 handler - Transmit Data Empty Interrupt Handler
*
* Occurs under following conditions:
* - Transmit Buffer is empty
@ -2296,7 +2296,7 @@ static int rx65n_riic_txi2interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_tei0interrupt
*
* Description:
* Interrupt RIIC0 TEI0 handler – Transmission End Interrupt Handler
* Interrupt RIIC0 TEI0 handler - Transmission End Interrupt Handler
*
* Occurs under following conditions:
* - Address/data transmission completed
@ -2336,7 +2336,7 @@ static int rx65n_riic_tei0interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_tei1interrupt
*
* Description:
* Interrupt RIIC1 TEI1 handler – Transmission End Interrupt Handler
* Interrupt RIIC1 TEI1 handler - Transmission End Interrupt Handler
*
* Occurs under following conditions:
* - Address/data transmission completed
@ -2372,7 +2372,7 @@ static int rx65n_riic_tei1interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_tei2interrupt
*
* Description:
* Interrupt RIIC2 TEI2 handler – Transmission End Interrupt Handler
* Interrupt RIIC2 TEI2 handler - Transmission End Interrupt Handler
*
* Occurs under following conditions:
* - Address/data transmission completed
@ -2408,7 +2408,7 @@ static int rx65n_riic_tei2interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_eei0interrupt
*
* Description:
* Interrupt RIIC0 EEI0 handler – Event/Error Generation Interrupt Handler
* Interrupt RIIC0 EEI0 handler - Event/Error Generation Interrupt Handler
*
* Occurs under following conditions:
* - START condition detected
@ -2532,7 +2532,7 @@ static int rx65n_riic_eei0interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_eei1interrupt
*
* Description:
* Interrupt RIIC1 EEI1 handler – Event/Error Generation Interrupt Handler
* Interrupt RIIC1 EEI1 handler - Event/Error Generation Interrupt Handler
*
* Occurs under following conditions:
* - START condition detected
@ -2652,7 +2652,7 @@ static int rx65n_riic_eei1interrupt(int irq, void *context, void *arg)
* Name: rx65n_riic_eei2interrupt
*
* Description:
* Interrupt RIIC2 EEI2 handler – Event/Error Generation Interrupt Handler
* Interrupt RIIC2 EEI2 handler - Event/Error Generation Interrupt Handler
*
* Occurs under following conditions:
* - START condition detected

4
arch/risc-v/src/esp32c3/esp32c3_pm.c
View File

@ -556,7 +556,7 @@ static int IRAM_ATTR esp32c3_sleep_start(uint32_t pd_flags)
bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
/* Stop UART output so that output is not lost due to APB frequency change.
* For light sleep, suspend UART output — it will resume after wakeup.
* For light sleep, suspend UART output - it will resume after wakeup.
* For deep sleep, wait for the contents of UART FIFO to be sent.
*/
@ -1060,7 +1060,7 @@ void esp32c3_pmstandby(uint64_t time_in_us)
uint64_t hw_diff_us;
#endif
/* don't power down XTAL — powering it up takes different time on. */
/* don't power down XTAL - powering it up takes different time on. */
esp32c3_sleep_enable_rtc_timer_wakeup(time_in_us);
#ifdef CONFIG_ESP32C3_RT_TIMER

2
arch/risc-v/src/mpfs/mpfs_corepwm.c
View File

@ -396,7 +396,7 @@ static int pwm_timer(struct mpfs_pwmtimer_s *priv,
*
* Example for clk = 25MHz, prescale 0 and 32 bit wide registers:
* PWM period granularity PWM_PG = (PRESCALE + 1) / pwmclk =
* 40 ns × 1 = 40 ns, so the smallest step is 40ns
* 40 ns * 1 = 40 ns, so the smallest step is 40ns
* pwmclk = clk / (PRESCALE + 1) = 25,000,000 / (PRESCALE + 1) =
* 25,000,000
*

2
arch/sparc/src/bm3803/bm3803-irq.c
View File

@ -236,7 +236,7 @@ void sparc_clrpend_irq(int irq)
{
if (irq <= BM3803_IRQ_LAST_INTERRUPT)
{
/* written with a ‘1’, in Interrupt Clear Register
/* written with a '1', in Interrupt Clear Register
* will clear the corresponding bit(s) in the interrupt pending
* register
*/

2
arch/sparc/src/bm3823/bm3823-irq.c
View File

@ -241,7 +241,7 @@ void sparc_clrpend_irq(int irq)
{
if (irq <= BM3823_IRQ_LAST_INTERRUPT)
{
/* written with a ‘1’, in Interrupt Clear Register
/* written with a '1', in Interrupt Clear Register
* will clear the corresponding bit(s) in the interrupt pending
* register
*/

2
arch/sparc/src/s698pm/s698pm-irq.c
View File

@ -449,7 +449,7 @@ void sparc_clrpend_irq(int irq)
if ((irq >= S698PM_IRQ_FIRST_INT && irq <= S698PM_IRQ_LAST_INT) ||
(irq > S698PM_IRQ_LAST && irq < NR_IRQS))
{
/* written with a ‘1’, in Interrupt Clear Register
/* written with a '1', in Interrupt Clear Register
* will clear the corresponding bit(s) in the interrupt pending
* register
*/

2
arch/xtensa/src/common/xtensa_assert.c
View File

@ -106,7 +106,7 @@ void xtensa_panic(int xptcode, uint32_t *regs)
* Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT
* register.
* 5 AllocaCause
* MOVSP instruction, if caller’s registers are not in the register
* MOVSP instruction, if caller's registers are not in the register
* file.
* 6 IntegerDivideByZeroCause
* QUOS, QUOU, REMS, or REMU divisor operand is zero.

4
arch/xtensa/src/esp32/esp32_pm.c
View File

@ -557,7 +557,7 @@ static int IRAM_ATTR esp32_sleep_start(uint32_t pd_flags)
uint32_t cur_freq;
/* Stop UART output so that output is not lost due to APB frequency change.
* For light sleep, suspend UART output — it will resume after wakeup.
* For light sleep, suspend UART output - it will resume after wakeup.
* For deep sleep, wait for the contents of UART FIFO to be sent.
*/
@ -970,7 +970,7 @@ void esp32_pmstandby(uint64_t time_in_us)
uint64_t hw_diff_us;
#endif
/* don't power down XTAL — powering it up takes different time on. */
/* don't power down XTAL - powering it up takes different time on. */
esp32_sleep_enable_timer_wakeup(time_in_us);

6
arch/xtensa/src/esp32/esp32_region.c
View File

@ -81,9 +81,9 @@ static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr)
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
* 0 - cached, RW
* 2 - bypass cache, RWX (default value after CPU reset)
* 15 - no access, raise exception
*
****************************************************************************/

6
arch/xtensa/src/esp32s2/esp32s2_region.c
View File

@ -81,9 +81,9 @@ static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr)
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
* 0 - cached, RW
* 2 - bypass cache, RWX (default value after CPU reset)
* 15 - no access, raise exception
*
****************************************************************************/

6
arch/xtensa/src/esp32s3/esp32s3_region.c
View File

@ -81,9 +81,9 @@ static inline void xtensa_write_itlb(uint32_t vpn, uint32_t attr)
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
* 0 - cached, RW
* 2 - bypass cache, RWX (default value after CPU reset)
* 15 - no access, raise exception
*
****************************************************************************/

2
arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c
View File

@ -285,7 +285,7 @@ int esp32s3_configrtcio(int rtcio_num, rtcio_pinattr_t attr)
else if ((attr & RTC_PULLDOWN) != 0)
{
/* The pull-up value of the USB pins are controlled by the
* pins’ pull-up value together with USB pull-up value. USB DP
* pins' pull-up value together with USB pull-up value. USB DP
* pin is default to PU enabled. Note that from ESP32-S2 ECO1,
* USB_EXCHG_PINS feature has been supported. If this efuse is
* burnt, the gpio pin which should be checked is

4
drivers/lcd/st7565.c
View File

@ -958,7 +958,7 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd,
st7565_reset(priv, true);
/* it seems too long but written in NHD‐C12864KGZ DISPLAY
/* it seems too long but written in NHD-C12864KGZ DISPLAY
* INITIALIZATION...
*/
@ -966,7 +966,7 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd,
st7565_reset(priv, false);
/* it seems too long but written in NHD‐C12864KGZ DISPLAY
/* it seems too long but written in NHD-C12864KGZ DISPLAY
* INITIALIZATION...
*/

4
drivers/video/max7456.c
View File

@ -1086,7 +1086,7 @@ static ssize_t __read_cm(FAR struct mx7_dev_s *dev,
while (len != 0)
{
/* "2) Write CMAH[7:0] = xxH to select the character (0–255) to be
/* "2) Write CMAH[7:0] = xxH to select the character (0-255) to be
* read (Figures 10 and 13)."
*
* Put another way: CMAH is the row number in the EEPROM.
@ -1103,7 +1103,7 @@ static ssize_t __read_cm(FAR struct mx7_dev_s *dev,
__mx7_read_nvm(dev);
/* "4) Write CMAL[7:0] = xxH to select the 4-pixel byte (0–63) in
/* "4) Write CMAL[7:0] = xxH to select the 4-pixel byte (0-63) in
* the character to be read (Figures 10 and 13)."
*
* That means CMAL is the column number.

4
drivers/video/vnc/vnc_negotiate.c
View File

@ -279,7 +279,7 @@ int vnc_negotiate(FAR struct vnc_session_s *session)
/* Receive the ClientInit message
*
* "Once the client and server are sure that they’re happy to talk to one
* "Once the client and server are sure that they're happy to talk to one
* another using the agreed security type, the protocol passes to the
* initialization phase. The client sends a ClientInit message followed
* by the server sending a ServerInit message."
@ -307,7 +307,7 @@ int vnc_negotiate(FAR struct vnc_session_s *session)
/* Send the ServerInit message
*
* "After receiving the ClientInit message, the server sends a ServerInit
* message. This tells the client the width and height of the server’s
* message. This tells the client the width and height of the server's
* framebuffer, its pixel format and the name associated with the
* desktop:"
*

10
drivers/wireless/ISM1_868MHzGFSK100kbps.c
View File

@ -30,14 +30,14 @@
/* Settings for 868 MHz, GFSK at 100kbps
*
* ISM Region 1 (Europe) only, Band 868–870 MHz
* ISM Region 1 (Europe) only, Band 868-870 MHz
*
* Frequency ERP Duty Cycle Bandwidth Remarks
* 868 – 868.6 MHz +14 dBm < 1% No limits
* 868.7 – 869.2 MHz +14 dBm < 0.1% No limits
* 869.3 – 869.4 MHz +10 dBm No limits < 25 kHz Appropriate access
* 868 - 868.6 MHz +14 dBm < 1% No limits
* 868.7 - 869.2 MHz +14 dBm < 0.1% No limits
* 869.3 - 869.4 MHz +10 dBm No limits < 25 kHz Appropriate access
* protocol required
* 869.4 – 869.65 MHz +27 dBm < 10% < 25 kHz Channels may be
* 869.4 - 869.65 MHz +27 dBm < 10% < 25 kHz Channels may be
* combined to one
* high speed channel
* 869.7 -870 MHz +7 dBm No limits No limits

2
drivers/wireless/ISM2_433MHzMSK500kbps.c
View File

@ -30,7 +30,7 @@
/* Settings for 905 MHz, GFSK at 250kbps
*
* ISM Region 2 (America) only, Band 902–928 MHz
* ISM Region 2 (America) only, Band 902-928 MHz
*
* Cordless phones 1 W
* Microwave ovens 750 W

2
drivers/wireless/ISM2_905MHzGFSK250kbps.c
View File

@ -30,7 +30,7 @@
/* Settings for 905 MHz, GFSK at 250kbps
*
* ISM Region 2 (America) only, Band 902–928 MHz
* ISM Region 2 (America) only, Band 902-928 MHz
*
* Cordless phones 1 W
* Microwave ovens 750 W

6
drivers/wireless/ieee802154/mrf24j40/mrf24j40.c
View File

@ -88,17 +88,17 @@ static int mrf24j40_energydetect(FAR struct mrf24j40_radio_s *dev,
reg |= 0x30;
mrf24j40_setreg(dev->spi, MRF24J40_TXBCON1, reg);
/* 1. Set RSSIMODE1 0x3E<7> – Initiate RSSI calculation. */
/* 1. Set RSSIMODE1 0x3E<7> - Initiate RSSI calculation. */
mrf24j40_setreg(dev->spi, MRF24J40_BBREG6, 0x80);
/* 2. Wait until RSSIRDY 0x3E<0> is set to ‘1’ – RSSI calculation is
/* 2. Wait until RSSIRDY 0x3E<0> is set to '1' - RSSI calculation is
* complete.
*/
while (!(mrf24j40_getreg(dev->spi, MRF24J40_BBREG6) & 0x01));
/* 3. Read RSSI 0x210<7:0> – The RSSI register contains the averaged RSSI
/* 3. Read RSSI 0x210<7:0> - The RSSI register contains the averaged RSSI
* received power level for 8 symbol periods.
*/

4
drivers/wireless/ieee802154/mrf24j40/mrf24j40_getset.c
View File

@ -137,11 +137,11 @@ int mrf24j40_setchannel(FAR struct mrf24j40_radio_s *dev, uint8_t chan)
return -EINVAL;
}
/* 15. Set channel – See Section 3.4 “Channel Selection”. */
/* 15. Set channel - See Section 3.4 "Channel Selection". */
mrf24j40_setreg(dev->spi, MRF24J40_RFCON0, (chan - 11) << 4 | 0x03);
/* 17. RFCTL (0x36) = 0x04 – Reset RF state machine.
/* 17. RFCTL (0x36) = 0x04 - Reset RF state machine.
* 18. RFCTL (0x36) = 0x00.
*/

6
drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c
View File

@ -175,14 +175,14 @@ static void mrf24j40_slpclkcal(FAR struct mrf24j40_radio_s *dev)
0x01 | MRF24J40_SLPCON1_CLKOUT_DISABLED);
/* Begin calibration by setting the SLPCALEN bit (SLPCAL2 0x20b<4>) to
* ‘1’. Sixteen samples of the SLPCLK are counted and stored in the
* '1'. Sixteen samples of the SLPCLK are counted and stored in the
* SLPCAL register. No need to mask, this is the only writable bit
*/
mrf24j40_setreg(dev->spi, MRF24J40_SLPCAL2, MRF24J40_SLPCAL2_SLPCALEN);
/* Calibration is complete when the SLPCALRDY bit (SLPCAL2 0x20b<7>) is
* set to ‘1’.
* set to '1'.
*/
while (!(mrf24j40_getreg(dev->spi, MRF24J40_SLPCAL2) &
@ -439,7 +439,7 @@ int mrf24j40_reset(FAR struct ieee802154_radio_s *radio)
mrf24j40_setreg(dev->spi, MRF24J40_BBREG6 , 0x40); /* 01000000 Append RSSI to rx packets */
/* Calibrate the Sleep Clock (SLPCLK) frequency. Refer to Section 3.15.1.2
* “Sleep Clock Calibration”.
* "Sleep Clock Calibration".
*/
mrf24j40_slpclkcal(dev);

8
drivers/wireless/nrf24l01.c
View File

@ -1805,10 +1805,10 @@ int nrf24l01_settxpower(FAR struct nrf24l01_dev_s *dev, int outpower)
/* RF_PWR value <-> Output power in dBm
*
* '00' – -18dBm
* '01' – -12dBm
* '10' – -6dBm
* '11' – 0dBm
* '00' - -18dBm
* '01' - -12dBm
* '10' - -6dBm
* '11' - 0dBm
*/
switch (outpower)

2
fs/partition/fs_gpt.c
View File

@ -86,7 +86,7 @@ begin_packed_struct struct gpt_header_s
uint64_t my_lba; /* Current LBA (location of this header copy) */
uint64_t alternate_lba; /* Backup LBA (location of the other header copy) */
uint64_t first_usable_lba; /* First usable LBA for partitions primary partition table last LBA + 1 */
uint64_t last_usable_lba; /* Last usable LBA secondary partition table first LBA − 1 */
uint64_t last_usable_lba; /* Last usable LBA secondary partition table first LBA - 1 */
struct gpt_guid_s disk_guid; /* Disk GUID in mixed endian */
uint64_t partition_entry_lba; /* Starting LBA of array of partition entries (always 2 in primary copy) */
uint32_t num_partition_entries; /* Number of partition entries in array */

2
libs/libm/libm/lib_libexpif.c
View File

@ -54,7 +54,7 @@
* Private Data
****************************************************************************/
/* Values above M_E64 will never be used since it’s larger than FLT_MAX
/* Values above M_E64 will never be used since it's larger than FLT_MAX
*(3.402823e+38).
*/

2
net/sixlowpan/sixlowpan_framelist.c
View File

@ -562,7 +562,7 @@ int sixlowpan_queue_frames(FAR struct radio_driver_s *radio,
* 1. Datagram size describes the total (un-fragmented) payload.
* 2. Datagram tag identifies the set of fragments and is used to
* match fragments of the same payload.
* 3. Datagram offset identifies the fragment’s offset within the
* 3. Datagram offset identifies the fragment's offset within the
* unfragmented payload.
*
* The fragment header length is 4 bytes for the first header and 5

4
tools/nxstyle.c
View File

@ -2653,7 +2653,7 @@ int main(int argc, char **argv, char **envp)
{
/* "--" should be next to its operand. If there are
* whitespaces or non-operand characters on both left
* and right (e.g. "a -- "， “a[i --]”, "(-- i)"),
* and right (e.g. "a -- ", "a[i --]", "(-- i)"),
* there's an error.
*/
@ -2700,7 +2700,7 @@ int main(int argc, char **argv, char **envp)
{
/* "++" should be next to its operand. If there are
* whitespaces or non-operand characters on both left
* and right (e.g. "a ++ "， “a[i ++]”, "(++ i)"),
* and right (e.g. "a ++ ", "a[i ++]", "(++ i)"),
* there's an error.
*/

6
wireless/bluetooth/bt_att.c
View File

@ -841,7 +841,7 @@ static uint8_t att_find_type_req(FAR struct bt_conn_s *conn,
}
/* The Attribute Protocol Find By Type Value Request shall be used with the
* Attribute Type parameter set to the UUID for «Primary Service» and the
* Attribute Type parameter set to the UUID for "Primary Service" and the
* Attribute Value set to the 16-bit Bluetooth UUID or 128-bit UUID for the
* specific primary service.
*/
@ -1367,8 +1367,8 @@ static uint8_t att_read_group_req(FAR struct bt_conn_s *conn,
/* Core v4.2, Vol 3, sec 2.5.3 Attribute Grouping: Not all of the grouping
* attributes can be used in the ATT Read By Group Type Request. The
* «Primary Service» and «Secondary Service» grouping types may be used
* in the Read By Group Type Request. The «Characteristic» grouping type
* "Primary Service" and "Secondary Service" grouping types may be used
* in the Read By Group Type Request. The "Characteristic" grouping type
* shall not be used in the ATT Read By Group Type Request.
*/

6
wireless/ieee802154/mac802154_scan.c
View File

@ -131,7 +131,7 @@ int mac802154_req_scan(MACHANDLE mac, FAR struct ieee802154_scan_req_s *req)
/* ...after switching to the channel for a passive scan, the device
* shall enable its receiver for at most
* [aBaseSuperframeDuration × (2 * n + 1)],
* [aBaseSuperframeDuration * (2 * n + 1)],
* where n is the value of the ScanDuration parameter. [1] pg. 25
*/
@ -299,7 +299,7 @@ void mac802154_edscan_onresult(FAR struct ieee802154_privmac_s *priv,
/* ...after switching to the channel for a passive scan, the device
* shall enable its receiver for at most
* [aBaseSuperframeDuration × (2 * n + 1)],
* [aBaseSuperframeDuration * (2 * n + 1)],
* where n is the value of the ScanDuration parameter. [1] pg. 25
*/
@ -353,7 +353,7 @@ static void mac802154_scantimeout(FAR void *arg)
/* ...after switching to the channel for a passive scan, the device
* shall enable its receiver for at most
* [aBaseSuperframeDuration × (2 * n + 1)],
* [aBaseSuperframeDuration * (2 * n + 1)],
* where n is the value of the ScanDuration parameter. [1] pg. 25
*/