Fix SSP0 hard fault
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2771 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
16640befc4
commit
508c638e42
@ -1164,3 +1164,7 @@
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interrupts.
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* arch/arm/src/lpc17xx/lp17_clockconfig.c - Power was not being
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provided to GPIO module. This is a critical bugfix!
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* arch/arm/src/lpc17xx/lpc17_serial.c - Improved logic to handle
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missed TX interrupts.
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* arch/arm/src/lpc17xx/lpc17_ssp.c - Fix a hard fault during SSP
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initialization.
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@ -1839,6 +1839,10 @@ nuttx-5.8 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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interrupts.
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* arch/arm/src/lpc17xx/lp17_clockconfig.c - Power was not being
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provided to GPIO module. This is a critical bugfix!
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* arch/arm/src/lpc17xx/lpc17_serial.c - Improved logic to handle
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missed TX interrupts.
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* arch/arm/src/lpc17xx/lpc17_ssp.c - Fix a hard fault during SSP
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initialization.
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pascal-2.1 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -142,6 +142,15 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t ch);
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static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
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static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
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/* Initialization */
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#ifdef CONFIG_LPC17_SSP0
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static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void);
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#endif
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#ifdef CONFIG_LPC17_SSP1
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static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void);
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -225,7 +234,7 @@ static struct lpc17_sspdev_s g_ssp1dev =
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static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset)
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{
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return ssp_getreg(priv, priv->sspbase + offset);
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return getreg32(priv->sspbase + (uint32_t)offset);
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}
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/************************************************************************************
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@ -246,7 +255,7 @@ static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offse
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static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset, uint32_t value)
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{
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putreg32(value, priv->sspbase + offset);
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putreg32(value, priv->sspbase + (uint32_t)offset);
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}
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/****************************************************************************
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@ -670,6 +679,110 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
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}
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}
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/****************************************************************************
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* Name: lpc17_ssp0initialize
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*
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* Description:
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* Initialize the SSP0
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*
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* Input Parameter:
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* None
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*
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* Returned Value:
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* Valid SPI device structure reference on succcess; a NULL on failure
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*
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****************************************************************************/
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#ifdef CONFIG_LPC17_SSP0
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static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void)
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{
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irqstate_t flags;
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uint32_t regval;
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/* Configure multiplexed pins as connected on the board. Chip select
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* pins must be configured by board-specific logic. All SSP0 pins and
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* one SSP1 pin (SCK) have multiple, alternative pin selection.
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* Definitions in the board.h file must be provided to resolve the
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* board-specific pin configuration like:
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*
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* #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
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*/
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flags = irqsave();
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lpc17_configgpio(GPIO_SSP0_SCK);
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lpc17_configgpio(GPIO_SSP0_MISO);
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lpc17_configgpio(GPIO_SSP0_MOSI);
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/* Configure clocking */
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regval = getreg32(LPC17_SYSCON_PCLKSEL1);
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regval &= ~SYSCON_PCLKSEL1_SSP0_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL1);
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/* Enable peripheral clocking to SSP0 */
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regval = getreg32(LPC17_SYSCON_PCONP);
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regval |= SYSCON_PCONP_PCSSP0;
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putreg32(regval, LPC17_SYSCON_PCONP);
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irqrestore(flags);
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return &g_ssp0dev;
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}
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#endif
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/****************************************************************************
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* Name: lpc17_ssp1initialize
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*
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* Description:
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* Initialize the SSP1
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*
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* Input Parameter:
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* None
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*
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* Returned Value:
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* Valid SPI device structure reference on succcess; a NULL on failure
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*
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****************************************************************************/
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#ifdef CONFIG_LPC17_SSP1
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static inline FAR struct spi_dev_s *lpc17_ssp1initialize(void)
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{
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irqstate_t flags;
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uint32_t regval;
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/* Configure multiplexed pins as connected on the board. Chip select
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* pins must be configured by board-specific logic. All SSP0 pins and
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* one SSP1 pin (SCK) have multiple, alternative pin selection.
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* Definitions in the board.h file must be provided to resolve the
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* board-specific pin configuration like:
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*
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* #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
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*/
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flags = irqsave();
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lpc17_configgpio(GPIO_SSP1_SCK);
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lpc17_configgpio(GPIO_SSP1_MISO);
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lpc17_configgpio(GPIO_SSP1_MOSI);
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/* Configure clocking */
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regval = getreg32(LPC17_SYSCON_PCLKSEL0);
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regval &= ~SYSCON_PCLKSEL0_SSP1_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL0);
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/* Enable peripheral clocking to SSP0 and SSP1 */
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regval = getreg32(LPC17_SYSCON_PCONP);
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regval |= SYSCON_PCONP_PCSSP1;
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putreg32(regval, LPC17_SYSCON_PCONP);
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irqrestore(flags);
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return &g_ssp1dev;
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -691,7 +804,6 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
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FAR struct spi_dev_s *up_spiinitialize(int port)
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{
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FAR struct lpc17_sspdev_s *priv;
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irqstate_t flags;
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uint32_t regval;
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int i;
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@ -701,69 +813,18 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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{
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#ifdef CONFIG_LPC17_SSP0
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case 0:
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priv = &g_ssp0dev;
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priv = lpc17_ssp0initialize();
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break;
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#endif
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#ifdef CONFIG_LPC17_SSP1
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case 1:
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priv = &g_ssp1dev;
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priv = lpc17_ssp1initialize();
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break;
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#endif
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default:
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return NULL;
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}
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/* Configure multiplexed pins as connected on the board. Chip select
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* pins must be configured by board-specific logic. All SSP0 pins and
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* one SSP1 pin (SCK) have multiple, alternative pin selection.
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* Definitions in the board.h file must be provided to resolve the
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* board-specific pin configuration like:
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*
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* #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
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*/
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flags = irqsave();
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#ifdef CONFIG_LPC17_SSP0
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lpc17_configgpio(GPIO_SSP0_SCK);
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lpc17_configgpio(GPIO_SSP0_MISO);
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lpc17_configgpio(GPIO_SSP0_MOSI);
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#endif
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#ifdef CONFIG_LPC17_SSP1
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lpc17_configgpio(GPIO_SSP1_SCK);
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lpc17_configgpio(GPIO_SSP1_MISO);
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lpc17_configgpio(GPIO_SSP1_MOSI);
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#endif
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/* Configure clocking */
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#ifdef CONFIG_LPC17_SSP0
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regval = getreg32(LPC17_SYSCON_PCLKSEL1);
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regval &= ~SYSCON_PCLKSEL1_SSP0_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL1);
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#endif
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#ifdef CONFIG_LPC17_SSP1
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regval = getreg32(LPC17_SYSCON_PCLKSEL0);
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regval &= ~SYSCON_PCLKSEL0_SSP1_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL0);
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#endif
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/* Enable peripheral clocking to SSP0 and SSP1 */
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regval = getreg32(LPC17_SYSCON_PCONP);
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regval &= ~(SYSCON_PCONP_PCSSP0|SYSCON_PCONP_PCSSP1);
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#ifdef CONFIG_LPC17_SSP0
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regval |= SYSCON_PCONP_PCSSP0;
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#endif
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#ifdef CONFIG_LPC17_SSP1
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regval |= SYSCON_PCONP_PCSSP1;
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#endif
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putreg32(regval, LPC17_SYSCON_PCONP);
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irqrestore(flags);
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/* Configure 8-bit SPI mode */
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ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI);
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@ -795,7 +856,6 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
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regval = ssp_getreg(priv, LPC17_SSP_CR1_OFFSET);
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ssp_putreg(priv, LPC17_SSP_CR1_OFFSET, regval | SSP_CR1_SSE);
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for (i = 0; i < LPC17_SSP_FIFOSZ; i++)
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{
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(void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET);
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