From 509350a61410eba6087df731e2f949f763cf374e Mon Sep 17 00:00:00 2001 From: Eero Nurkkala Date: Thu, 23 Dec 2021 13:05:09 +0200 Subject: [PATCH] risc-v/mpfs: update m100pfsevp board info Update the cache settings for the Aries m100pfsevp board. This assigns scratchpad ways for this board as well, as seen in the commit 491ae6c. Signed-off-by: Eero Nurkkala --- .../m100pfsevp/include/board_liberodefs.h | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h index 9759501d77..798ffa8ae9 100644 --- a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h +++ b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h @@ -591,23 +591,23 @@ /* Cache settings */ -#define LIBERO_SETTING_WAY_MASK_DMA 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000ffff -#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000ffff -#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000000 +#define LIBERO_SETTING_WAY_MASK_DMA 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000f0ff +#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000f0ff +#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000004 #define LIBERO_SETTING_L2_SHUTDOWN_CR 0x00000000 -#define LIBERO_SETTING_WAY_ENABLE 0x00000007 +#define LIBERO_SETTING_WAY_ENABLE 0x0000000b #endif /* __BOARDS_RISCV_MPFS_M100PFSEVP_INCLUDE_BOARD_LIBERODEFS_H */