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arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

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This commit is contained in:
Gregory Nutt 2018-09-21 21:32:50 -06:00
parent 6632ac721e
commit 510b0f7e07
11 changed files with 22 additions and 22 deletions
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4
arch/arm/src/imxrt/imxrt_irq.c
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@ -406,11 +406,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/kinetis/kinetis_irq.c
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@ -347,11 +347,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/lc823450/lc823450_irq.c
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@ -467,8 +467,8 @@ void up_irqinitialize(void)
/* Disable all interrupts */ /* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE); putreg32(0xffffffff, NVIC_IRQ0_31_CLEAR);
putreg32(0, NVIC_IRQ32_63_ENABLE); putreg32(0xffffffff, NVIC_IRQ32_63_CLEAR);
/* Colorize the interrupt stack for debug purposes */ /* Colorize the interrupt stack for debug purposes */

4
arch/arm/src/lpc17xx/lpc17_irq.c
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@ -316,11 +316,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/sam34/sam_irq.c
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@ -378,11 +378,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/samd5e5/sam_irq.c
View File

@ -456,11 +456,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/samv7/sam_irq.c
View File

@ -374,11 +374,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/stm32f7/stm32_irq.c
View File

@ -408,11 +408,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/stm32h7/stm32_irq.c
View File

@ -433,11 +433,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/tiva/tiva_irq.c
View File

@ -386,11 +386,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default

4
arch/arm/src/xmc4/xmc4_irq.c
View File

@ -347,11 +347,11 @@ void up_irqinitialize(void)
* registers. * registers.
*/ */
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
i > 0; i > 0;
i--, regaddr += 4) i--, regaddr += 4)
{ {
putreg32(0, regaddr); putreg32(0xffffffff, regaddr);
} }
/* Make sure that we are using the correct vector table. The default /* Make sure that we are using the correct vector table. The default