Paging update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2869 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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4856091610
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@ -193,7 +193,17 @@
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/* Bits 11:9: Should be zero */
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#define PMD_FINE_TEX_MASK 0xfffff000 /* Bits 31:12: v5, Physical page */
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/* Level 2 Table Descriptor (PTE). -- All tables */
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/* Level 2 Table Descriptor (PTE). A section descriptor provides the base address
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* of a 1MB block of memory. The page table descriptors provide the base address of
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* a page table that contains second-level descriptors. There are two sizes of page
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* table:
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* - Coarse page tables have 256 entries, splitting the 1MB that the table
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* describes into 4KB blocks
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* - Fine/tiny page tables have 1024 entries, splitting the 1MB that the table
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* describes into 1KB blocks.
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*
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* The following definitions apply to all L2 tables:
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*/
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#define PTE_TYPE_MASK (3 << 0) /* Bits: 1:0: Type of mapping */
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#define PTE_TYPE_FAULT (0 << 0) /* None */
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@ -226,7 +236,9 @@
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#define PTE_SMALL_AP_URW_SRW (0xff << 4)
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#define PTE_SMALL_TEX_MASK 0xfffff000 /* Bits: 31:12: Physical page */
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/* Tiny page -- 1Kb */
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#define PTE_SMALL_NPAGES 256 /* 256 Coarse PTE's per section */
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/* Fine/Tiny page -- 1Kb */
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/* Bits: 1:0: Type of mapping */
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/* Bits: 3:2: Bufferable/cacheable */
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@ -238,6 +250,8 @@
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/* Bits: 9:6: Should be zero */
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#define PTE_TINY_TEX_MASK 0xfffffc00 /* Bits: 31:10: Physical page */
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#define PTE_TINY_NPAGES 1024 /* 1024 Tiny PTE's per section */
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/* Default MMU flags for memory and IO */
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#define MMU_MEMFLAGS \
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@ -253,9 +267,11 @@
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#define SECTION_SIZE (1 << 20) /* 1Mb */
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/* We place the page tables 16K below the beginning of .text. The
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* following value is assume to be the (virtual) start address of
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* .text.
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/* CP15 register c2 contains a pointer to the base address of a paged table in
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* physical memory. Only bits 14-31 of the page table address is retained there;
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* The full 30-bit address is formed by ORing in bits 2-13 or the virtual address
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* (MVA). As a consequence, the page table must be aligned to a 16Kb address in
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* physical memory and could require up to 16Kb of memory.
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*/
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#define PGTABLE_SIZE 0x00004000
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/arm/pg_macros.S
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* arch/arm/src/arm/pg_macros.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -41,6 +41,7 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/page.h>
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#include "arm.h"
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@ -48,11 +49,42 @@
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* Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifdef CONFIG_PAGING
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/* Sanity check -- we cannot be using a ROM page table and supporting on-
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* demand paging.
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*/
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# ifdef CONFIG_ARCH_ROMPGTABLE
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# error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE"
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# endif
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/* Create some friendly definitions to handle some differences between
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* small and tiny pages.
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*/
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# if CONFIG_PAGING_PAGESIZE == 1024
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# define PTE_NPAGES PTE_TINY_NPAGES
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# elif CONFIG_PAGING_PAGESIZE == 4096
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# define PTE_NPAGES PTE_SMALL_NPAGES
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# else
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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# endif
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#define PT_SIZE (PTE_NPAGES * 4)
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#endif /* CONFIG_PAGING */
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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/* Write one L2 entry for a coarse page table entry.
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#ifdef __ASSEMBLY
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/****************************************************************************
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* Name: wrpte_coarse
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*
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* Description:
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* Write one L2 entry for a coarse PTE.
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*
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* Inputs (unmodified):
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* ctab - Register containing the address of the coarse page table
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@ -61,9 +93,11 @@
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* mmuflags - the MMU flags to use in the mapping
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*
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* Scratch registers (modified): tmp1, tmp2
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*/
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*
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****************************************************************************/
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.macro wrl2coarse, ctab, paddr, vaddr, mmuflags, tmp1, tmp2
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#ifdef CONFIG_PAGING
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.macro wrpte_coarse, ctab, paddr, vaddr, mmuflags, tmp1, tmp2
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/* Get tmp1 = (paddr | mmuflags), the value to write into the table */
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@ -79,8 +113,13 @@
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str \tmp1, [\ctab, \tmp2, lsr #10]
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.endm
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#endif /* CONFIG_PAGING */
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/* Write one L1 entry for a coarse page table.
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/****************************************************************************
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* Name: wrpmd_coarse
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*
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* Description:
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* Write one L1 entry for a coarse page table.
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*
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* Inputs (unmodified unless noted):
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* paddr - Physical address of the section (modified)
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@ -88,9 +127,11 @@
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* mmuflags - MMU flags to use in the section mapping
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*
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* Scratch registers (modified): tmp1, tmp2, tmp3
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*/
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*
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****************************************************************************/
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.macro wrl1coarse, paddr, vaddr, mmuflags, tmp1, tmp2
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#ifdef CONFIG_PAGING
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.macro wrpmd_coarse, paddr, vaddr, mmuflags, tmp1, tmp2
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/* tmp1 = the base of the L1 page table */
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ldr \tmp1, =PGTABLE_BASE_VADDR
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@ -106,9 +147,14 @@
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lsr \tmp2, \vaddr, #20
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str \paddr, [\tmp1, \tmp2, lsl #2]
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.endm
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#endif /* CONFIG_PAGING */
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/* Write one coarse L1 entry and all assocated L2 entries for a
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* coarse page table.
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/****************************************************************************
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* Name: wr_coarse
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*
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* Description:
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* Write one coarse L1 entry and all assocated L2 entries for a coarse
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* page table.
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*
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* Inputs:
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* offset - coarse page table offset (unmodified)
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@ -120,8 +166,11 @@
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*
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* On return, paddr and vaddr refer to the beginning of the
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* next section.
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*/
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.macro wrcoarse, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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.macro wr_coarse, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
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/* tmp1 = address of L2 table; tmp2 = MMU flags */
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@ -132,14 +181,14 @@
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1:
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/* Write that L2 entry into the coarse page table */
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wrl2coarse \tmp1, \paddr, \vaddr, \tmp2, \tmp3, \tmp4
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wrpte_coarse \tmp1, \paddr, \vaddr, \tmp2, \tmp3, \tmp4
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/* Update the physical and virtual addresses that will
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* correspond to the next table entry.
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*/
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add \paddr, \paddr, #4096
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add \vaddr, \vaddr, #4096
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add \paddr, \paddr, #CONFIG_PAGING_PAGESIZE
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add \vaddr, \vaddr, #CONFIG_PAGING_PAGESIZE
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2:
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/* Check if all of the pages have been written. If not, then
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* loop and write the next entry.
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@ -156,12 +205,17 @@
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ldr \tmp1, =PGTABLE_COARSE_BASE_PADDR
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ldr \tmp2, =MMU_L1_VECTORFLAGS
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add \tmp1, \offset, \tmp1
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wrl1coarse \tmp1, \vaddr, \tmp2, \tmp3, \tmp4
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wrpmd_coarse \tmp1, \vaddr, \tmp2, \tmp3, \tmp4
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.endm
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#endif /* CONFIG_PAGING */
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/* Write several, contiguous coarse L1 page table entries (and all
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* associated L2 page table entries). As many entries will be
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* written as many as needed to span npages.
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/****************************************************************************
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* Name: wr_sections
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*
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* Description:
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* Write several, contiguous coarse L1 page table entries (and all
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* associated L2 page table entries). As many entries will be written as
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* many as needed to span npages.
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*
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* Inputs:
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* offset - coarse page table offset (modified)
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@ -170,28 +224,34 @@
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* npages - Number of pages to write in the section
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*
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* Scratch registers (modified): tmp1, tmp2, tmp3, tmp4, tmp5
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*/
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*
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****************************************************************************/
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.macro wrsections, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
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#ifdef CONFIG_PAGING
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.macro wr_sections, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
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b 2f
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1:
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/* Select the number of coarse, 4Kb pages to write in this section.
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* This number will be 256 unless there are fewer than 256 pages
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* remaining to be mapped.
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/* Select the number of pages to write in this section. This number
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* will be 256 for coarse page tables or 1024 for fine/tiny page
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* tables (unless the npages argument indicates that there are fewer
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* than pages remaining to be mapped).
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*/
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cmp \npages, #255 /* Check if <= 255 */
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movls \tmp1, \npages /* YES.. tmp1 = npages */
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movls \npages, #0 /* npages = 0 */
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movhi \tmp1, #256 /* NO.. tmp1 = 256 */
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subhi \npages, \npages, #256 /* npages -= 256 */
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cmp \npages, #(PTE_NPAGES-1) /* Check if npages < PTE_NPAGES */
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movls \tmp1, \npages /* YES.. tmp1 = npages */
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movls \npages, #0 /* npages = 0 */
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movhi \tmp1, #PTE_NPAGES /* NO.. tmp1 = PTE_NPAGES */
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subhi \npages, \npages, #PTE_NPAGES /* npages -= PTE_NPAGES */
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/* Write the L2 entries for this section */
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wrcoarse \offset, \paddr, \vaddr, \tmp1, \tmp1, \tmp2, \tmp3, \tmp4
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add \offset, \offset, #1024
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wr_coarse \offset, \paddr, \vaddr, \tmp1, \tmp1, \tmp2, \tmp3, \tmp4
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add \offset, \offset, #PT_SIZE
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2:
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cmp \npages, #0
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bne 1b
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.endm
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#endif /* CONFIG_PAGING */
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#endif /* __ASSEMBLY */
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#endif /* __ARCH_ARM_SRC_ARM_PG_MACROS_H */
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@ -173,18 +173,16 @@
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#define PGTABLE_BASE_PADDR DM320_SDRAM_PADDR
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#define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR
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#define PGTABLE_COARSE_BASE_PADDR (PGTABLE_BASE_PADDR+0x00000800)
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#define PGTABLE_COARSE_END_PADDR (PGTABLE_BASE_PADDR+0x00003000)
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#define PTTABLE_PERIPHERALS_PADDR (PGTABLE_BASE_PADDR+0x00003000)
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#define PGTABLE_COARSE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000)
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#define PGTABLE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000)
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#define PGTABLE_BASE_VADDR DM320_SDRAM_VADDR
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#define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR
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#define PGTABLE_COARSE_BASE_VADDR (PGTABLE_BASE_VADDR+0x00000800)
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#define PGTABLE_COARSE_END_VADDR (PGTABLE_BASE_VADDR+0x00003000)
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#define PTTABLE_PERIPHERALS_VADDR (PGTABLE_BASE_VADDR+0x00003000)
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#define PGTABLE_COARSE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000)
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#define PGTABLE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000)
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#define PGTBALE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR)
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#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
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@ -247,7 +247,7 @@
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#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_VBASE+0x00003000)
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#define PGTABLE_VEND (PGTABLE_VBASE+0x00004000)
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#define PGTBALE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE)
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#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/lpc313x/chip.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -48,6 +48,7 @@
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/* LPC313X Physical (unmapped) Memory Map */
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#define LPC313X_FIRST_PSECTION 0x00000000 /* Beginning of the physical address space */
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#define LPC313X_SHADOWSPACE_PSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
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/* 0x00001000-0xff027fff: Reserved */
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#define LPC313X_INTSRAM_PSECTION 0x11028000 /* Internal SRAM 0+1 192Kb */
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@ -78,6 +79,12 @@
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/* 0x60001000-0x6fffffff: Reserved */
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#define LPC313X_NAND_PSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
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/* 0x70000800-0xffffffff: Reserved */
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#ifdef CONDFIG_LPC313X_EXTNAND /* End of the physical address space */
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# define LPC313X_LAST_PSECTION (LPC313X_NAND_PSECTION + (1 << 20))
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#else
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# define LPC313X_LAST_PSECTION (LPC313X_INTC_PSECTION + (1 << 20))
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#endif
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/* APB0-4 Domain Offsets */
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#define LPC313X_APB0_EVNTRTR_OFFSET 0x00000000 /* Event Router */
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@ -204,6 +211,7 @@
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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# defined LPC313X_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */
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# define LPC313X_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
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# define LPC313X_INTSRAM_VSECTION 0x11028000 /* Internal SRAM 96Kb-192Kb */
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# define LPC313X_INTSRAM0_VADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
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@ -224,6 +232,12 @@
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# define LPC313X_EXTSDRAM0_VSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
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# define LPC313X_INTC_VSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
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# define LPC313X_NAND_VSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
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#
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# ifdef CONDFIG_LPC313X_EXTNAND /* End of the virtual address space */
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# define LPC313X_LAST_VSECTION (LPC313X_NAND_VSECTION + (1 << 20))
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# else
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# define LPC313X_LAST_VSECTION (LPC313X_INTC_VSECTION + (1 << 20))
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# endif
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#endif
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/* The boot logic will create a temporarily mapping based on where NuttX is
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@ -304,17 +318,17 @@
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* normal operation). We will reuse this memory for coarse page tables as follows:
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*/
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#define PGTABLE_COARSE_BASE_PADDR (PGTABLE_BASE_PADDR+0x00000800)
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#define PGTABLE_COARSE_END_PADDR (PGTABLE_BASE_PADDR+0x00003000)
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#define PTTABLE_PERIPHERALS_PADDR (PGTABLE_BASE_PADDR+0x00003000)
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#define PGTABLE_COARSE_POFFSET ((LPC313X_LAST_PSECTION >> 20) << 2)
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#define PGTABLE_COARSE_BASE_PADDR (PGTABLE_BASE_PADDR+PGTABLE_COARSE_POFFSET)
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#define PGTABLE_COARSE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000)
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#define PGTABLE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000)
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#define PGTABLE_COARSE_BASE_VADDR (PGTABLE_BASE_VADDR+0x00000800)
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#define PGTABLE_COARSE_END_VADDR (PGTABLE_BASE_VADDR+0x00003000)
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#define PTTABLE_PERIPHERALS_VADDR (PGTABLE_BASE_VADDR+0x00003000)
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#define PGTABLE_COARSE_VOFFSET ((LPC313X_LAST_VSECTION >>20) << 2)
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#define PGTABLE_COARSE_BASE_VADDR (PGTABLE_BASE_VADDR+PGTABLE_COARSE_VOFFSET)
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#define PGTABLE_COARSE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000)
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#define PGTABLE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000)
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#define PGTBALE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_TABLE_SIZE (4*256)
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#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR)
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#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
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