Xtensa: Add CPU1 start logic
This commit is contained in:
Gregory Nutt
parent
c1334048c5
commit
51fc3de40b
@ -35,7 +35,7 @@
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# The start-up, "head", file
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HEAD_ASRC =
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HEAD_ASRC = esp32_start.c
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# Common XTENSA files (arch/xtensa/src/common)
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@ -50,8 +50,9 @@ CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c
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# Configuration-dependent common XTENSA files
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# Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism
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# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize()
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# in xtensa_initialize.c. Then this stub would not be needed.
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# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to
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# up_netinitialize() in xtensa_initialize.c. Then this stub would not be
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# needed.
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ifneq ($(CONFIG_LX6_ETHERNET),y)
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ifeq ($(CONFIG_NET),y)
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@ -59,9 +60,15 @@ ifeq ($(CONFIG_NET),y)
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endif
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endif
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# Required LX6 files (arch/xtensa/src/lx6)
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# Required ESP32 files (arch/xtensa/src/lx6)
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CHIP_ASRCS =
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CHIP_CSRCS =
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# Configuration-dependent LX6 files
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# Configuration-dependent ESP32 files
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ifeq ($(CONFIG_SMP),y)
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#CMN_CSRCS += esp32_cpuindex.c esp32_cpustart.c esp32_cpupause.c
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#CMN_CSRCS += esp32_cpuidlestack.c
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CMN_CSRCS += esp32_cpustart.c
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endif
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220
arch/xtensa/src/esp32/esp32_cpustart.c
Normal file
220
arch/xtensa/src/esp32/esp32_cpustart.c
Normal file
@ -0,0 +1,220 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_cpustart.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/sched.h>
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#include "sched/sched.h"
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#include "xtensa.h"
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#ifdef CONFIG_SMP
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#warning REVISIT Need cpu_configure_region_protection() prototype
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void cpu_configure_region_protection(void);
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#warning REVISIT Need ets_set_appcpu_boot_addr() prototype
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void ets_set_appcpu_boot_addr(uint32_t);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static bool g_appcpu_started;
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static sem_t g_appcpu_interlock;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_registerdump
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****************************************************************************/
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#if 0 /* Was useful in solving some startup problems */
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static inline void xtensa_registerdump(FAR struct tcb_s *tcb)
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{
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_info("CPU%d:\n", up_cpu_index());
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/* Dump the startup registers */
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/* To be provided */
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}
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#else
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# define xtensa_registerdump(tcb)
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_start_handler
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*
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* Description:
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* This is the handler for SGI1. This handler simply returns from the
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* interrupt, restoring the state of the new task at the head of the ready
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* to run list.
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*
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* Input Parameters:
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* Standard interrupt handling
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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int xtensa_start_handler(int irq, FAR void *context)
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{
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FAR struct tcb_s *tcb;
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sinfo("CPU%d Started\n", up_cpu_index());
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/* Handle interlock*/
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g_appcpu_started = true;
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sem_post(&g_appcpu_interlock);
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/* Reset scheduler parameters */
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tcb = this_task();
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sched_resume_scheduler(tcb);
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/* Move CPU0 exception vectors to IRAM */
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asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start));
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/* Make page 0 access raise an exception */
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cpu_configure_region_protection();
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/* Dump registers so that we can see what is going to happen on return */
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xtensa_registerdump(tcb);
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/* Then switch contexts. This instantiates the exception context of the
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* tcb at the head of the assigned task list. In this case, this should
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* be the CPUs NULL task.
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*/
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up_restorestate(tcb->xcp.regs);
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return OK;
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}
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/****************************************************************************
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* Name: up_cpu_start
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*
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* Description:
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* In an SMP configution, only one CPU is initially active (CPU 0). System
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* initialization occurs on that single thread. At the completion of the
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* initialization of the OS, just before beginning normal multitasking,
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* the additional CPUs would be started by calling this function.
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*
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* Each CPU is provided the entry point to is IDLE task when started. A
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* TCB for each CPU's IDLE task has been initialized and placed in the
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* CPU's g_assignedtasks[cpu] list. Not stack has been alloced or
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* initialized.
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*
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* The OS initialization logic calls this function repeatedly until each
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* CPU has been started, 1 through (CONFIG_SMP_NCPUS-1).
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*
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* Input Parameters:
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* cpu - The index of the CPU being started. This will be a numeric
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* value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU
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* 0 is already active)
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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int up_cpu_start(int cpu)
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{
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DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
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if (!g_appcpu_started)
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{
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uint32_t regval;
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int ret;
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/* Start CPU1 */
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sinfo("Starting CPU%d\n", cpu);
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sem_init(&g_appcpu_interlock, 0, 0)
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regval = getreg32(DPORT_APPCPU_CTRL_B_REG);
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regval |= DPORT_APPCPU_CLKGATE_EN;
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putreg32(regval, DPORT_APPCPU_CTRL_B_REG);
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regval = getreg32(DPORT_APPCPU_CTRL_C_REG);
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regval ~= DPORT_APPCPU_RUNSTALL;
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putreg32(regval, DPORT_APPCPU_CTRL_C_REG);
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regval = getreg32(DPORT_APPCPU_CTRL_A_REG);
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regval |= DPORT_APPCPU_RESETTING;
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putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
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regval = getreg32(DPORT_APPCPU_CTRL_A_REG);
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regval &= ~DPORT_APPCPU_RESETTING;
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putreg32(regval, DPORT_APPCPU_CTRL_A_REG);
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/* Set the CPU1 start address */
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ets_set_appcpu_boot_addr((uint32_t)xtensa_start_handler);
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/* And way for the initial task to run on CPU1 */
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while (!app_cpu_started)
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{
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ret = sem_wait(&g_appcpu_interlock);
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if (ret < 0)
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{
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DEBUGASSERT(errno == EINTR);
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}
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}
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sem_destroy(&g_appcpu_interlock);
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}
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}
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#endif /* CONFIG_SMP */
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@ -66,20 +66,20 @@ void IRAM_ATTR __start()
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/* Kill the watchdog timer */
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regval = getreg32(RTC_CNTL_WDTCONFIG0_REG);
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regval ~= RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
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regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
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putreg32(regval, RTC_CNTL_WDTCONFIG0_REG);
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regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */
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regval ~= (1 << 14);
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regval &= ~(1 << 14);
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putreg32(regval, 0x6001f048);
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/* Make page 0 access raise an exception */
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cpu_configure_region_protection();
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/* Move exception vectors to IRAM */
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/* Move CPU0 exception vectors to IRAM */
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asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start));
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asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start));
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/* Set .bss to zero */
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