USB host drivers: Cannot take semaphores in cancel() method
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cde3fef581
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52720e9368
@ -2560,7 +2560,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
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if (chan->chreason == CHREASON_XFRC)
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{
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/* Set the request done reult */
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/* Set the request done result */
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chan->result = OK;
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}
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@ -2629,7 +2629,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
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/* For a BULK transfer, the hardware is capable of retrying
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* automatically on a NAK. However, this is not always
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* what we need to do. So we always halt the transfer and
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* return control to high level logic in the even of a NAK.
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* return control to high level logic in the event of a NAK.
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*/
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#if 1
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@ -2642,7 +2642,9 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
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efm32_chan_halt(priv, chidx, CHREASON_NAK);
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}
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/* Re-activate CTRL and BULK channels */
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/* Re-activate CTRL and BULK channels.
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* REVISIT: This can cause a lot of interrupts!
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*/
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else if (chan->eptype == EFM32_USB_EPTYPE_CTRL ||
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chan->eptype == EFM32_USB_EPTYPE_BULK)
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@ -3520,7 +3522,7 @@ static int efm32_gint_isr(int irq, FAR void *context)
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pending = efm32_getreg(EFM32_USB_GINTSTS);
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pending &= efm32_getreg(EFM32_USB_GINTMSK);
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/* Return from the interrupt when there are no furhter pending
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/* Return from the interrupt when there are no further pending
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* interrupts.
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*/
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@ -3531,7 +3533,6 @@ static int efm32_gint_isr(int irq, FAR void *context)
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/* Otherwise, process each pending, unmasked GINT interrupts */
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/* Handle the start of frame interrupt */
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#ifdef CONFIG_EFM32_OTGFS_SOFINTR
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@ -4705,12 +4706,10 @@ static int efm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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DEBUGASSERT(priv && chidx < EFM32_MAX_TX_FIFOS);
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chan = &priv->chan[chidx];
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/* We must have exclusive access to the USB host hardware and state structures.
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* And when we have that, we need to disable interrupts to avoid race conditions
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* with the asynchronous completion of the transfer being cancelled.
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/* We need to disable interrupts to avoid race conditions with the asynchronous
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* completion of the transfer being cancelled.
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*/
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efm32_takesem(&priv->exclsem);
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flags = irqsave();
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/* Halt the channel */
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@ -4760,7 +4759,6 @@ static int efm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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#endif
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irqrestore(flags);
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efm32_givesem(&priv->exclsem);
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return OK;
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}
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@ -4508,6 +4508,9 @@ static int lpc31_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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/* We must have exclusive access to the EHCI hardware and data structures. This
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* will prevent servicing any transfer completion events while we perform the
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* the cancellation, but will not prevent DMA-related race conditions.
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*
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* REVISIT: This won't work. This function must be callable from the interrupt
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* level.
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*/
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lpc31_takesem(&g_ehci.exclsem);
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@ -4335,6 +4335,9 @@ static int sam_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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/* We must have exclusive access to the EHCI hardware and data structures. This
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* will prevent servicing any transfer completion events while we perform the
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* the cancellation, but will not prevent DMA-related race conditions.
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*
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* REVISIT: This won't work. This function must be callable from the interrupt
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* level.
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*/
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sam_takesem(&g_ehci.exclsem);
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@ -2482,7 +2482,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
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if (chan->chreason == CHREASON_XFRC)
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{
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/* Set the request done reult */
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/* Set the request done result */
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chan->result = OK;
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}
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@ -2551,7 +2551,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
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/* For a BULK transfer, the hardware is capable of retrying
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* automatically on a NAK. However, this is not always
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* what we need to do. So we always halt the transfer and
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* return control to high level logic in the even of a NAK.
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* return control to high level logic in the event of a NAK.
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*/
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#if 1
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@ -2564,7 +2564,9 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
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stm32_chan_halt(priv, chidx, CHREASON_NAK);
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}
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/* Re-activate CTRL and BULK channels */
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/* Re-activate CTRL and BULK channels.
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* REVISIT: This can cause a lot of interrupts!
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*/
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else if (chan->eptype == OTGFS_EPTYPE_CTRL ||
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chan->eptype == OTGFS_EPTYPE_BULK)
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@ -3455,7 +3457,7 @@ static int stm32_gint_isr(int irq, FAR void *context)
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pending = stm32_getreg(STM32_OTGFS_GINTSTS);
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pending &= stm32_getreg(STM32_OTGFS_GINTMSK);
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/* Return from the interrupt when there are no furhter pending
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/* Return from the interrupt when there are no further pending
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* interrupts.
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*/
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@ -3466,7 +3468,6 @@ static int stm32_gint_isr(int irq, FAR void *context)
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/* Otherwise, process each pending, unmasked GINT interrupts */
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/* Handle the start of frame interrupt */
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#ifdef CONFIG_STM32_OTGFS_SOFINTR
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@ -4637,12 +4638,10 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS);
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chan = &priv->chan[chidx];
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/* We must have exclusive access to the USB host hardware and state structures.
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* And when we have that, we need to disable interrupts to avoid race conditions
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* with the asynchronous completion of the transfer being cancelled.
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/* We need to disable interrupts to avoid race conditions with the asynchronous
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* completion of the transfer being cancelled.
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*/
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stm32_takesem(&priv->exclsem);
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flags = irqsave();
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/* Halt the channel */
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@ -4692,7 +4691,6 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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#endif
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irqrestore(flags);
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stm32_givesem(&priv->exclsem);
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return OK;
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}
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@ -2482,7 +2482,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
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if (chan->chreason == CHREASON_XFRC)
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{
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/* Set the request done reult */
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/* Set the request done result */
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chan->result = OK;
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}
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@ -2551,7 +2551,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
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/* For a BULK transfer, the hardware is capable of retrying
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* automatically on a NAK. However, this is not always
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* what we need to do. So we always halt the transfer and
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* return control to high level logic in the even of a NAK.
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* return control to high level logic in the event of a NAK.
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*/
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#if 1
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@ -2564,7 +2564,9 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
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stm32_chan_halt(priv, chidx, CHREASON_NAK);
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}
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/* Re-activate CTRL and BULK channels */
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/* Re-activate CTRL and BULK channels.
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* REVISIT: This can cause a lot of interrupts!
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*/
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else if (chan->eptype == OTGHS_EPTYPE_CTRL ||
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chan->eptype == OTGHS_EPTYPE_BULK)
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@ -3455,7 +3457,7 @@ static int stm32_gint_isr(int irq, FAR void *context)
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pending = stm32_getreg(STM32_OTGHS_GINTSTS);
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pending &= stm32_getreg(STM32_OTGHS_GINTMSK);
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/* Return from the interrupt when there are no furhter pending
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/* Return from the interrupt when there are no further pending
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* interrupts.
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*/
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@ -3466,7 +3468,6 @@ static int stm32_gint_isr(int irq, FAR void *context)
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/* Otherwise, process each pending, unmasked GINT interrupts */
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/* Handle the start of frame interrupt */
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#ifdef CONFIG_STM32_OTGHS_SOFINTR
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@ -4637,12 +4638,10 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS);
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chan = &priv->chan[chidx];
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/* We must have exclusive access to the USB host hardware and state structures.
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* And when we have that, we need to disable interrupts to avoid race conditions
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* with the asynchronous completion of the transfer being cancelled.
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/* We need to disable interrupts to avoid race conditions with the asynchronous
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* completion of the transfer being cancelled.
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*/
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stm32_takesem(&priv->exclsem);
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flags = irqsave();
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/* Halt the channel */
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@ -4692,7 +4691,6 @@ static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
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#endif
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irqrestore(flags);
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stm32_givesem(&priv->exclsem);
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return OK;
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}
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