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arm64_sync_exc: Use temporaries x9/x10 instead of x0/x1

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Why? Because this allows optimizing the user system call path in such
a way that the parameter registers don't have to be read from the saved
integer register context when the system call is executed.
This commit is contained in:
Ville Juven 2024-08-13 11:54:11 +03:00 committed by Alan Carvalho de Assis
parent b27bf82b6e
commit 52781221b3
2 changed files with 10 additions and 9 deletions
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6
arch/arm64/src/common/arm64_vector_table.S
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@ -143,7 +143,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
/* Current EL with SP0 / Synchronous */ /* Current EL with SP0 / Synchronous */
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x9, x10
b arm64_sync_exc b arm64_sync_exc
/* Current EL with SP0 / IRQ */ /* Current EL with SP0 / IRQ */
@ -167,7 +167,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
/* Current EL with SPx / Synchronous */ /* Current EL with SPx / Synchronous */
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x9, x10
b arm64_sync_exc b arm64_sync_exc
/* Current EL with SPx / IRQ */ /* Current EL with SPx / IRQ */
@ -191,7 +191,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
/* Lower EL using AArch64 / Synchronous */ /* Lower EL using AArch64 / Synchronous */
.align 7 .align 7
arm64_enter_exception x0, x1 arm64_enter_exception x9, x10
b arm64_sync_exc b arm64_sync_exc
/* Lower EL using AArch64 / IRQ */ /* Lower EL using AArch64 / IRQ */

13
arch/arm64/src/common/arm64_vectors.S
View File

@ -187,18 +187,18 @@ SECTION_FUNC(text, arm64_sync_exc)
/* checking the EC value to see which exception need to be handle */ /* checking the EC value to see which exception need to be handle */
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 #if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
mrs x0, esr_el3 mrs x9, esr_el3
#else #else
mrs x0, esr_el1 mrs x9, esr_el1
#endif #endif
lsr x1, x0, #26 lsr x10, x9, #26
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
/* fpu trap */ /* fpu trap */
cmp x1, #0x07 /*Access to SIMD or floating-point */ cmp x10, #0x07 /* Access to SIMD or floating-point */
bne 1f bne 1f
mov x0, sp mov x0, sp /* x0 = context */
bl arm64_fpu_trap bl arm64_fpu_trap
/* when the fpu trap is handled */ /* when the fpu trap is handled */
@ -208,7 +208,7 @@ SECTION_FUNC(text, arm64_sync_exc)
#endif #endif
/* 0x15 = SVC system call */ /* 0x15 = SVC system call */
cmp x1, #0x15 cmp x10, #0x15
/* if this is a svc call ?*/ /* if this is a svc call ?*/
@ -248,6 +248,7 @@ SECTION_FUNC(text, arm64_sync_exc)
*/ */
mov x0, sp /* x0 = reg frame */ mov x0, sp /* x0 = reg frame */
/* Call arm64_syscall() on the user stack */ /* Call arm64_syscall() on the user stack */
bl arm64_syscall /* Call the handler */ bl arm64_syscall /* Call the handler */