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STM32 Ethernet, Slightly differ register layout for DM9161AEP PHY

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5177 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-09-22 19:19:56 +00:00
parent 3a818c18d2
commit 52877875b3
5 changed files with 164 additions and 46 deletions
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90
arch/arm/src/stm32/Kconfig
View File

@ -1684,6 +1684,7 @@ config SDIO_WIDTH_D1_ONLY
endmenu
if STM32_ETHMAC
menu "Ethernet MAC configuration"
config STM32_PHYADDR
@ -1695,7 +1696,6 @@ config STM32_PHYADDR
config STM32_MII
bool "Use MII interface"
default n
depends on STM32_ETHMAC
---help---
Support Ethernet MII interface.
@ -1734,14 +1734,13 @@ endchoice
config STM32_AUTONEG
bool "Use autonegotiation"
default y
depends on STM32_ETHMAC
---help---
Use PHY autonegotiation to determine speed and mode
config STM32_ETHFD
bool "Full duplex"
default n
depends on STM32_ETHMAC && !STM32_AUTONEG
depends on !STM32_AUTONEG
---help---
If STM32_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
@ -1749,61 +1748,104 @@ config STM32_ETHFD
config STM32_ETH100MBPS
bool "100 Mbps"
default n
depends on STM32_ETHMAC && !STM32_AUTONEG
depends on !STM32_AUTONEG
---help---
If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
config STM32_PHYSR
hex "PHY status register address"
int "PHY Status Register Address (decimal)"
depends on STM32_AUTONEG
---help---
This must be provided if STM32_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
config STM32_PHYSR_SPEED
hex "PHY speed mask"
config STM32_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on STM32_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config STM32_PHYSR_SPEED
hex "PHY Speed Mask"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provides bit mask
indicating 10 or 100MBps speed.
for isolating the 10 or 100MBps speed indication.
config STM32_PHYSR_100MBPS
hex "PHY 100Mbps speed value"
depends on STM32_AUTONEG
hex "PHY 100Mbps Speed Value"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config STM32_PHYSR_MODE
hex "PHY mode mask"
depends on STM32_AUTONEG
hex "PHY Mode Mask"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provide bit mask
indicating full or half duplex modes.
for isolating the full or half duplex mode bits.
config STM32_PHYSR_FULLDUPLEX
hex "PHY full duplex mode value"
depends on STM32_AUTONEG
hex "PHY Full Duplex Mode Value"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config STM32_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config STM32_PHYSR_10HD
hex "10MHz/Half Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config STM32_PHYSR_100HD
hex "100MHz/Half Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config STM32_PHYSR_10FD
hex "10MHz/Full Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config STM32_PHYSR_100FD
hex "100MHz/Full Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
config STM32_ETH_PTP
bool "Precision Time Protocol (PTP)"
default n
depends on STM32_ETHMAC
---help---
Precision Time Protocol (PTP). Not supported but some hooks are indicated
with this condition.
endmenu
config STM32_RMII
bool
default y if !STM32_MII
depends on STM32_ETHMAC
choice
prompt "RMII clock configuration"
@ -1837,6 +1879,16 @@ config STM32_RMII_EXTCLK
endchoice
config STM32_ETHMAC_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG.
endmenu
endif
menu "USB Host Configuration"
config STM32_OTGFS_RXFIFO_SIZE

81
arch/arm/src/stm32/stm32_eth.c
View File

@ -135,17 +135,35 @@
# ifndef CONFIG_STM32_PHYSR
# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_SPEED
# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_100MBPS
# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_MODE
# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX
# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# ifdef CONFIG_STM32_PHYSR_ALTCONFIG
# ifndef CONFIG_STM32_PHYSR_ALTMODE
# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_10HD
# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_100HD
# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_10FD
# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_100FD
# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration"
# endif
# else
# ifndef CONFIG_STM32_PHYSR_SPEED
# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_100MBPS
# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_MODE
# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX
# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# endif
# endif
#endif
@ -2552,6 +2570,46 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
/* Remember the selected speed and duplex modes */
nvdbg("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval);
/* Different PHYs present speed and mode information in different ways. IF
* This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that the PHY
* represents speed and mode information are combined, for example, with
* separate bits for 10HD, 100HD, 10FD and 100FD.
*/
#ifdef CONFIG_STM32_PHYSR_ALTCONFIG
switch (phyval & CONFIG_STM32_PHYSR_ALTMODE)
{
default:
case CONFIG_STM32_PHYSR_10HD:
priv->fduplex = 0;
priv->mbps100 = 0;
break;
case CONFIG_STM32_PHYSR_100HD:
priv->fduplex = 0;
priv->mbps100 = 1;
break;
case CONFIG_STM32_PHYSR_10FD:
priv->fduplex = 1;
priv->mbps100 = 0;
break;
case CONFIG_STM32_PHYSR_100FD:
priv->fduplex = 1;
priv->mbps100 = 1;
break;
}
/* Different PHYs present speed and mode information in different ways. Some
* will present separate information for speed and mode (this is the default).
* Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
* full/half duplex indication.
*/
#else
if ((phyval & CONFIG_STM32_PHYSR_MODE) == CONFIG_STM32_PHYSR_FULLDUPLEX)
{
priv->fduplex = 1;
@ -2561,6 +2619,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
{
priv->mbps100 = 1;
}
#endif
#else /* Auto-negotion not selected */

12
configs/olimex-stm32-p107/include/board.h
View File

@ -50,8 +50,6 @@
* Pre-processor Definitions
************************************************************************************/
#define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK
/* Clocking *************************************************************************/
/* On-board crystal frequency is 25MHz (HSE) */
@ -97,10 +95,14 @@
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
/* MCO output */
/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
*
* STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
*/
#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10
# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */
# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */
#endif
/************************************************************************************

13
configs/shenzhou/include/board.h
View File

@ -50,8 +50,6 @@
* Pre-processor Definitions
************************************************************************************/
#define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK
/* Clocking *************************************************************************/
/* On-board crystal frequency is 25MHz (HSE) */
@ -97,10 +95,14 @@
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
/* MCO output */
/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
*
* STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
*/
#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10
# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */
# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */
#endif
/* LED definitions ******************************************************************/
@ -179,6 +181,9 @@
* 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
* 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
*
* The board desdign can support a 50MHz external clock to drive the PHY
* (U9). However, on my board, U9 is not present.
*
* 67 PA8 MCO DM9161AEP
*/

14
configs/shenzhou/nsh/defconfig
View File

@ -174,14 +174,14 @@ CONFIG_STM32_JTAG_FULL_ENABLE=y
#
CONFIG_STM32_PHYADDR=1
# CONFIG_STM32_MII is not set
# CONFIG_STM32_MII_MCO is not set
# CONFIG_STM32_MII_EXTCLK is not set
CONFIG_STM32_AUTONEG=y
CONFIG_STM32_PHYSR=16
CONFIG_STM32_PHYSR_SPEED=0x0002
CONFIG_STM32_PHYSR_100MBPS=0x0000
CONFIG_STM32_PHYSR_MODE=0x0004
CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
CONFIG_STM32_PHYSR=17
CONFIG_STM32_PHYSR_ALTCONFIG=y
CONFIG_STM32_PHYSR_ALTMODE=0xf000
CONFIG_STM32_PHYSR_10HD=0x1000
CONFIG_STM32_PHYSR_100HD=0x4000
CONFIG_STM32_PHYSR_10FD=0x2000
CONFIG_STM32_PHYSR_100FD=0x8000
# CONFIG_STM32_ETH_PTP is not set
CONFIG_STM32_RMII=y
CONFIG_STM32_RMII_MCO=y